diff --git a/llvm/include/llvm/CodeGen/LiveRegMatrix.h b/llvm/include/llvm/CodeGen/LiveRegMatrix.h --- a/llvm/include/llvm/CodeGen/LiveRegMatrix.h +++ b/llvm/include/llvm/CodeGen/LiveRegMatrix.h @@ -104,19 +104,19 @@ /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). /// When there is more than one kind of interference, the InterferenceKind /// with the highest enum value is returned. - InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); + InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg); /// Check for interference in the segment [Start, End) that may prevent /// assignment to PhysReg. If this function returns true, there is /// interference in the segment [Start, End) of some other interval already /// assigned to PhysReg. If this function returns false, PhysReg is free at /// the segment [Start, End). - bool checkInterference(SlotIndex Start, SlotIndex End, unsigned PhysReg); + bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg); /// Assign VirtReg to PhysReg. /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and /// update VirtRegMap. The live range is expected to be available in PhysReg. - void assign(LiveInterval &VirtReg, unsigned PhysReg); + void assign(LiveInterval &VirtReg, MCRegister PhysReg); /// Unassign VirtReg from its PhysReg. /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes @@ -124,7 +124,7 @@ void unassign(LiveInterval &VirtReg); /// Returns true if the given \p PhysReg has any live intervals assigned. - bool isPhysRegUsed(unsigned PhysReg) const; + bool isPhysRegUsed(MCRegister PhysReg) const; //===--------------------------------------------------------------------===// // Low-level interface. @@ -136,18 +136,19 @@ /// Check for regmask interference only. /// Return true if VirtReg crosses a regmask operand that clobbers PhysReg. /// If PhysReg is null, check if VirtReg crosses any regmask operands. - bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0); + bool checkRegMaskInterference(LiveInterval &VirtReg, + MCRegister PhysReg = MCRegister::NoRegister); /// Check for regunit interference only. /// Return true if VirtReg overlaps a fixed assignment of one of PhysRegs's /// register units. - bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg); + bool checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg); /// Query a line of the assigned virtual register matrix directly. /// Use MCRegUnitIterator to enumerate all regunits in the desired PhysReg. /// This returns a reference to an internal Query data structure that is only /// valid until the next query() call. - LiveIntervalUnion::Query &query(const LiveRange &LR, unsigned RegUnit); + LiveIntervalUnion::Query &query(const LiveRange &LR, MCRegister RegUnit); /// Directly access the live interval unions per regunit. /// This returns an array indexed by the regunit number. diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -78,7 +78,7 @@ template static bool foreachUnit(const TargetRegisterInfo *TRI, - LiveInterval &VRegInterval, unsigned PhysReg, + LiveInterval &VRegInterval, MCRegister PhysReg, Callable Func) { if (VRegInterval.hasSubRanges()) { for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { @@ -101,7 +101,7 @@ return false; } -void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { +void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " << printReg(PhysReg, TRI) << ':'); assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment"); @@ -135,7 +135,7 @@ LLVM_DEBUG(dbgs() << '\n'); } -bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const { +bool LiveRegMatrix::isPhysRegUsed(MCRegister PhysReg) const { for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { if (!Matrix[*Unit].empty()) return true; @@ -144,7 +144,7 @@ } bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, - unsigned PhysReg) { + MCRegister PhysReg) { // Check if the cached information is valid. // The same BitVector can be reused for all PhysRegs. // We could cache multiple VirtRegs if it becomes necessary. @@ -162,7 +162,7 @@ } bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, - unsigned PhysReg) { + MCRegister PhysReg) { if (VirtReg.empty()) return false; CoalescerPair CP(VirtReg.reg(), PhysReg, *TRI); @@ -176,14 +176,14 @@ } LiveIntervalUnion::Query &LiveRegMatrix::query(const LiveRange &LR, - unsigned RegUnit) { + MCRegister RegUnit) { LiveIntervalUnion::Query &Q = Queries[RegUnit]; Q.init(UserTag, LR, Matrix[RegUnit]); return Q; } LiveRegMatrix::InterferenceKind -LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { +LiveRegMatrix::checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) { if (VirtReg.empty()) return IK_Free; @@ -197,9 +197,9 @@ // Check the matrix for virtual register interference. bool Interference = foreachUnit(TRI, VirtReg, PhysReg, - [&](unsigned Unit, const LiveRange &LR) { - return query(LR, Unit).checkInterference(); - }); + [&](MCRegister Unit, const LiveRange &LR) { + return query(LR, Unit).checkInterference(); + }); if (Interference) return IK_VirtReg; @@ -207,7 +207,7 @@ } bool LiveRegMatrix::checkInterference(SlotIndex Start, SlotIndex End, - unsigned PhysReg) { + MCRegister PhysReg) { // Construct artificial live range containing only one segment [Start, End). VNInfo valno(0, Start); LiveRange::Segment Seg(Start, End, &valno); diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h --- a/llvm/lib/CodeGen/RegAllocBase.h +++ b/llvm/lib/CodeGen/RegAllocBase.h @@ -101,8 +101,8 @@ // Each call must guarantee forward progess by returning an available PhysReg // or new set of split live virtual registers. It is up to the splitter to // converge quickly toward fully spilled live ranges. - virtual Register selectOrSplit(LiveInterval &VirtReg, - SmallVectorImpl &splitLVRs) = 0; + virtual MCRegister selectOrSplit(LiveInterval &VirtReg, + SmallVectorImpl &splitLVRs) = 0; // Use this group name for NamedRegionTimer. static const char TimerGroupName[]; diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -110,7 +110,7 @@ using VirtRegVec = SmallVector; VirtRegVec SplitVRegs; - unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); + MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); if (AvailablePhysReg == ~0u) { // selectOrSplit failed to find a register! diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -100,8 +100,8 @@ return LI; } - Register selectOrSplit(LiveInterval &VirtReg, - SmallVectorImpl &SplitVRegs) override; + MCRegister selectOrSplit(LiveInterval &VirtReg, + SmallVectorImpl &SplitVRegs) override; /// Perform register allocation. bool runOnMachineFunction(MachineFunction &mf) override; @@ -253,10 +253,10 @@ // |vregs| * |machineregs|. And since the number of interference tests is // minimal, there is no value in caching them outside the scope of // selectOrSplit(). -Register RABasic::selectOrSplit(LiveInterval &VirtReg, - SmallVectorImpl &SplitVRegs) { +MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg, + SmallVectorImpl &SplitVRegs) { // Populate a list of physical register spill candidates. - SmallVector PhysRegSpillCands; + SmallVector PhysRegSpillCands; // Check for an available register in this class. auto Order = @@ -281,8 +281,9 @@ } // Try to spill another interfering reg with less spill weight. - for (SmallVectorImpl::iterator PhysRegI = PhysRegSpillCands.begin(), - PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { + for (auto PhysRegI = PhysRegSpillCands.begin(), + PhysRegE = PhysRegSpillCands.end(); + PhysRegI != PhysRegE; ++PhysRegI) { if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue; diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -418,7 +418,8 @@ Spiller &spiller() override { return *SpillerInstance; } void enqueue(LiveInterval *LI) override; LiveInterval *dequeue() override; - Register selectOrSplit(LiveInterval&, SmallVectorImpl&) override; + MCRegister selectOrSplit(LiveInterval &, + SmallVectorImpl &) override; void aboutToRemoveInterval(LiveInterval &) override; /// Perform register allocation. @@ -432,8 +433,8 @@ static char ID; private: - Register selectOrSplitImpl(LiveInterval &, SmallVectorImpl &, - SmallVirtRegSet &, unsigned = 0); + MCRegister selectOrSplitImpl(LiveInterval &, SmallVectorImpl &, + SmallVirtRegSet &, unsigned = 0); bool LRE_CanEraseVirtReg(unsigned) override; void LRE_WillShrinkVirtReg(unsigned) override; @@ -459,8 +460,8 @@ void calcGapWeights(unsigned, SmallVectorImpl&); Register canReassign(LiveInterval &VirtReg, Register PrevReg); bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); - bool canEvictInterference(LiveInterval&, Register, bool, EvictionCost&, - const SmallVirtRegSet&); + bool canEvictInterference(LiveInterval &, MCRegister, bool, EvictionCost &, + const SmallVirtRegSet &); bool canEvictInterferenceInRange(LiveInterval &VirtReg, Register oPhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost); @@ -869,7 +870,7 @@ /// @param MaxCost Only look for cheaper candidates and update with new cost /// when returning true. /// @returns True when interference can be evicted cheaper than MaxCost. -bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, Register PhysReg, +bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) { // It is only possible to evict virtual register interference. @@ -2606,7 +2607,7 @@ SmallLISet RecoloringCandidates; // Record the original mapping virtual register to physical register in case // the recoloring fails. - DenseMap VirtRegToPhysReg; + DenseMap VirtRegToPhysReg; // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in // this recoloring "session". assert(!FixedRegisters.count(VirtReg.reg())); @@ -2701,7 +2702,7 @@ Register ItVirtReg = (*It)->reg(); if (VRM->hasPhys(ItVirtReg)) Matrix->unassign(**It); - Register ItPhysReg = VirtRegToPhysReg[ItVirtReg]; + MCRegister ItPhysReg = VirtRegToPhysReg[ItVirtReg]; Matrix->assign(**It, ItPhysReg); } } @@ -2725,8 +2726,8 @@ while (!RecoloringQueue.empty()) { LiveInterval *LI = dequeue(RecoloringQueue); LLVM_DEBUG(dbgs() << "Try to recolor: " << *LI << '\n'); - Register PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, - Depth + 1); + MCRegister PhysReg = + selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1); // When splitting happens, the live-range may actually be empty. // In that case, this is okay to continue the recoloring even // if we did not find an alternative color for it. Indeed, @@ -2753,12 +2754,12 @@ // Main Entry Point //===----------------------------------------------------------------------===// -Register RAGreedy::selectOrSplit(LiveInterval &VirtReg, - SmallVectorImpl &NewVRegs) { +MCRegister RAGreedy::selectOrSplit(LiveInterval &VirtReg, + SmallVectorImpl &NewVRegs) { CutOffInfo = CO_None; LLVMContext &Ctx = MF->getFunction().getContext(); SmallVirtRegSet FixedRegisters; - Register Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters); + MCRegister Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters); if (Reg == ~0U && (CutOffInfo != CO_None)) { uint8_t CutOffEncountered = CutOffInfo & (CO_Depth | CO_Interf); if (CutOffEncountered == CO_Depth) @@ -2902,7 +2903,7 @@ SmallVector RecoloringCandidates; HintsInfo Info; unsigned Reg = VirtReg.reg(); - Register PhysReg = VRM->getPhys(Reg); + MCRegister PhysReg = VRM->getPhys(Reg); // Start the recoloring algorithm from the input live-interval, then // it will propagate to the ones that are copy-related with it. Visited.insert(Reg); @@ -3014,10 +3015,10 @@ } } -Register RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, - SmallVectorImpl &NewVRegs, - SmallVirtRegSet &FixedRegisters, - unsigned Depth) { +MCRegister RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, + SmallVectorImpl &NewVRegs, + SmallVirtRegSet &FixedRegisters, + unsigned Depth) { unsigned CostPerUseLimit = ~0u; // First try assigning a free register. auto Order = @@ -3030,8 +3031,8 @@ // register. if (CSRCost.getFrequency() && isUnusedCalleeSavedReg(PhysReg) && NewVRegs.empty()) { - Register CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, - CostPerUseLimit, NewVRegs); + MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, + CostPerUseLimit, NewVRegs); if (CSRReg || !NewVRegs.empty()) // Return now if we decide to use a CSR or create new vregs due to // pre-splitting. diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp --- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -118,11 +118,11 @@ LRM->unassign(*Intervals[N]); for (unsigned N = 0; N < NumRegs; ++N) - if (LRM->checkInterference(*Intervals[N], StartReg + N)) + if (LRM->checkInterference(*Intervals[N], MCRegister::from(StartReg + N))) return false; for (unsigned N = 0; N < NumRegs; ++N) - LRM->assign(*Intervals[N], StartReg + N); + LRM->assign(*Intervals[N], MCRegister::from(StartReg + N)); return true; } @@ -273,7 +273,7 @@ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::vaddr0); SmallVector Intervals; - SmallVector OrigRegs; + SmallVector OrigRegs; SlotIndex MinInd, MaxInd; for (unsigned I = 0; I < Info->VAddrDwords; ++I) { const MachineOperand &Op = MI->getOperand(VAddr0Idx + I); diff --git a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp --- a/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp @@ -239,7 +239,8 @@ // Search for a register in Bank unused within LI. // Returns phys reg or NoRegister. - unsigned scavengeReg(LiveInterval &LI, unsigned Bank, unsigned SubReg) const; + MCRegister scavengeReg(LiveInterval &LI, unsigned Bank, + unsigned SubReg) const; // Try to reassign candidate. Returns number or stall cycles saved. unsigned tryReassign(Candidate &C); @@ -648,15 +649,15 @@ return TotalStallCycles; } -unsigned GCNRegBankReassign::scavengeReg(LiveInterval &LI, unsigned Bank, - unsigned SubReg) const { +MCRegister GCNRegBankReassign::scavengeReg(LiveInterval &LI, unsigned Bank, + unsigned SubReg) const { const TargetRegisterClass *RC = MRI->getRegClass(LI.reg()); unsigned MaxNumRegs = (Bank < NUM_VGPR_BANKS) ? MaxNumVGPRs : MaxNumSGPRs; unsigned MaxReg = MaxNumRegs + (Bank < NUM_VGPR_BANKS ? AMDGPU::VGPR0 : AMDGPU::SGPR0); - for (Register Reg : RC->getRegisters()) { + for (MCRegister Reg : RC->getRegisters()) { // Check occupancy limit. if (TRI->isSubRegisterEq(Reg, MaxReg)) break; @@ -667,7 +668,7 @@ for (unsigned I = 0; CSRegs[I]; ++I) if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && !LRM->isPhysRegUsed(CSRegs[I])) - return AMDGPU::NoRegister; + return MCRegister::from(AMDGPU::NoRegister); LLVM_DEBUG(dbgs() << "Trying register " << printReg(Reg) << '\n'); @@ -675,7 +676,7 @@ return Reg; } - return AMDGPU::NoRegister; + return MCRegister::from(AMDGPU::NoRegister); } unsigned GCNRegBankReassign::tryReassign(Candidate &C) { @@ -720,11 +721,11 @@ } llvm::sort(BankStalls); - Register OrigReg = VRM->getPhys(C.Reg); + MCRegister OrigReg = VRM->getPhys(C.Reg); LRM->unassign(LI); while (!BankStalls.empty()) { BankStall BS = BankStalls.pop_back_val(); - Register Reg = scavengeReg(LI, BS.Bank, C.SubReg); + MCRegister Reg = scavengeReg(LI, BS.Bank, C.SubReg); if (Reg == AMDGPU::NoRegister) { LLVM_DEBUG(dbgs() << "No free registers in bank " << printBank(BS.Bank) << '\n'); diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -104,7 +104,7 @@ LiveInterval &LI = LIS->getInterval(Reg); - for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { + for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { if (!MRI->isPhysRegUsed(PhysReg) && Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { Matrix->assign(LI, PhysReg);