Index: llvm/test/TableGen/sched-aliases.td =================================================================== --- /dev/null +++ llvm/test/TableGen/sched-aliases.td @@ -0,0 +1,50 @@ +// REQUIRES: aarch64-registered-target +// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/AArch64 -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s + +// Check that we've defined scheduling classes for FMOVv2f32_ns and FMOVv2f64 for Model0 +// CHECK: InstRW: New SC [[SC:[0-9]+]]:FMOVv2f32_ns on Model0 +// CHECK: InstRW: New SC [[SC2:[0-9]+]]:FMOVv2f64_ns on Model0 + +// Generic transition for WriteV should be defined for Model0/ProcFoo0 as well as for +// all instructions without explicitly defined scheduling classes. +// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices +// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices + +// Transition from FMOVv2f64_ns should still be added for Model0/ProcFoo0, +// even though we've defined custom scheduling class. +// CHECK: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices +// CHECK-NEXT: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices + +// Transition from FMOVv2f32_ns should not be added for Model0/ProcFoo0, +// because custom sched class for it is defined and it's not variant. +// CHECK-NOT: Adding transition from FMOVv2f32_ns([[SC]]) + +include "AArch64.td" + +def Model0 : SchedMachineModel { + let CompleteModel = 0; +} + +def Model0UnitV : ProcResource<1> { let BufferSize = 0; } + +let SchedModel = Model0 in { + +def Model0WriteV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; } +def Model0WriteV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; } +def Model0WriteV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; } + +def Model0QFormPred : MCSchedPredicate; +def Model0WriteV : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def : SchedAlias; + +def : InstRW<[Model0WriteV_1cyc], (instrs FMOVv2f32_ns)>; +def : InstRW<[WriteV], (instrs FMOVv2f64_ns)>; +} + +def ProcFoo0 : SubtargetFeature<"foo-0", "ARMProcFamily", "foo-0", + "Test Processor #1", []>; + +def : ProcessorModel<"foo-0-model", Model0, [ProcFoo0]>; Index: llvm/test/tools/llvm-mca/ARM/A57-basic-instructions.s =================================================================== --- /dev/null +++ llvm/test/tools/llvm-mca/ARM/A57-basic-instructions.s @@ -0,0 +1,2572 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=armv7 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s + + .text + adc r1, r2, #15 + adc r1, r2, #240 + adc r1, r2, #3840 + adc r1, r2, #61440 + adc r1, r2, #983040 + adc r1, r2, #15728640 + adc r1, r2, #251658240 + adc r1, r2, #-268435456 + adc r1, r2, #-268435441 + adc r7, r8, #-2147483638 + adc r7, r8, #40, #2 + adcs r1, r2, #3840 + adcs r7, r8, #40, #2 + adcseq r1, r2, #3840 + adceq r1, r2, #3840 + adc r4, r5, r6 + adc r4, r5, r6, lsl #1 + adc r4, r5, r6, lsl #31 + adc r4, r5, r6, lsr #1 + adc r4, r5, r6, lsr #31 + adc r4, r5, r6, lsr #32 + adc r4, r5, r6, asr #1 + adc r4, r5, r6, asr #31 + adc r4, r5, r6, asr #32 + adc r4, r5, r6, ror #1 + adc r4, r5, r6, ror #31 + adc r6, r7, r8, lsl r9 + adc r6, r7, r8, lsr r9 + adc r6, r7, r8, asr r9 + adc r6, r7, r8, ror r9 + adc r4, r5, r6, rrx + adc r5, r5, r6 + adc r4, r4, r5, lsl #1 + adc r4, r4, r5, lsl #31 + adc r4, r4, r5, lsr #1 + adc r4, r4, r5, lsr #31 + adc r4, r4, r5, lsr #32 + adc r4, r4, r5, asr #1 + adc r4, r4, r5, asr #31 + adc r4, r4, r5, asr #32 + adc r4, r4, r5, ror #1 + adc r4, r4, r5, ror #31 + adc r4, r4, r5, rrx + adc r6, r6, r7, lsl r9 + adc r6, r6, r7, lsr r9 + adc r6, r6, r7, asr r9 + adc r6, r6, r7, ror r9 + adc r4, r4, r5, rrx + add r4, r5, #61440 + add r7, r8, #-2147483638 + add r7, r8, #40, #2 + add r4, r5, r6 + add r4, r5, r6, lsl #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, asr #5 + add r4, r5, r6, ror #5 + add r6, r7, r8, lsl r9 + add r6, r7, r8, lsr r9 + add r6, r7, r8, asr r9 + add r6, r7, r8, ror r9 + add r4, r5, r6, rrx + add r5, r5, #61440 + add r4, r4, r5 + add r4, r4, r5, lsl #5 + add r4, r4, r5, lsr #5 + add r4, r4, r5, lsr #5 + add r4, r4, r5, asr #5 + add r4, r4, r5, ror #5 + add r6, r6, r7, lsl r9 + add r6, r6, r7, lsr r9 + add r6, r6, r7, asr r9 + add r6, r6, r7, ror r9 + add r4, r4, r5, rrx + adds r7, r8, #-2147483638 + adds r7, r8, #40, #2 + add r2, pc, #3 + sub r2, pc, #3 + sub r1, pc, #0 + sub r1, pc, #301989888 + add r1, pc, #301989888 + and r10, r1, #15 + and r7, r8, #-2147483638 + and r7, r8, #40, #2 + and r10, r1, r6 + and r10, r1, r6, lsl #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, asr #10 + and r10, r1, r6, ror #10 + and r6, r7, r8, lsl r2 + and r6, r7, r8, lsr r2 + and r6, r7, r8, asr r2 + and r6, r7, r8, ror r2 + and r10, r1, r6, rrx + and r1, r1, #15 + and r10, r10, r1 + and r10, r10, r1, lsl #10 + and r10, r10, r1, lsr #10 + and r10, r10, r1, lsr #10 + and r10, r10, r1, asr #10 + and r10, r10, r1, ror #10 + and r6, r6, r7, lsl r2 + and r6, r6, r7, lsr r2 + and r6, r6, r7, asr r2 + and r6, r6, r7, ror r2 + and r10, r10, r1, rrx + bfc r5, #3, #17 + bfclo r5, #3, #17 + bfi r5, r2, #3, #17 + bfine r5, r2, #3, #17 + bic r10, r1, #15 + bic r7, r8, #-2147483638 + bic r7, r8, #40, #2 + bic r10, r1, r6 + bic r10, r1, r6, lsl #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, asr #10 + bic r10, r1, r6, ror #10 + bic r6, r7, r8, lsl r2 + bic r6, r7, r8, lsr r2 + bic r6, r7, r8, asr r2 + bic r6, r7, r8, ror r2 + bic r10, r1, r6, rrx + bic r1, r1, #15 + bic r10, r10, r1 + bic r10, r10, r1, lsl #10 + bic r10, r10, r1, lsr #10 + bic r10, r10, r1, lsr #10 + bic r10, r10, r1, asr #10 + bic r10, r10, r1, ror #10 + bic r6, r6, r7, lsl r2 + bic r6, r6, r7, lsr r2 + bic r6, r6, r7, asr r2 + bic r6, r6, r7, ror r2 + bic r10, r10, r1, rrx + bkpt #10 + bkpt #65535 + blx r2 + blxne r2 + blx #32424576 + blx #16212288 + bx r2 + bxne r2 + bxj r2 + bxjne r2 + clrex + clz r1, r2 + clzeq r1, r2 + cmn r1, #15 + cmn r7, #40, #2 + cmn r7, #-2147483638 + cmn r1, r6 + cmn r1, r6, lsl #10 + cmn r1, r6, lsr #10 + cmn sp, r6, lsr #10 + cmn r1, r6, asr #10 + cmn r1, r6, ror #10 + cmn r7, r8, lsl r2 + cmn sp, r8, lsr r2 + cmn r7, r8, asr r2 + cmn r7, r8, ror r2 + cmn r1, r6, rrx + cmp r1, #15 + cmp r7, #40, #2 + cmp r7, #-2147483638 + cmp r1, r6 + cmp r1, r6, lsl #10 + cmp r1, r6, lsr #10 + cmp sp, r6, lsr #10 + cmp r1, r6, asr #10 + cmp r1, r6, ror #10 + cmp r7, r8, lsl r2 + cmp sp, r8, lsr r2 + cmp r7, r8, asr r2 + cmp r7, r8, ror r2 + cmp r1, r6, rrx + cpsie aif + cps #15 + cpsid if, #10 + cpsid af, #17 + cpsie f, #26 + dbg #0 + dbg #5 + dbg #15 + dmb #0x0 + dmb oshld + dmb oshst + dmb osh + dmb #0x4 + dmb nshld + dmb nshst + dmb nsh + dmb #0x8 + dmb ishld + dmb ishst + dmb ish + dmb #0xc + dmb ld + dmb st + dmb sy + ssbb + dsb oshld + dsb oshst + dsb osh + pssbb + dsb nshld + dsb nshst + dsb nsh + dsb #0x8 + dsb ishld + dsb ishst + dsb ish + dsb #0xc + dsb ld + dsb st + dsb sy + eor r4, r5, #61440 + eor r7, r8, #-2147483638 + eor r7, r8, #40, #2 + eor r4, r5, r6 + eor r4, r5, r6, lsl #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, asr #5 + eor r4, r5, r6, ror #5 + eor r6, r7, r8, lsl r9 + eor r6, r7, r8, lsr r9 + eor r6, r7, r8, asr r9 + eor r6, r7, r8, ror r9 + eor r4, r5, r6, rrx + eor r5, r5, #61440 + eor r4, r4, r5 + eor r4, r4, r5, lsl #5 + eor r4, r4, r5, lsr #5 + eor r4, r4, r5, lsr #5 + eor r4, r4, r5, asr #5 + eor r4, r4, r5, ror #5 + eor r6, r6, r7, lsl r9 + eor r6, r6, r7, lsr r9 + eor r6, r6, r7, asr r9 + eor r6, r6, r7, ror r9 + eor r4, r4, r5, rrx + isb sy + isb #0xa + ldm r2, {r1, r3, r4, r5, r6, sp} + ldmib r2, {r1, r3, r4, r5, r6, sp} + ldmda r2, {r1, r3, r4, r5, r6, sp} + ldmdb r2, {r1, r3, r4, r5, r6, sp} + ldm r2!, {r1, r3, r4, r5, r6, sp} + ldmib r2!, {r1, r3, r4, r5, r6, sp} + ldmda r2!, {r1, r3, r4, r5, r6, sp} + ldmdb r2!, {r1, r3, r4, r5, r6, sp} + ldrexb r3, [r4] + ldrexh r2, [r5] + ldrex r1, [r7] + ldrexd r6, r7, [r8] + mla r1, r2, r3, r4 + mlas r1, r2, r3, r4 + mlane r1, r2, r3, r4 + mlasne r1, r2, r3, r4 + mls r2, r5, r6, r3 + mlsne r2, r5, r6, r3 + mov r3, #7 + mov r4, #4080 + mov r5, #16711680 + mov sp, #35 + mov r9, #240, #30 + mov r7, #-2147483638 + mov pc, #2147483658 + movw r6, #65535 + movw r9, #65535 + movw sp, #1193 + movs r3, #7 + movs r11, #99 + movs r11, #240, #30 + moveq r4, #4080 + movseq r5, #16711680 + mov r2, r3 + movs r2, r3 + moveq r2, r3 + movseq r2, r3 + movt r3, #7 + movt r6, #65535 + movt sp, #3397 + movteq r4, #4080 + mrc p14, #0, r1, c1, c2, #4 + mrc p15, #7, apsr_nzcv, c15, c6, #6 + mrs r8, apsr + mrs r8, spsr + msr CPSR_fc, #5 + msr APSR_g, #5 + msr APSR_nzcvq, #5 + msr APSR_nzcvq, #5 + msr APSR_nzcvqg, #5 + msr CPSR_fc, #5 + msr CPSR_c, #5 + msr CPSR_x, #5 + msr CPSR_fc, #5 + msr CPSR_fc, #5 + msr CPSR_fsx, #5 + msr SPSR_fc, #5 + msr SPSR_fsxc, #5 + msr CPSR_fsxc, #5 + msr APSR_nzcvq, #2147483658 + msr SPSR_fsxc, #40, #2 + msr CPSR_fc, r0 + msr APSR_g, r0 + msr APSR_nzcvq, r0 + msr APSR_nzcvq, r0 + msr APSR_nzcvqg, r0 + msr CPSR_fc, r0 + msr CPSR_c, r0 + msr CPSR_x, r0 + msr CPSR_fc, r0 + msr CPSR_fc, r0 + msr CPSR_fsx, r0 + msr SPSR_fc, r0 + msr SPSR_fsxc, r0 + msr CPSR_fsxc, r0 + mul r5, r6, r7 + muls r5, r6, r7 + mulgt r5, r6, r7 + mulsle r5, r6, r7 + mvn r3, #7 + mvn r4, #4080 + mvn r5, #16711680 + mvn r7, #40, #2 + mvn r7, #-2147483638 + mvns r3, #7 + mvns r11, #240, #30 + mvns r11, #-2147483638 + mvneq r4, #4080 + mvnseq r5, #16711680 + mvn r2, r3 + mvns r2, r3 + mvn r5, r6, lsl #19 + mvn r5, r6, lsr #9 + mvn r5, r6, asr #4 + mvn r5, r6, ror #6 + mvn r5, r6, rrx + mvneq r2, r3 + mvnseq r2, r3, lsl #10 + mvn r5, r6, lsl r7 + mvns r5, r6, lsr r7 + mvngt r5, r6, asr r7 + mvnslt r5, r6, ror r7 + nop + nopgt + orr r4, r5, #61440 + orr r7, r8, #-2147483638 + orr r7, r8, #40, #2 + orr r4, r5, r6 + orr r4, r5, r6, lsl #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, asr #5 + orr r4, r5, r6, ror #5 + orr r6, r7, r8, lsl r9 + orr r6, r7, r8, lsr r9 + orr r6, r7, r8, asr r9 + orr r6, r7, r8, ror r9 + orr r4, r5, r6, rrx + orr r5, r5, #61440 + orr r4, r4, r5 + orr r4, r4, r5, lsl #5 + orr r4, r4, r5, lsr #5 + orr r4, r4, r5, lsr #5 + orr r4, r4, r5, asr #5 + orr r4, r4, r5, ror #5 + orr r6, r6, r7, lsl r9 + orr r6, r6, r7, lsr r9 + orr r6, r6, r7, asr r9 + orr r6, r6, r7, ror r9 + orr r4, r4, r5, rrx + orrseq r4, r5, #61440 + orrne r4, r5, r6 + orrseq r4, r5, r6, lsl #5 + orrlo r6, r7, r8, ror r9 + orrshi r4, r5, r6, rrx + orrhs r5, r5, #61440 + orrseq r4, r4, r5 + orrne r6, r6, r7, asr r9 + orrslt r6, r6, r7, ror r9 + orrsgt r4, r4, r5, rrx + pkhbt r2, r2, r3 + pkhbt r2, r2, r3, lsl #31 + pkhbt r2, r2, r3 + pkhbt r2, r2, r3, lsl #15 + pkhbt r2, r2, r3 + pkhtb r2, r2, r3, asr #31 + pkhtb r2, r2, r3, asr #15 + ldr r7, [sp], #4 + pop {r7, r8, r9, r10} + str r7, [sp, #-4]! + push {r7, r8, r9, r10} + qadd r1, r2, r3 + qaddne r1, r2, r3 + qadd16 r1, r2, r3 + qadd16gt r1, r2, r3 + qadd8 r1, r2, r3 + qadd8le r1, r2, r3 + qdadd r6, r7, r8 + qdaddhi r6, r7, r8 + qdsub r6, r7, r8 + qdsubhi r6, r7, r8 + qsax r9, r12, r0 + qsaxeq r9, r12, r0 + qsub r1, r2, r3 + qsubne r1, r2, r3 + qsub16 r1, r2, r3 + qsub16gt r1, r2, r3 + qsub8 r1, r2, r3 + qsub8le r1, r2, r3 + rbit r1, r2 + rbitne r1, r2 + rev r1, r9 + revne r1, r5 + rev16 r8, r3 + rev16ne r12, r4 + revsh r4, r9 + revshne r9, r1 + rfeda r2 + rfedb r3 + rfeia r5 + rfeib r6 + rfeda r4! + rfedb r7! + rfeia r9! + rfeib r8! + rfeda r2 + rfedb r3 + rfeia r5 + rfeib r6 + rfeda r4! + rfedb r7! + rfeia r9! + rfeib r8! + rfeia r1 + rfeia r1! + rsb r4, r5, #61440 + rsb r7, r8, #-2147483638 + rsb r7, r8, #40, #2 + rsb r4, r5, r6 + rsb r4, r5, r6, lsl #5 + rsblo r4, r5, r6, lsr #5 + rsb r4, r5, r6, lsr #5 + rsb r4, r5, r6, asr #5 + rsb r4, r5, r6, ror #5 + rsb r6, r7, r8, lsl r9 + rsb r6, r7, r8, lsr r9 + rsb r6, r7, r8, asr r9 + rsble r6, r7, r8, ror r9 + rsb r4, r5, r6, rrx + rsb r5, r5, #61440 + rsb r4, r4, r5 + rsb r4, r4, r5, lsl #5 + rsb r4, r4, r5, lsr #5 + rsbne r4, r4, r5, lsr #5 + rsb r4, r4, r5, asr #5 + rsb r4, r4, r5, ror #5 + rsbgt r6, r6, r7, lsl r9 + rsb r6, r6, r7, lsr r9 + rsb r6, r6, r7, asr r9 + rsb r6, r6, r7, ror r9 + rsb r4, r4, r5, rrx + rsbs r7, r8, #-2147483638 + rsbs r7, r8, #40, #2 + rsc r4, r5, #61440 + rsc r7, r8, #-2147483638 + rsc r7, r8, #40, #2 + rsc r4, r5, r6 + rsc r4, r5, r6, lsl #5 + rsclo r4, r5, r6, lsr #5 + rsc r4, r5, r6, lsr #5 + rsc r4, r5, r6, asr #5 + rsc r4, r5, r6, ror #5 + rsc r6, r7, r8, lsl r9 + rsc r6, r7, r8, lsr r9 + rsc r6, r7, r8, asr r9 + rscle r6, r7, r8, ror r9 + rsc r5, r5, #61440 + rsc r4, r4, r5 + rsc r4, r4, r5, lsl #5 + rsc r4, r4, r5, lsr #5 + rscne r4, r4, r5, lsr #5 + rsc r4, r4, r5, asr #5 + rsc r4, r4, r5, ror #5 + rscgt r6, r6, r7, lsl r9 + rsc r6, r6, r7, lsr r9 + rsc r6, r6, r7, asr r9 + rsc r6, r6, r7, ror r9 + rrx r0, r1 + rrx sp, pc + rrx pc, lr + rrx lr, sp + rrxs r0, r1 + rrxs sp, pc + rrxs pc, lr + rrxs lr, sp + sadd16 r1, r2, r3 + sadd16gt r1, r2, r3 + sadd8 r1, r2, r3 + sadd8le r1, r2, r3 + sasx r9, r12, r0 + sasxeq r9, r12, r0 + sbc r4, r5, #61440 + sbc r7, r8, #-2147483638 + sbc r7, r8, #40, #2 + sbc r4, r5, r6 + sbc r4, r5, r6, lsl #5 + sbc r4, r5, r6, lsr #5 + sbc r4, r5, r6, lsr #5 + sbc r4, r5, r6, asr #5 + sbc r4, r5, r6, ror #5 + sbc r6, r7, r8, lsl r9 + sbc r6, r7, r8, lsr r9 + sbc r6, r7, r8, asr r9 + sbc r6, r7, r8, ror r9 + sbc r5, r5, #61440 + sbc r4, r4, r5 + sbc r4, r4, r5, lsl #5 + sbc r4, r4, r5, lsr #5 + sbc r4, r4, r5, lsr #5 + sbc r4, r4, r5, asr #5 + sbc r4, r4, r5, ror #5 + sbc r6, r6, r7, lsl r9 + sbc r6, r6, r7, lsr r9 + sbc r6, r6, r7, asr r9 + sbc r6, r6, r7, ror r9 + sbfx r4, r5, #16, #1 + sbfxgt r4, r5, #16, #16 + sel r9, r2, r1 + selne r9, r2, r1 + setend be + setend le + sev + seveq + shadd16 r4, r8, r2 + shadd16gt r4, r8, r2 + shadd8 r4, r8, r2 + shadd8gt r4, r8, r2 + shasx r4, r8, r2 + shasxgt r4, r8, r2 + shsub16 r4, r8, r2 + shsub16gt r4, r8, r2 + shsub8 r4, r8, r2 + shsub8gt r4, r8, r2 + smlabb r3, r1, r9, r0 + smlabt r5, r6, r4, r1 + smlatb r4, r2, r3, r2 + smlatt r8, r3, r8, r4 + smlabbge r3, r1, r9, r0 + smlabtle r5, r6, r4, r1 + smlatbne r4, r2, r3, r2 + smlatteq r8, r3, r8, r4 + smlad r2, r3, r5, r8 + smladx r2, r3, r5, r8 + smladeq r2, r3, r5, r8 + smladxhi r2, r3, r5, r8 + smlal r2, r3, r5, r8 + smlals r2, r3, r5, r8 + smlaleq r2, r3, r5, r8 + smlalshi r2, r3, r5, r8 + smlalbb r3, r1, r9, r0 + smlalbt r5, r6, r4, r1 + smlaltb r4, r2, r3, r2 + smlaltt r8, r3, r8, r4 + smlalbbge r3, r1, r9, r0 + smlalbtle r5, r6, r4, r1 + smlaltbne r4, r2, r3, r2 + smlaltteq r8, r3, r8, r4 + smlald r2, r3, r5, r8 + smlaldx r2, r3, r5, r8 + smlaldeq r2, r3, r5, r8 + smlaldxhi r2, r3, r5, r8 + smlawb r2, r3, r10, r8 + smlawt r8, r3, r5, r9 + smlawbeq r2, r7, r5, r8 + smlawthi r1, r3, r0, r8 + smlsd r2, r3, r5, r8 + smlsdx r2, r3, r5, r8 + smlsdeq r2, r3, r5, r8 + smlsdxhi r2, r3, r5, r8 + smlsld r2, r9, r5, r1 + smlsldx r4, r11, r2, r8 + smlsldeq r8, r2, r5, r6 + smlsldxhi r1, r0, r3, r8 + smmla r1, r2, r3, r4 + smmlar r4, r3, r2, r1 + smmlalo r1, r2, r3, r4 + smmlarhs r4, r3, r2, r1 + smmls r1, r2, r3, r4 + smmlsr r4, r3, r2, r1 + smmlslo r1, r2, r3, r4 + smmlsrhs r4, r3, r2, r1 + smmul r2, r3, r4 + smmulr r3, r2, r1 + smmullo r2, r3, r4 + smmulrhs r3, r2, r1 + smuad r2, r3, r4 + smuadx r3, r2, r1 + smuadlt r2, r3, r4 + smuadxge r3, r2, r1 + smulbb r3, r9, r0 + smulbt r5, r4, r1 + smultb r4, r2, r2 + smultt r8, r3, r4 + smulbbge r1, r9, r0 + smulbtle r5, r6, r4 + smultbne r2, r3, r2 + smultteq r8, r3, r4 + smull r3, r9, r0, r1 + smulls r3, r9, r0, r2 + smulleq r8, r3, r4, r5 + smullseq r8, r3, r4, r3 + smulwb r3, r9, r0 + smulwt r3, r9, r2 + smusd r3, r0, r1 + smusdx r3, r9, r2 + smusdeq r8, r3, r2 + smusdxne r7, r4, r3 + srsda sp, #5 + srsdb sp, #1 + srsia sp, #0 + srsib sp, #15 + srsda sp!, #31 + srsdb sp!, #19 + srsia sp!, #2 + srsib sp!, #14 + srsda sp, #11 + srsdb sp, #10 + srsia sp, #9 + srsib sp, #5 + srsda sp!, #5 + srsdb sp!, #5 + srsia sp!, #5 + srsib sp!, #5 + srsia sp, #5 + srsia sp!, #5 + ssat r8, #1, r10 + ssat r8, #1, r10, lsl #31 + ssat r8, #1, r10, asr #32 + ssat r8, #1, r10, asr #1 + ssat16 r2, #1, r7 + ssat16 r3, #16, r5 + ssax r2, r3, r4 + ssaxlt r2, r3, r4 + ssub16 r1, r0, r6 + ssub16ne r5, r3, r2 + ssub8 r9, r2, r4 + ssub8eq r5, r1, r2 + stm r2, {r1, r3, r4, r5, r6, sp} + stm r3, {r1, r3, r4, r5, r6, lr} + stmib r4, {r1, r3, r4, r5, r6, sp} + stmda r5, {r1, r3, r4, r5, r6, sp} + stmdb r6, {r1, r3, r4, r5, r6, r8} + stmdb sp, {r1, r3, r4, r5, r6, sp} + stm r8!, {r1, r3, r4, r5, r6, sp} + stmib r9!, {r1, r3, r4, r5, r6, sp} + stmda sp!, {r1, r3, r4, r5, r6} + stmdb r0!, {r1, r5, r7, sp} + strexb r1, r3, [r4] + strexh r4, r2, [r5] + strex r2, r1, [r7] + strexd r6, r2, r3, [r8] + strexd sp, r0, r1, [r0] + sub r4, r5, #61440 + sub r7, r8, #-2147483638 + sub r7, r8, #40, #2 + sub r4, r5, r6 + sub r4, r5, r6, lsl #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, asr #5 + sub r4, r5, r6, ror #5 + sub r6, r7, r8, lsl r9 + sub r6, r7, r8, lsr r9 + sub r6, r7, r8, asr r9 + sub r6, r7, r8, ror r9 + sub r5, r5, #61440 + sub r4, r4, r5 + sub r4, r4, r5, lsl #5 + sub r4, r4, r5, lsr #5 + sub r4, r4, r5, lsr #5 + sub r4, r4, r5, asr #5 + sub r4, r4, r5, ror #5 + sub r6, r6, r7, lsl r9 + sub r6, r6, r7, lsr r9 + sub r6, r6, r7, asr r9 + sub r6, r6, r7, ror r9 + subs r7, r8, #-2147483638 + subs r7, r8, #40, #2 + svc #16 + svc #0 + svc #16777215 + sxtab r2, r3, r4 + sxtab r4, r5, r6 + sxtablt r6, r2, r9, ror #8 + sxtab r5, r1, r4, ror #16 + sxtab r7, r8, r3, ror #24 + sxtab16ge r0, r1, r4 + sxtab16 r6, r2, r7 + sxtab16 r3, r5, r8, ror #8 + sxtab16 r3, r2, r1, ror #16 + sxtab16eq r1, r2, r3, ror #24 + sxtah r1, r3, r9 + sxtahhi r6, r1, r6 + sxtah r3, r8, r3, ror #8 + sxtahlo r2, r2, r4, ror #16 + sxtah r9, r3, r3, ror #24 + sxtbge r2, r4 + sxtb r5, r6 + sxtb r6, r9, ror #8 + sxtblo r5, r1, ror #16 + sxtb r8, r3, ror #24 + sxtb16 r1, r4 + sxtb16 r6, r7 + sxtb16hs r3, r5, ror #8 + sxtb16 r3, r1, ror #16 + sxtb16ge r2, r3, ror #24 + sxthne r3, r9 + sxth r1, r6 + sxth r3, r8, ror #8 + sxthle r2, r2, ror #16 + sxth r9, r3, ror #24 + teq r5, #61440 + teq r7, #-2147483638 + teq r7, #40, #2 + teq r4, r5 + teq r4, r5, lsl #5 + teq r4, r5, lsr #5 + teq r4, r5, lsr #5 + teq r4, r5, asr #5 + teq r4, r5, ror #5 + teq r6, r7, lsl r9 + teq r6, r7, lsr r9 + teq r6, r7, asr r9 + teq r6, r7, ror r9 + tst r5, #61440 + tst r7, #-2147483638 + tst r7, #40, #2 + tst r4, r5 + tst r4, r5, lsl #5 + tst r4, r5, lsr #5 + tst r4, r5, lsr #5 + tst r4, r5, asr #5 + tst r4, r5, ror #5 + tst r6, r7, lsl r9 + tst r6, r7, lsr r9 + tst r6, r7, asr r9 + tst r6, r7, ror r9 + uadd16 r1, r2, r3 + uadd16gt r1, r2, r3 + uadd8 r1, r2, r3 + uadd8le r1, r2, r3 + uasx r9, r12, r0 + uasxeq r9, r12, r0 + ubfx r4, r5, #16, #1 + ubfxgt r4, r5, #16, #16 + uhadd16 r4, r8, r2 + uhadd16gt r4, r8, r2 + uhadd8 r4, r8, r2 + uhadd8gt r4, r8, r2 + uhasx r4, r8, r2 + uhasxgt r4, r8, r2 + uhsub16 r4, r8, r2 + uhsub16gt r4, r8, r2 + uhsub8 r4, r8, r2 + uhsub8gt r4, r8, r2 + umaal r3, r4, r5, r6 + umaallt r3, r4, r5, r6 + umlal r2, r4, r6, r8 + umlalgt r6, r1, r2, r6 + umlals r2, r9, r2, r3 + umlalseq r3, r5, r1, r2 + umull r2, r4, r6, r8 + umullgt r6, r1, r2, r6 + umulls r2, r9, r2, r3 + umullseq r3, r5, r1, r2 + uqadd16 r1, r2, r3 + uqadd16gt r4, r7, r9 + uqadd8 r3, r4, r8 + uqadd8le r8, r1, r2 + uqasx r2, r4, r1 + uqasxhi r5, r2, r9 + uqsax r1, r3, r7 + uqsax r3, r6, r2 + uqsub16 r1, r5, r3 + uqsub16gt r3, r2, r5 + uqsub8 r2, r1, r4 + uqsub8le r4, r6, r9 + usad8 r2, r1, r4 + usad8le r4, r6, r9 + usada8 r1, r5, r3, r7 + usada8gt r3, r2, r5, r1 + usat r8, #1, r10 + usat r8, #4, r10 + usat r8, #5, r10, lsl #31 + usat r8, #31, r10, asr #32 + usat r8, #16, r10, asr #1 + usat16 r2, #2, r7 + usat16 r3, #15, r5 + usax r2, r3, r4 + usaxne r2, r3, r4 + usub16 r4, r2, r7 + usub16hi r1, r1, r3 + usub8 r1, r8, r5 + usub8le r9, r2, r3 + uxtab r2, r3, r4 + uxtab r4, r5, r6 + uxtablt r6, r2, r9, ror #8 + uxtab r5, r1, r4, ror #16 + uxtab r7, r8, r3, ror #24 + uxtab16ge r0, r1, r4 + uxtab16 r6, r2, r7 + uxtab16 r3, r5, r8, ror #8 + uxtab16 r3, r2, r1, ror #16 + uxtab16eq r1, r2, r3, ror #24 + uxtah r1, r3, r9 + uxtahhi r6, r1, r6 + uxtah r3, r8, r3, ror #8 + uxtahlo r2, r2, r4, ror #16 + uxtah r9, r3, r3, ror #24 + uxtbge r2, r4 + uxtb r5, r6 + uxtb r6, r9, ror #8 + uxtblo r5, r1, ror #16 + uxtb r8, r3, ror #24 + uxtb16 r1, r4 + uxtb16 r6, r7 + uxtb16hs r3, r5, ror #8 + uxtb16 r3, r1, ror #16 + uxtb16ge r2, r3, ror #24 + uxthne r3, r9 + uxth r1, r6 + uxth r3, r8, ror #8 + uxthle r2, r2, ror #16 + uxth r9, r3, ror #24 + wfe + wfehi + wfi + wfilt + yield + yieldne + sevl + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #15 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #240 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #3840 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #61440 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #983040 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #15728640 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #251658240 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #-268435456 +# CHECK-NEXT: 1 1 0.50 adc r1, r2, #-268435441 +# CHECK-NEXT: 1 1 0.50 adc r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 adc r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 adcs r1, r2, #3840 +# CHECK-NEXT: 1 1 0.50 adcs r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 adcseq r1, r2, #3840 +# CHECK-NEXT: 1 1 0.50 adceq r1, r2, #3840 +# CHECK-NEXT: 1 1 0.50 adc r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, lsl #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, lsl #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, lsr #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, lsr #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, lsr #32 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, asr #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, asr #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, asr #32 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, ror #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, ror #31 +# CHECK-NEXT: 1 2 1.00 adc r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 adc r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 adc r5, r5, r6 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, lsl #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, lsl #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, lsr #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, lsr #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, lsr #32 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, asr #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, asr #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, asr #32 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, ror #1 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, ror #31 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, rrx +# CHECK-NEXT: 1 2 1.00 adc r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 adc r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 adc r4, r4, r5, rrx +# CHECK-NEXT: 1 1 0.50 add r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 add r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 add r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 add r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 add r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 add r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 add r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 add r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 add r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 add r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 add r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 add r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 add r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 add r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 add r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 add r4, r4, r5, rrx +# CHECK-NEXT: 1 1 0.50 adds r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 adds r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 adr r2, #3 +# CHECK-NEXT: 1 1 0.50 sub r2, pc, #3 +# CHECK-NEXT: 1 1 0.50 sub r1, pc, #0 +# CHECK-NEXT: 1 1 0.50 sub r1, pc, #301989888 +# CHECK-NEXT: 1 1 0.50 adr r1, #301989888 +# CHECK-NEXT: 1 1 0.50 and r10, r1, #15 +# CHECK-NEXT: 1 1 0.50 and r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 and r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 and r10, r1, r6 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, lsl #10 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, asr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, ror #10 +# CHECK-NEXT: 1 2 1.00 and r6, r7, r8, lsl r2 +# CHECK-NEXT: 1 2 1.00 and r6, r7, r8, lsr r2 +# CHECK-NEXT: 1 2 1.00 and r6, r7, r8, asr r2 +# CHECK-NEXT: 1 2 1.00 and r6, r7, r8, ror r2 +# CHECK-NEXT: 1 2 1.00 and r10, r1, r6, rrx +# CHECK-NEXT: 1 1 0.50 and r1, r1, #15 +# CHECK-NEXT: 1 1 0.50 and r10, r10, r1 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, lsl #10 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, lsr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, lsr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, asr #10 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, ror #10 +# CHECK-NEXT: 1 2 1.00 and r6, r6, r7, lsl r2 +# CHECK-NEXT: 1 2 1.00 and r6, r6, r7, lsr r2 +# CHECK-NEXT: 1 2 1.00 and r6, r6, r7, asr r2 +# CHECK-NEXT: 1 2 1.00 and r6, r6, r7, ror r2 +# CHECK-NEXT: 1 2 1.00 and r10, r10, r1, rrx +# CHECK-NEXT: 1 2 1.00 bfc r5, #3, #17 +# CHECK-NEXT: 1 2 1.00 bfclo r5, #3, #17 +# CHECK-NEXT: 1 2 1.00 bfi r5, r2, #3, #17 +# CHECK-NEXT: 1 2 1.00 bfine r5, r2, #3, #17 +# CHECK-NEXT: 1 1 0.50 bic r10, r1, #15 +# CHECK-NEXT: 1 1 0.50 bic r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 bic r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 bic r10, r1, r6 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, lsl #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, asr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, ror #10 +# CHECK-NEXT: 1 2 1.00 bic r6, r7, r8, lsl r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r7, r8, lsr r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r7, r8, asr r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r7, r8, ror r2 +# CHECK-NEXT: 1 2 1.00 bic r10, r1, r6, rrx +# CHECK-NEXT: 1 1 0.50 bic r1, r1, #15 +# CHECK-NEXT: 1 1 0.50 bic r10, r10, r1 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, lsl #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, lsr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, lsr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, asr #10 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, ror #10 +# CHECK-NEXT: 1 2 1.00 bic r6, r6, r7, lsl r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r6, r7, lsr r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r6, r7, asr r2 +# CHECK-NEXT: 1 2 1.00 bic r6, r6, r7, ror r2 +# CHECK-NEXT: 1 2 1.00 bic r10, r10, r1, rrx +# CHECK-NEXT: 0 0 0.00 U bkpt #10 +# CHECK-NEXT: 0 0 0.00 U bkpt #65535 +# CHECK-NEXT: 2 2 1.00 blx r2 +# CHECK-NEXT: 2 2 1.00 blxne r2 +# CHECK-NEXT: 2 1 1.00 U blx #32424576 +# CHECK-NEXT: 2 1 1.00 U blx #16212288 +# CHECK-NEXT: 1 1 1.00 U bx r2 +# CHECK-NEXT: 1 1 1.00 U bxne r2 +# CHECK-NEXT: 1 1 1.00 U bxj r2 +# CHECK-NEXT: 1 1 1.00 U bxjne r2 +# CHECK-NEXT: 0 0 0.00 * * U clrex +# CHECK-NEXT: 1 1 0.50 clz r1, r2 +# CHECK-NEXT: 1 1 0.50 clzeq r1, r2 +# CHECK-NEXT: 1 1 0.50 cmn r1, #15 +# CHECK-NEXT: 1 1 0.50 cmn r7, #40, #2 +# CHECK-NEXT: 1 1 0.50 cmn r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 cmn r1, r6 +# CHECK-NEXT: 1 2 1.00 cmn r1, r6, lsl #10 +# CHECK-NEXT: 1 2 1.00 cmn r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 cmn sp, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 cmn r1, r6, asr #10 +# CHECK-NEXT: 1 2 1.00 cmn r1, r6, ror #10 +# CHECK-NEXT: 1 2 1.00 cmn r7, r8, lsl r2 +# CHECK-NEXT: 1 2 1.00 cmn sp, r8, lsr r2 +# CHECK-NEXT: 1 2 1.00 cmn r7, r8, asr r2 +# CHECK-NEXT: 1 2 1.00 cmn r7, r8, ror r2 +# CHECK-NEXT: 1 2 1.00 cmn r1, r6, rrx +# CHECK-NEXT: 1 1 0.50 cmp r1, #15 +# CHECK-NEXT: 1 1 0.50 cmp r7, #40, #2 +# CHECK-NEXT: 1 1 0.50 cmp r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 cmp r1, r6 +# CHECK-NEXT: 1 2 1.00 cmp r1, r6, lsl #10 +# CHECK-NEXT: 1 2 1.00 cmp r1, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 cmp sp, r6, lsr #10 +# CHECK-NEXT: 1 2 1.00 cmp r1, r6, asr #10 +# CHECK-NEXT: 1 2 1.00 cmp r1, r6, ror #10 +# CHECK-NEXT: 1 2 1.00 cmp r7, r8, lsl r2 +# CHECK-NEXT: 1 2 1.00 cmp sp, r8, lsr r2 +# CHECK-NEXT: 1 2 1.00 cmp r7, r8, asr r2 +# CHECK-NEXT: 1 2 1.00 cmp r7, r8, ror r2 +# CHECK-NEXT: 1 2 1.00 cmp r1, r6, rrx +# CHECK-NEXT: 0 0 0.00 U cpsie aif +# CHECK-NEXT: 0 0 0.00 U cps #15 +# CHECK-NEXT: 0 0 0.00 U cpsid if, #10 +# CHECK-NEXT: 0 0 0.00 U cpsid af, #17 +# CHECK-NEXT: 0 0 0.00 U cpsie f, #26 +# CHECK-NEXT: 0 0 0.00 * * U dbg #0 +# CHECK-NEXT: 0 0 0.00 * * U dbg #5 +# CHECK-NEXT: 0 0 0.00 * * U dbg #15 +# CHECK-NEXT: 0 0 0.00 * * U dmb #0x0 +# CHECK-NEXT: 0 0 0.00 * * U dmb oshld +# CHECK-NEXT: 0 0 0.00 * * U dmb oshst +# CHECK-NEXT: 0 0 0.00 * * U dmb osh +# CHECK-NEXT: 0 0 0.00 * * U dmb #0x4 +# CHECK-NEXT: 0 0 0.00 * * U dmb nshld +# CHECK-NEXT: 0 0 0.00 * * U dmb nshst +# CHECK-NEXT: 0 0 0.00 * * U dmb nsh +# CHECK-NEXT: 0 0 0.00 * * U dmb #0x8 +# CHECK-NEXT: 0 0 0.00 * * U dmb ishld +# CHECK-NEXT: 0 0 0.00 * * U dmb ishst +# CHECK-NEXT: 0 0 0.00 * * U dmb ish +# CHECK-NEXT: 0 0 0.00 * * U dmb #0xc +# CHECK-NEXT: 0 0 0.00 * * U dmb ld +# CHECK-NEXT: 0 0 0.00 * * U dmb st +# CHECK-NEXT: 0 0 0.00 * * U dmb sy +# CHECK-NEXT: 0 0 0.00 * * U ssbb +# CHECK-NEXT: 0 0 0.00 * * U dsb oshld +# CHECK-NEXT: 0 0 0.00 * * U dsb oshst +# CHECK-NEXT: 0 0 0.00 * * U dsb osh +# CHECK-NEXT: 0 0 0.00 * * U pssbb +# CHECK-NEXT: 0 0 0.00 * * U dsb nshld +# CHECK-NEXT: 0 0 0.00 * * U dsb nshst +# CHECK-NEXT: 0 0 0.00 * * U dsb nsh +# CHECK-NEXT: 0 0 0.00 * * U dsb #0x8 +# CHECK-NEXT: 0 0 0.00 * * U dsb ishld +# CHECK-NEXT: 0 0 0.00 * * U dsb ishst +# CHECK-NEXT: 0 0 0.00 * * U dsb ish +# CHECK-NEXT: 0 0 0.00 * * U dsb #0xc +# CHECK-NEXT: 0 0 0.00 * * U dsb ld +# CHECK-NEXT: 0 0 0.00 * * U dsb st +# CHECK-NEXT: 0 0 0.00 * * U dsb sy +# CHECK-NEXT: 1 1 0.50 eor r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 eor r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 eor r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 eor r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 eor r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 eor r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 eor r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 eor r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 eor r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 eor r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 eor r4, r4, r5, rrx +# CHECK-NEXT: 0 0 0.00 * * U isb sy +# CHECK-NEXT: 0 0 0.00 * * U isb #0xa +# CHECK-NEXT: 16 10 16.00 * ldm r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 16 10 16.00 * ldmib r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 16 10 16.00 * ldmda r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 16 10 16.00 * ldmdb r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 32 10 16.00 * ldm r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 32 10 16.00 * ldmib r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 32 10 16.00 * ldmda r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 32 10 16.00 * ldmdb r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 0 0 0.00 * * U ldrexb r3, [r4] +# CHECK-NEXT: 0 0 0.00 * * U ldrexh r2, [r5] +# CHECK-NEXT: 0 0 0.00 * * U ldrex r1, [r7] +# CHECK-NEXT: 0 0 0.00 * U ldrexd r6, r7, [r8] +# CHECK-NEXT: 1 3 1.00 mla r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 mlas r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 mlane r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 mlasne r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 mls r2, r5, r6, r3 +# CHECK-NEXT: 1 3 1.00 mlsne r2, r5, r6, r3 +# CHECK-NEXT: 1 1 0.50 mov r3, #7 +# CHECK-NEXT: 1 1 0.50 mov r4, #4080 +# CHECK-NEXT: 1 1 0.50 mov r5, #16711680 +# CHECK-NEXT: 1 1 0.50 mov sp, #35 +# CHECK-NEXT: 1 1 0.50 mov r9, #240, #30 +# CHECK-NEXT: 1 1 0.50 mov r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 mov pc, #2147483658 +# CHECK-NEXT: 1 1 0.50 movw r6, #65535 +# CHECK-NEXT: 1 1 0.50 movw r9, #65535 +# CHECK-NEXT: 1 1 0.50 movw sp, #1193 +# CHECK-NEXT: 1 1 0.50 movs r3, #7 +# CHECK-NEXT: 1 1 0.50 movs r11, #99 +# CHECK-NEXT: 1 1 0.50 movs r11, #240, #30 +# CHECK-NEXT: 1 1 0.50 moveq r4, #4080 +# CHECK-NEXT: 1 1 0.50 movseq r5, #16711680 +# CHECK-NEXT: 1 1 0.50 mov r2, r3 +# CHECK-NEXT: 1 1 0.50 movs r2, r3 +# CHECK-NEXT: 1 1 0.50 moveq r2, r3 +# CHECK-NEXT: 1 1 0.50 movseq r2, r3 +# CHECK-NEXT: 1 2 1.00 movt r3, #7 +# CHECK-NEXT: 1 2 1.00 movt r6, #65535 +# CHECK-NEXT: 1 2 1.00 movt sp, #3397 +# CHECK-NEXT: 1 2 1.00 movteq r4, #4080 +# CHECK-NEXT: 0 0 0.00 * * U mrc p14, #0, r1, c1, c2, #4 +# CHECK-NEXT: 0 0 0.00 * * U mrc p15, #7, apsr_nzcv, c15, c6, #6 +# CHECK-NEXT: 0 0 0.00 U mrs r8, apsr +# CHECK-NEXT: 0 0 0.00 U mrs r8, spsr +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, #5 +# CHECK-NEXT: 0 0 0.00 U msr APSR_g, #5 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #5 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #5 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvqg, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_c, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_x, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fsx, #5 +# CHECK-NEXT: 0 0 0.00 U msr SPSR_fc, #5 +# CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, #5 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fsxc, #5 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, #2147483658 +# CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, #40, #2 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, r0 +# CHECK-NEXT: 0 0 0.00 U msr APSR_g, r0 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, r0 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvq, r0 +# CHECK-NEXT: 0 0 0.00 U msr APSR_nzcvqg, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_c, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_x, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fc, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fsx, r0 +# CHECK-NEXT: 0 0 0.00 U msr SPSR_fc, r0 +# CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, r0 +# CHECK-NEXT: 0 0 0.00 U msr CPSR_fsxc, r0 +# CHECK-NEXT: 1 3 1.00 mul r5, r6, r7 +# CHECK-NEXT: 1 3 1.00 muls r5, r6, r7 +# CHECK-NEXT: 1 3 1.00 mulgt r5, r6, r7 +# CHECK-NEXT: 1 3 1.00 mulsle r5, r6, r7 +# CHECK-NEXT: 1 1 0.50 mvn r3, #7 +# CHECK-NEXT: 1 1 0.50 mvn r4, #4080 +# CHECK-NEXT: 1 1 0.50 mvn r5, #16711680 +# CHECK-NEXT: 1 1 0.50 mvn r7, #40, #2 +# CHECK-NEXT: 1 1 0.50 mvn r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 mvns r3, #7 +# CHECK-NEXT: 1 1 0.50 mvns r11, #240, #30 +# CHECK-NEXT: 1 1 0.50 mvns r11, #-2147483638 +# CHECK-NEXT: 1 1 0.50 mvneq r4, #4080 +# CHECK-NEXT: 1 1 0.50 mvnseq r5, #16711680 +# CHECK-NEXT: 1 1 0.50 mvn r2, r3 +# CHECK-NEXT: 1 1 0.50 mvns r2, r3 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, lsl #19 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, lsr #9 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, asr #4 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, ror #6 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 mvneq r2, r3 +# CHECK-NEXT: 1 1 0.50 mvnseq r2, r3, lsl #10 +# CHECK-NEXT: 1 1 0.50 mvn r5, r6, lsl r7 +# CHECK-NEXT: 1 1 0.50 mvns r5, r6, lsr r7 +# CHECK-NEXT: 1 1 0.50 mvngt r5, r6, asr r7 +# CHECK-NEXT: 1 1 0.50 mvnslt r5, r6, ror r7 +# CHECK-NEXT: 0 0 0.00 * * U nop +# CHECK-NEXT: 0 0 0.00 * * U nopgt +# CHECK-NEXT: 1 1 0.50 orr r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 orr r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 orr r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 orr r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 orr r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 orr r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 orr r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 orr r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 orr r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 orr r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 orr r4, r4, r5, rrx +# CHECK-NEXT: 1 1 0.50 orrseq r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 orrne r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 orrseq r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 orrlo r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 orrshi r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 orrhs r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 orrseq r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 orrne r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 orrslt r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 orrsgt r4, r4, r5, rrx +# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3 +# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3, lsl #31 +# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3 +# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3, lsl #15 +# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3 +# CHECK-NEXT: 1 2 1.00 pkhtb r2, r2, r3, asr #31 +# CHECK-NEXT: 1 2 1.00 pkhtb r2, r2, r3, asr #15 +# CHECK-NEXT: 2 4 1.00 * pop {r7} +# CHECK-NEXT: 32 10 16.00 * pop {r7, r8, r9, r10} +# CHECK-NEXT: 2 1 1.00 * push {r7} +# CHECK-NEXT: 2 2 1.00 * push {r7, r8, r9, r10} +# CHECK-NEXT: 1 2 1.00 U qadd r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qaddne r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qadd16 r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qadd16gt r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qadd8 r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qadd8le r1, r2, r3 +# CHECK-NEXT: 2 3 1.00 U qdadd r6, r7, r8 +# CHECK-NEXT: 2 3 1.00 U qdaddhi r6, r7, r8 +# CHECK-NEXT: 2 3 1.00 U qdsub r6, r7, r8 +# CHECK-NEXT: 2 3 1.00 U qdsubhi r6, r7, r8 +# CHECK-NEXT: 2 3 1.00 qsax r9, r12, r0 +# CHECK-NEXT: 2 3 1.00 qsaxeq r9, r12, r0 +# CHECK-NEXT: 1 2 1.00 U qsub r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qsubne r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qsub16 r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qsub16gt r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qsub8 r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 U qsub8le r1, r2, r3 +# CHECK-NEXT: 1 1 0.50 rbit r1, r2 +# CHECK-NEXT: 1 1 0.50 rbitne r1, r2 +# CHECK-NEXT: 1 1 0.50 rev r1, r9 +# CHECK-NEXT: 1 1 0.50 revne r1, r5 +# CHECK-NEXT: 1 1 0.50 rev16 r8, r3 +# CHECK-NEXT: 1 1 0.50 rev16ne r12, r4 +# CHECK-NEXT: 1 1 0.50 revsh r4, r9 +# CHECK-NEXT: 1 1 0.50 revshne r9, r1 +# CHECK-NEXT: 0 0 0.00 U rfeda r2 +# CHECK-NEXT: 0 0 0.00 U rfedb r3 +# CHECK-NEXT: 0 0 0.00 U rfeia r5 +# CHECK-NEXT: 0 0 0.00 U rfeib r6 +# CHECK-NEXT: 0 0 0.00 U rfeda r4! +# CHECK-NEXT: 0 0 0.00 U rfedb r7! +# CHECK-NEXT: 0 0 0.00 U rfeia r9! +# CHECK-NEXT: 0 0 0.00 U rfeib r8! +# CHECK-NEXT: 0 0 0.00 U rfeda r2 +# CHECK-NEXT: 0 0 0.00 U rfedb r3 +# CHECK-NEXT: 0 0 0.00 U rfeia r5 +# CHECK-NEXT: 0 0 0.00 U rfeib r6 +# CHECK-NEXT: 0 0 0.00 U rfeda r4! +# CHECK-NEXT: 0 0 0.00 U rfedb r7! +# CHECK-NEXT: 0 0 0.00 U rfeia r9! +# CHECK-NEXT: 0 0 0.00 U rfeib r8! +# CHECK-NEXT: 0 0 0.00 U rfeia r1 +# CHECK-NEXT: 0 0 0.00 U rfeia r1! +# CHECK-NEXT: 1 1 0.50 rsb r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 rsb r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 rsb r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 U rsb r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 rsblo r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 rsble r6, r7, r8, ror r9 +# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, rrx +# CHECK-NEXT: 1 1 0.50 rsb r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 U rsb r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsbne r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 rsbgt r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, ror r9 +# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, rrx +# CHECK-NEXT: 1 1 0.50 rsbs r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 rsbs r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 rsc r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 rsc r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 rsc r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 U rsc r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 rsc r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 rsclo r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 rscle r6, r7, r8, ror r9 +# CHECK-NEXT: 1 1 0.50 rsc r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 U rsc r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 rscne r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 rscgt r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, ror r9 +# CHECK-NEXT: 1 1 0.50 rrx r0, r1 +# CHECK-NEXT: 1 1 0.50 rrx sp, pc +# CHECK-NEXT: 1 1 0.50 rrx pc, lr +# CHECK-NEXT: 1 1 0.50 rrx lr, sp +# CHECK-NEXT: 1 1 0.50 rrxs r0, r1 +# CHECK-NEXT: 1 1 0.50 rrxs sp, pc +# CHECK-NEXT: 1 1 0.50 rrxs pc, lr +# CHECK-NEXT: 1 1 0.50 rrxs lr, sp +# CHECK-NEXT: 2 2 1.00 * * U sadd16 r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U sadd16gt r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U sadd8 r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U sadd8le r1, r2, r3 +# CHECK-NEXT: 2 3 1.00 * * U sasx r9, r12, r0 +# CHECK-NEXT: 2 3 1.00 * * U sasxeq r9, r12, r0 +# CHECK-NEXT: 1 1 0.50 sbc r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 sbc r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 sbc r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 sbc r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 sbc r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 sbc r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r7, r8, ror r9 +# CHECK-NEXT: 1 1 0.50 sbc r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 sbc r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 sbc r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 sbc r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 sbc r6, r6, r7, ror r9 +# CHECK-NEXT: 1 1 0.50 U sbfx r4, r5, #16, #1 +# CHECK-NEXT: 1 1 0.50 U sbfxgt r4, r5, #16, #16 +# CHECK-NEXT: 1 1 0.50 * sel r9, r2, r1 +# CHECK-NEXT: 1 1 0.50 * selne r9, r2, r1 +# CHECK-NEXT: 0 0 0.00 U setend be +# CHECK-NEXT: 0 0 0.00 U setend le +# CHECK-NEXT: 0 0 0.00 * * U sev +# CHECK-NEXT: 0 0 0.00 * * U seveq +# CHECK-NEXT: 1 2 1.00 shadd16 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shadd16gt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shadd8 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shadd8gt r4, r8, r2 +# CHECK-NEXT: 2 3 1.00 shasx r4, r8, r2 +# CHECK-NEXT: 2 3 1.00 shasxgt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shsub16 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shsub16gt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shsub8 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 shsub8gt r4, r8, r2 +# CHECK-NEXT: 1 3 1.00 smlabb r3, r1, r9, r0 +# CHECK-NEXT: 1 3 1.00 smlabt r5, r6, r4, r1 +# CHECK-NEXT: 1 3 1.00 smlatb r4, r2, r3, r2 +# CHECK-NEXT: 1 3 1.00 smlatt r8, r3, r8, r4 +# CHECK-NEXT: 1 3 1.00 smlabbge r3, r1, r9, r0 +# CHECK-NEXT: 1 3 1.00 smlabtle r5, r6, r4, r1 +# CHECK-NEXT: 1 3 1.00 smlatbne r4, r2, r3, r2 +# CHECK-NEXT: 1 3 1.00 smlatteq r8, r3, r8, r4 +# CHECK-NEXT: 1 3 1.00 smlad r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smladx r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smladeq r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smladxhi r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlal r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlals r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlaleq r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlalshi r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlalbb r3, r1, r9, r0 +# CHECK-NEXT: 2 4 2.00 smlalbt r5, r6, r4, r1 +# CHECK-NEXT: 2 4 2.00 smlaltb r4, r2, r3, r2 +# CHECK-NEXT: 2 4 2.00 smlaltt r8, r3, r8, r4 +# CHECK-NEXT: 2 4 2.00 smlalbbge r3, r1, r9, r0 +# CHECK-NEXT: 2 4 2.00 smlalbtle r5, r6, r4, r1 +# CHECK-NEXT: 2 4 2.00 smlaltbne r4, r2, r3, r2 +# CHECK-NEXT: 2 4 2.00 smlaltteq r8, r3, r8, r4 +# CHECK-NEXT: 2 4 2.00 smlald r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlaldx r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlaldeq r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlaldxhi r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smlawb r2, r3, r10, r8 +# CHECK-NEXT: 1 3 1.00 smlawt r8, r3, r5, r9 +# CHECK-NEXT: 1 3 1.00 smlawbeq r2, r7, r5, r8 +# CHECK-NEXT: 1 3 1.00 smlawthi r1, r3, r0, r8 +# CHECK-NEXT: 1 3 1.00 smlsd r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smlsdx r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smlsdeq r2, r3, r5, r8 +# CHECK-NEXT: 1 3 1.00 smlsdxhi r2, r3, r5, r8 +# CHECK-NEXT: 2 4 2.00 smlsld r2, r9, r5, r1 +# CHECK-NEXT: 2 4 2.00 smlsldx r4, r11, r2, r8 +# CHECK-NEXT: 2 4 2.00 smlsldeq r8, r2, r5, r6 +# CHECK-NEXT: 2 4 2.00 smlsldxhi r1, r0, r3, r8 +# CHECK-NEXT: 1 3 1.00 smmla r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmlar r4, r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smmlalo r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmlarhs r4, r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 U smmls r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmlsr r4, r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 U smmlslo r1, r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmlsrhs r4, r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smmul r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmulr r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smmullo r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smmulrhs r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smuad r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smuadx r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smuadlt r2, r3, r4 +# CHECK-NEXT: 1 3 1.00 smuadxge r3, r2, r1 +# CHECK-NEXT: 1 3 1.00 smulbb r3, r9, r0 +# CHECK-NEXT: 1 3 1.00 smulbt r5, r4, r1 +# CHECK-NEXT: 1 3 1.00 smultb r4, r2, r2 +# CHECK-NEXT: 1 3 1.00 smultt r8, r3, r4 +# CHECK-NEXT: 1 3 1.00 smulbbge r1, r9, r0 +# CHECK-NEXT: 1 3 1.00 smulbtle r5, r6, r4 +# CHECK-NEXT: 1 3 1.00 smultbne r2, r3, r2 +# CHECK-NEXT: 1 3 1.00 smultteq r8, r3, r4 +# CHECK-NEXT: 2 4 2.00 smull r3, r9, r0, r1 +# CHECK-NEXT: 2 4 2.00 smulls r3, r9, r0, r2 +# CHECK-NEXT: 2 4 2.00 smulleq r8, r3, r4, r5 +# CHECK-NEXT: 2 4 2.00 smullseq r8, r3, r4, r3 +# CHECK-NEXT: 1 3 1.00 smulwb r3, r9, r0 +# CHECK-NEXT: 1 3 1.00 smulwt r3, r9, r2 +# CHECK-NEXT: 1 3 1.00 smusd r3, r0, r1 +# CHECK-NEXT: 1 3 1.00 smusdx r3, r9, r2 +# CHECK-NEXT: 1 3 1.00 smusdeq r8, r3, r2 +# CHECK-NEXT: 1 3 1.00 smusdxne r7, r4, r3 +# CHECK-NEXT: 0 0 0.00 U srsda sp, #5 +# CHECK-NEXT: 0 0 0.00 U srsdb sp, #1 +# CHECK-NEXT: 0 0 0.00 U srsia sp, #0 +# CHECK-NEXT: 0 0 0.00 U srsib sp, #15 +# CHECK-NEXT: 0 0 0.00 U srsda sp!, #31 +# CHECK-NEXT: 0 0 0.00 U srsdb sp!, #19 +# CHECK-NEXT: 0 0 0.00 U srsia sp!, #2 +# CHECK-NEXT: 0 0 0.00 U srsib sp!, #14 +# CHECK-NEXT: 0 0 0.00 U srsda sp, #11 +# CHECK-NEXT: 0 0 0.00 U srsdb sp, #10 +# CHECK-NEXT: 0 0 0.00 U srsia sp, #9 +# CHECK-NEXT: 0 0 0.00 U srsib sp, #5 +# CHECK-NEXT: 0 0 0.00 U srsda sp!, #5 +# CHECK-NEXT: 0 0 0.00 U srsdb sp!, #5 +# CHECK-NEXT: 0 0 0.00 U srsia sp!, #5 +# CHECK-NEXT: 0 0 0.00 U srsib sp!, #5 +# CHECK-NEXT: 0 0 0.00 U srsia sp, #5 +# CHECK-NEXT: 0 0 0.00 U srsia sp!, #5 +# CHECK-NEXT: 1 2 1.00 ssat r8, #1, r10 +# CHECK-NEXT: 1 2 1.00 ssat r8, #1, r10, lsl #31 +# CHECK-NEXT: 1 2 1.00 ssat r8, #1, r10, asr #32 +# CHECK-NEXT: 1 2 1.00 ssat r8, #1, r10, asr #1 +# CHECK-NEXT: 1 2 1.00 ssat16 r2, #1, r7 +# CHECK-NEXT: 1 2 1.00 ssat16 r3, #16, r5 +# CHECK-NEXT: 2 3 1.00 * * U ssax r2, r3, r4 +# CHECK-NEXT: 2 3 1.00 * * U ssaxlt r2, r3, r4 +# CHECK-NEXT: 2 2 1.00 * * U ssub16 r1, r0, r6 +# CHECK-NEXT: 2 2 1.00 * * U ssub16ne r5, r3, r2 +# CHECK-NEXT: 2 2 1.00 * * U ssub8 r9, r2, r4 +# CHECK-NEXT: 2 2 1.00 * * U ssub8eq r5, r1, r2 +# CHECK-NEXT: 1 2 1.00 * stm r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 1 2 1.00 * stm r3, {r1, r3, r4, r5, r6, lr} +# CHECK-NEXT: 1 2 1.00 * stmib r4, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 1 2 1.00 * stmda r5, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 1 2 1.00 * stmdb r6, {r1, r3, r4, r5, r6, r8} +# CHECK-NEXT: 1 2 1.00 * stmdb sp, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 2 2 1.00 * stm r8!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 2 2 1.00 * stmib r9!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: 2 2 1.00 * stmda sp!, {r1, r3, r4, r5, r6} +# CHECK-NEXT: 2 2 1.00 * stmdb r0!, {r1, r5, r7, sp} +# CHECK-NEXT: 0 0 0.00 * * U strexb r1, r3, [r4] +# CHECK-NEXT: 0 0 0.00 * * U strexh r4, r2, [r5] +# CHECK-NEXT: 0 0 0.00 * * U strex r2, r1, [r7] +# CHECK-NEXT: 0 0 0.00 * U strexd r6, r2, r3, [r8] +# CHECK-NEXT: 0 0 0.00 * U strexd sp, r0, r1, [r0] +# CHECK-NEXT: 1 1 0.50 sub r4, r5, #61440 +# CHECK-NEXT: 1 1 0.50 sub r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 sub r7, r8, #40, #2 +# CHECK-NEXT: 1 1 0.50 sub r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 sub r4, r5, r6, lsl #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r5, r6, lsr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r5, r6, asr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r5, r6, ror #5 +# CHECK-NEXT: 1 2 1.00 sub r6, r7, r8, lsl r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r7, r8, lsr r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r7, r8, asr r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r7, r8, ror r9 +# CHECK-NEXT: 1 1 0.50 sub r5, r5, #61440 +# CHECK-NEXT: 1 1 0.50 sub r4, r4, r5 +# CHECK-NEXT: 1 2 1.00 sub r4, r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 sub r4, r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 sub r6, r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 sub r6, r6, r7, ror r9 +# CHECK-NEXT: 1 1 0.50 subs r7, r8, #-2147483638 +# CHECK-NEXT: 1 1 0.50 subs r7, r8, #40, #2 +# CHECK-NEXT: 0 0 0.00 U svc #16 +# CHECK-NEXT: 0 0 0.00 U svc #0 +# CHECK-NEXT: 0 0 0.00 U svc #16777215 +# CHECK-NEXT: 1 2 1.00 sxtab r2, r3, r4 +# CHECK-NEXT: 1 2 1.00 sxtab r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 sxtablt r6, r2, r9, ror #8 +# CHECK-NEXT: 1 2 1.00 sxtab r5, r1, r4, ror #16 +# CHECK-NEXT: 1 2 1.00 sxtab r7, r8, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 sxtab16ge r0, r1, r4 +# CHECK-NEXT: 1 2 1.00 sxtab16 r6, r2, r7 +# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 sxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 sxtah r1, r3, r9 +# CHECK-NEXT: 1 2 1.00 sxtahhi r6, r1, r6 +# CHECK-NEXT: 1 2 1.00 sxtah r3, r8, r3, ror #8 +# CHECK-NEXT: 1 2 1.00 sxtahlo r2, r2, r4, ror #16 +# CHECK-NEXT: 1 2 1.00 sxtah r9, r3, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 sxtbge r2, r4 +# CHECK-NEXT: 1 2 1.00 sxtb r5, r6 +# CHECK-NEXT: 1 2 1.00 sxtb r6, r9, ror #8 +# CHECK-NEXT: 1 2 1.00 sxtblo r5, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 sxtb r8, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 sxtb16 r1, r4 +# CHECK-NEXT: 1 2 1.00 sxtb16 r6, r7 +# CHECK-NEXT: 1 2 1.00 sxtb16hs r3, r5, ror #8 +# CHECK-NEXT: 1 2 1.00 sxtb16 r3, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 sxtb16ge r2, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 sxthne r3, r9 +# CHECK-NEXT: 1 2 1.00 sxth r1, r6 +# CHECK-NEXT: 1 2 1.00 sxth r3, r8, ror #8 +# CHECK-NEXT: 1 2 1.00 sxthle r2, r2, ror #16 +# CHECK-NEXT: 1 2 1.00 sxth r9, r3, ror #24 +# CHECK-NEXT: 1 1 0.50 teq r5, #61440 +# CHECK-NEXT: 1 1 0.50 teq r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 teq r7, #40, #2 +# CHECK-NEXT: 1 1 0.50 teq r4, r5 +# CHECK-NEXT: 1 2 1.00 teq r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 teq r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 teq r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 teq r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 teq r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 teq r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 teq r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 teq r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 teq r6, r7, ror r9 +# CHECK-NEXT: 1 1 0.50 tst r5, #61440 +# CHECK-NEXT: 1 1 0.50 tst r7, #-2147483638 +# CHECK-NEXT: 1 1 0.50 tst r7, #40, #2 +# CHECK-NEXT: 1 1 0.50 tst r4, r5 +# CHECK-NEXT: 1 2 1.00 tst r4, r5, lsl #5 +# CHECK-NEXT: 1 2 1.00 tst r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 tst r4, r5, lsr #5 +# CHECK-NEXT: 1 2 1.00 tst r4, r5, asr #5 +# CHECK-NEXT: 1 2 1.00 tst r4, r5, ror #5 +# CHECK-NEXT: 1 2 1.00 tst r6, r7, lsl r9 +# CHECK-NEXT: 1 2 1.00 tst r6, r7, lsr r9 +# CHECK-NEXT: 1 2 1.00 tst r6, r7, asr r9 +# CHECK-NEXT: 1 2 1.00 tst r6, r7, ror r9 +# CHECK-NEXT: 2 2 1.00 * * U uadd16 r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U uadd16gt r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U uadd8 r1, r2, r3 +# CHECK-NEXT: 2 2 1.00 * * U uadd8le r1, r2, r3 +# CHECK-NEXT: 2 3 1.00 * * U uasx r9, r12, r0 +# CHECK-NEXT: 2 3 1.00 * * U uasxeq r9, r12, r0 +# CHECK-NEXT: 1 1 0.50 U ubfx r4, r5, #16, #1 +# CHECK-NEXT: 1 1 0.50 U ubfxgt r4, r5, #16, #16 +# CHECK-NEXT: 1 2 1.00 uhadd16 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhadd16gt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhadd8 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhadd8gt r4, r8, r2 +# CHECK-NEXT: 2 3 1.00 uhasx r4, r8, r2 +# CHECK-NEXT: 2 3 1.00 uhasxgt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhsub16 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhsub16gt r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhsub8 r4, r8, r2 +# CHECK-NEXT: 1 2 1.00 uhsub8gt r4, r8, r2 +# CHECK-NEXT: 2 4 2.00 umaal r3, r4, r5, r6 +# CHECK-NEXT: 2 4 2.00 umaallt r3, r4, r5, r6 +# CHECK-NEXT: 2 4 2.00 umlal r2, r4, r6, r8 +# CHECK-NEXT: 2 4 2.00 umlalgt r6, r1, r2, r6 +# CHECK-NEXT: 2 4 2.00 umlals r2, r9, r2, r3 +# CHECK-NEXT: 2 4 2.00 umlalseq r3, r5, r1, r2 +# CHECK-NEXT: 2 4 2.00 umull r2, r4, r6, r8 +# CHECK-NEXT: 2 4 2.00 umullgt r6, r1, r2, r6 +# CHECK-NEXT: 2 4 2.00 umulls r2, r9, r2, r3 +# CHECK-NEXT: 2 4 2.00 umullseq r3, r5, r1, r2 +# CHECK-NEXT: 1 2 1.00 uqadd16 r1, r2, r3 +# CHECK-NEXT: 1 2 1.00 uqadd16gt r4, r7, r9 +# CHECK-NEXT: 1 2 1.00 uqadd8 r3, r4, r8 +# CHECK-NEXT: 1 2 1.00 uqadd8le r8, r1, r2 +# CHECK-NEXT: 2 3 1.00 uqasx r2, r4, r1 +# CHECK-NEXT: 2 3 1.00 uqasxhi r5, r2, r9 +# CHECK-NEXT: 2 3 1.00 uqsax r1, r3, r7 +# CHECK-NEXT: 2 3 1.00 uqsax r3, r6, r2 +# CHECK-NEXT: 1 2 1.00 uqsub16 r1, r5, r3 +# CHECK-NEXT: 1 2 1.00 uqsub16gt r3, r2, r5 +# CHECK-NEXT: 1 2 1.00 uqsub8 r2, r1, r4 +# CHECK-NEXT: 1 2 1.00 uqsub8le r4, r6, r9 +# CHECK-NEXT: 1 3 1.00 usad8 r2, r1, r4 +# CHECK-NEXT: 1 3 1.00 usad8le r4, r6, r9 +# CHECK-NEXT: 1 3 1.00 usada8 r1, r5, r3, r7 +# CHECK-NEXT: 1 3 1.00 usada8gt r3, r2, r5, r1 +# CHECK-NEXT: 1 2 1.00 usat r8, #1, r10 +# CHECK-NEXT: 1 2 1.00 usat r8, #4, r10 +# CHECK-NEXT: 1 2 1.00 usat r8, #5, r10, lsl #31 +# CHECK-NEXT: 1 2 1.00 usat r8, #31, r10, asr #32 +# CHECK-NEXT: 1 2 1.00 usat r8, #16, r10, asr #1 +# CHECK-NEXT: 1 2 1.00 usat16 r2, #2, r7 +# CHECK-NEXT: 1 2 1.00 usat16 r3, #15, r5 +# CHECK-NEXT: 2 3 1.00 * * U usax r2, r3, r4 +# CHECK-NEXT: 2 3 1.00 * * U usaxne r2, r3, r4 +# CHECK-NEXT: 2 2 1.00 * * U usub16 r4, r2, r7 +# CHECK-NEXT: 2 2 1.00 * * U usub16hi r1, r1, r3 +# CHECK-NEXT: 2 2 1.00 * * U usub8 r1, r8, r5 +# CHECK-NEXT: 2 2 1.00 * * U usub8le r9, r2, r3 +# CHECK-NEXT: 1 2 1.00 uxtab r2, r3, r4 +# CHECK-NEXT: 1 2 1.00 uxtab r4, r5, r6 +# CHECK-NEXT: 1 2 1.00 uxtablt r6, r2, r9, ror #8 +# CHECK-NEXT: 1 2 1.00 uxtab r5, r1, r4, ror #16 +# CHECK-NEXT: 1 2 1.00 uxtab r7, r8, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 uxtab16ge r0, r1, r4 +# CHECK-NEXT: 1 2 1.00 uxtab16 r6, r2, r7 +# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 uxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 uxtah r1, r3, r9 +# CHECK-NEXT: 1 2 1.00 uxtahhi r6, r1, r6 +# CHECK-NEXT: 1 2 1.00 uxtah r3, r8, r3, ror #8 +# CHECK-NEXT: 1 2 1.00 uxtahlo r2, r2, r4, ror #16 +# CHECK-NEXT: 1 2 1.00 uxtah r9, r3, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 uxtbge r2, r4 +# CHECK-NEXT: 1 2 1.00 uxtb r5, r6 +# CHECK-NEXT: 1 2 1.00 uxtb r6, r9, ror #8 +# CHECK-NEXT: 1 2 1.00 uxtblo r5, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 uxtb r8, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 uxtb16 r1, r4 +# CHECK-NEXT: 1 2 1.00 uxtb16 r6, r7 +# CHECK-NEXT: 1 2 1.00 uxtb16hs r3, r5, ror #8 +# CHECK-NEXT: 1 2 1.00 uxtb16 r3, r1, ror #16 +# CHECK-NEXT: 1 2 1.00 uxtb16ge r2, r3, ror #24 +# CHECK-NEXT: 1 2 1.00 uxthne r3, r9 +# CHECK-NEXT: 1 2 1.00 uxth r1, r6 +# CHECK-NEXT: 1 2 1.00 uxth r3, r8, ror #8 +# CHECK-NEXT: 1 2 1.00 uxthle r2, r2, ror #16 +# CHECK-NEXT: 1 2 1.00 uxth r9, r3, ror #24 +# CHECK-NEXT: 0 0 0.00 * * U wfe +# CHECK-NEXT: 0 0 0.00 * * U wfehi +# CHECK-NEXT: 0 0 0.00 * * U wfi +# CHECK-NEXT: 0 0 0.00 * * U wfilt +# CHECK-NEXT: 0 0 0.00 * * U yield +# CHECK-NEXT: 0 0 0.00 * * U yieldne +# CHECK-NEXT: 0 0 0.00 * * U sevl + +# CHECK: Resources: +# CHECK-NEXT: [0] - A57UnitB +# CHECK-NEXT: [1.0] - A57UnitI +# CHECK-NEXT: [1.1] - A57UnitI +# CHECK-NEXT: [2] - A57UnitL +# CHECK-NEXT: [3] - A57UnitM +# CHECK-NEXT: [4] - A57UnitS +# CHECK-NEXT: [5] - A57UnitW +# CHECK-NEXT: [6] - A57UnitX + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] +# CHECK-NEXT: 8.00 148.50 148.50 161.00 527.00 12.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #240 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #3840 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #983040 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #15728640 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #251658240 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #-268435456 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r1, r2, #-268435441 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - adcs r1, r2, #3840 +# CHECK-NEXT: - 0.50 0.50 - - - - - adcs r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - adcseq r1, r2, #3840 +# CHECK-NEXT: - 0.50 0.50 - - - - - adceq r1, r2, #3840 +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, lsl #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, lsl #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, lsr #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, lsr #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, lsr #32 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, asr #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, asr #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, asr #32 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, ror #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, ror #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - adc r5, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, lsl #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, lsl #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, lsr #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, lsr #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, lsr #32 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, asr #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, asr #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, asr #32 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, ror #1 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, ror #31 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, rrx +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - adc r4, r4, r5, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - add r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - add r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - add r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - add r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - add r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - add r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - add r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - add r4, r4, r5, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - adds r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - adds r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - adr r2, #3 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r2, pc, #3 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r1, pc, #0 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r1, pc, #301989888 +# CHECK-NEXT: - 0.50 0.50 - - - - - adr r1, #301989888 +# CHECK-NEXT: - 0.50 0.50 - - - - - and r10, r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - and r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - and r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - and r10, r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r7, r8, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r7, r8, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r7, r8, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r7, r8, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r1, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - and r1, r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - and r10, r10, r1 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r6, r7, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r6, r7, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r6, r7, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - and r6, r6, r7, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - and r10, r10, r1, rrx +# CHECK-NEXT: - - - - 1.00 - - - bfc r5, #3, #17 +# CHECK-NEXT: - - - - 1.00 - - - bfclo r5, #3, #17 +# CHECK-NEXT: - - - - 1.00 - - - bfi r5, r2, #3, #17 +# CHECK-NEXT: - - - - 1.00 - - - bfine r5, r2, #3, #17 +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r10, r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r10, r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r7, r8, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r7, r8, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r7, r8, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r7, r8, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r1, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r1, r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - bic r10, r10, r1 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r6, r7, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r6, r7, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r6, r7, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r6, r6, r7, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - bic r10, r10, r1, rrx +# CHECK-NEXT: - - - - - - - - bkpt #10 +# CHECK-NEXT: - - - - - - - - bkpt #65535 +# CHECK-NEXT: 1.00 0.50 0.50 - - - - - blx r2 +# CHECK-NEXT: 1.00 0.50 0.50 - - - - - blxne r2 +# CHECK-NEXT: 1.00 0.50 0.50 - - - - - blx #32424576 +# CHECK-NEXT: 1.00 0.50 0.50 - - - - - blx #16212288 +# CHECK-NEXT: 1.00 - - - - - - - bx r2 +# CHECK-NEXT: 1.00 - - - - - - - bxne r2 +# CHECK-NEXT: 1.00 - - - - - - - bxj r2 +# CHECK-NEXT: 1.00 - - - - - - - bxjne r2 +# CHECK-NEXT: - - - - - - - - clrex +# CHECK-NEXT: - 0.50 0.50 - - - - - clz r1, r2 +# CHECK-NEXT: - 0.50 0.50 - - - - - clzeq r1, r2 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmn r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmn r7, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmn r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmn r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - cmn r1, r6, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - cmn r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmn sp, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmn r1, r6, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmn r1, r6, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - cmn r7, r8, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - cmn sp, r8, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - cmn r7, r8, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - cmn r7, r8, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - cmn r1, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - cmp r1, #15 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmp r7, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmp r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - cmp r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - cmp r1, r6, lsl #10 +# CHECK-NEXT: - - - - 1.00 - - - cmp r1, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmp sp, r6, lsr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmp r1, r6, asr #10 +# CHECK-NEXT: - - - - 1.00 - - - cmp r1, r6, ror #10 +# CHECK-NEXT: - - - - 1.00 - - - cmp r7, r8, lsl r2 +# CHECK-NEXT: - - - - 1.00 - - - cmp sp, r8, lsr r2 +# CHECK-NEXT: - - - - 1.00 - - - cmp r7, r8, asr r2 +# CHECK-NEXT: - - - - 1.00 - - - cmp r7, r8, ror r2 +# CHECK-NEXT: - - - - 1.00 - - - cmp r1, r6, rrx +# CHECK-NEXT: - - - - - - - - cpsie aif +# CHECK-NEXT: - - - - - - - - cps #15 +# CHECK-NEXT: - - - - - - - - cpsid if, #10 +# CHECK-NEXT: - - - - - - - - cpsid af, #17 +# CHECK-NEXT: - - - - - - - - cpsie f, #26 +# CHECK-NEXT: - - - - - - - - dbg #0 +# CHECK-NEXT: - - - - - - - - dbg #5 +# CHECK-NEXT: - - - - - - - - dbg #15 +# CHECK-NEXT: - - - - - - - - dmb #0x0 +# CHECK-NEXT: - - - - - - - - dmb oshld +# CHECK-NEXT: - - - - - - - - dmb oshst +# CHECK-NEXT: - - - - - - - - dmb osh +# CHECK-NEXT: - - - - - - - - dmb #0x4 +# CHECK-NEXT: - - - - - - - - dmb nshld +# CHECK-NEXT: - - - - - - - - dmb nshst +# CHECK-NEXT: - - - - - - - - dmb nsh +# CHECK-NEXT: - - - - - - - - dmb #0x8 +# CHECK-NEXT: - - - - - - - - dmb ishld +# CHECK-NEXT: - - - - - - - - dmb ishst +# CHECK-NEXT: - - - - - - - - dmb ish +# CHECK-NEXT: - - - - - - - - dmb #0xc +# CHECK-NEXT: - - - - - - - - dmb ld +# CHECK-NEXT: - - - - - - - - dmb st +# CHECK-NEXT: - - - - - - - - dmb sy +# CHECK-NEXT: - - - - - - - - ssbb +# CHECK-NEXT: - - - - - - - - dsb oshld +# CHECK-NEXT: - - - - - - - - dsb oshst +# CHECK-NEXT: - - - - - - - - dsb osh +# CHECK-NEXT: - - - - - - - - pssbb +# CHECK-NEXT: - - - - - - - - dsb nshld +# CHECK-NEXT: - - - - - - - - dsb nshst +# CHECK-NEXT: - - - - - - - - dsb nsh +# CHECK-NEXT: - - - - - - - - dsb #0x8 +# CHECK-NEXT: - - - - - - - - dsb ishld +# CHECK-NEXT: - - - - - - - - dsb ishst +# CHECK-NEXT: - - - - - - - - dsb ish +# CHECK-NEXT: - - - - - - - - dsb #0xc +# CHECK-NEXT: - - - - - - - - dsb ld +# CHECK-NEXT: - - - - - - - - dsb st +# CHECK-NEXT: - - - - - - - - dsb sy +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - eor r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - eor r4, r4, r5, rrx +# CHECK-NEXT: - - - - - - - - isb sy +# CHECK-NEXT: - - - - - - - - isb #0xa +# CHECK-NEXT: - - - 16.00 - - - - ldm r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - 16.00 - - - - ldmib r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - 16.00 - - - - ldmda r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - 16.00 - - - - ldmdb r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldm r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldmib r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldmda r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 8.00 8.00 16.00 - - - - ldmdb r2!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - - - - - - ldrexb r3, [r4] +# CHECK-NEXT: - - - - - - - - ldrexh r2, [r5] +# CHECK-NEXT: - - - - - - - - ldrex r1, [r7] +# CHECK-NEXT: - - - - - - - - ldrexd r6, r7, [r8] +# CHECK-NEXT: - - - - 1.00 - - - mla r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - mlas r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - mlane r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - mlasne r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - mls r2, r5, r6, r3 +# CHECK-NEXT: - - - - 1.00 - - - mlsne r2, r5, r6, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r3, #7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r4, #4080 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r5, #16711680 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov sp, #35 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r9, #240, #30 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov pc, #2147483658 +# CHECK-NEXT: - 0.50 0.50 - - - - - movw r6, #65535 +# CHECK-NEXT: - 0.50 0.50 - - - - - movw r9, #65535 +# CHECK-NEXT: - 0.50 0.50 - - - - - movw sp, #1193 +# CHECK-NEXT: - 0.50 0.50 - - - - - movs r3, #7 +# CHECK-NEXT: - 0.50 0.50 - - - - - movs r11, #99 +# CHECK-NEXT: - 0.50 0.50 - - - - - movs r11, #240, #30 +# CHECK-NEXT: - 0.50 0.50 - - - - - moveq r4, #4080 +# CHECK-NEXT: - 0.50 0.50 - - - - - movseq r5, #16711680 +# CHECK-NEXT: - 0.50 0.50 - - - - - mov r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - movs r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - moveq r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - movseq r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - movt r3, #7 +# CHECK-NEXT: - - - - 1.00 - - - movt r6, #65535 +# CHECK-NEXT: - - - - 1.00 - - - movt sp, #3397 +# CHECK-NEXT: - - - - 1.00 - - - movteq r4, #4080 +# CHECK-NEXT: - - - - - - - - mrc p14, #0, r1, c1, c2, #4 +# CHECK-NEXT: - - - - - - - - mrc p15, #7, apsr_nzcv, c15, c6, #6 +# CHECK-NEXT: - - - - - - - - mrs r8, apsr +# CHECK-NEXT: - - - - - - - - mrs r8, spsr +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, #5 +# CHECK-NEXT: - - - - - - - - msr APSR_g, #5 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvq, #5 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvq, #5 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvqg, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_c, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_x, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_fsx, #5 +# CHECK-NEXT: - - - - - - - - msr SPSR_fc, #5 +# CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, #5 +# CHECK-NEXT: - - - - - - - - msr CPSR_fsxc, #5 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvq, #2147483658 +# CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, #40, #2 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, r0 +# CHECK-NEXT: - - - - - - - - msr APSR_g, r0 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvq, r0 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvq, r0 +# CHECK-NEXT: - - - - - - - - msr APSR_nzcvqg, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_c, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_x, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_fc, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_fsx, r0 +# CHECK-NEXT: - - - - - - - - msr SPSR_fc, r0 +# CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, r0 +# CHECK-NEXT: - - - - - - - - msr CPSR_fsxc, r0 +# CHECK-NEXT: - - - - 1.00 - - - mul r5, r6, r7 +# CHECK-NEXT: - - - - 1.00 - - - muls r5, r6, r7 +# CHECK-NEXT: - - - - 1.00 - - - mulgt r5, r6, r7 +# CHECK-NEXT: - - - - 1.00 - - - mulsle r5, r6, r7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r3, #7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r4, #4080 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, #16711680 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r7, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r3, #7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r11, #240, #30 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r11, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvneq r4, #4080 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvnseq r5, #16711680 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, lsl #19 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, lsr #9 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, asr #4 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, ror #6 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - mvneq r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvnseq r2, r3, lsl #10 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvn r5, r6, lsl r7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvns r5, r6, lsr r7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvngt r5, r6, asr r7 +# CHECK-NEXT: - 0.50 0.50 - - - - - mvnslt r5, r6, ror r7 +# CHECK-NEXT: - - - - - - - - nop +# CHECK-NEXT: - - - - - - - - nopgt +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - orr r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - orr r4, r4, r5, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - orrseq r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - orrne r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - orrseq r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - orrlo r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - orrshi r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - orrhs r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - orrseq r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - orrne r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - orrslt r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - orrsgt r4, r4, r5, rrx +# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3, lsl #31 +# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3, lsl #15 +# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - pkhtb r2, r2, r3, asr #31 +# CHECK-NEXT: - - - - 1.00 - - - pkhtb r2, r2, r3, asr #15 +# CHECK-NEXT: - 0.50 0.50 1.00 - - - - pop {r7} +# CHECK-NEXT: - 8.00 8.00 16.00 - - - - pop {r7, r8, r9, r10} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - push {r7} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - push {r7, r8, r9, r10} +# CHECK-NEXT: - - - - 1.00 - - - qadd r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qaddne r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qadd16 r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qadd16gt r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qadd8 r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qadd8le r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdadd r6, r7, r8 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdaddhi r6, r7, r8 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdsub r6, r7, r8 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qdsubhi r6, r7, r8 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qsax r9, r12, r0 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - qsaxeq r9, r12, r0 +# CHECK-NEXT: - - - - 1.00 - - - qsub r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qsubne r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qsub16 r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qsub16gt r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qsub8 r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - qsub8le r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - rbit r1, r2 +# CHECK-NEXT: - 0.50 0.50 - - - - - rbitne r1, r2 +# CHECK-NEXT: - 0.50 0.50 - - - - - rev r1, r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - revne r1, r5 +# CHECK-NEXT: - 0.50 0.50 - - - - - rev16 r8, r3 +# CHECK-NEXT: - 0.50 0.50 - - - - - rev16ne r12, r4 +# CHECK-NEXT: - 0.50 0.50 - - - - - revsh r4, r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - revshne r9, r1 +# CHECK-NEXT: - - - - - - - - rfeda r2 +# CHECK-NEXT: - - - - - - - - rfedb r3 +# CHECK-NEXT: - - - - - - - - rfeia r5 +# CHECK-NEXT: - - - - - - - - rfeib r6 +# CHECK-NEXT: - - - - - - - - rfeda r4! +# CHECK-NEXT: - - - - - - - - rfedb r7! +# CHECK-NEXT: - - - - - - - - rfeia r9! +# CHECK-NEXT: - - - - - - - - rfeib r8! +# CHECK-NEXT: - - - - - - - - rfeda r2 +# CHECK-NEXT: - - - - - - - - rfedb r3 +# CHECK-NEXT: - - - - - - - - rfeia r5 +# CHECK-NEXT: - - - - - - - - rfeib r6 +# CHECK-NEXT: - - - - - - - - rfeda r4! +# CHECK-NEXT: - - - - - - - - rfedb r7! +# CHECK-NEXT: - - - - - - - - rfeia r9! +# CHECK-NEXT: - - - - - - - - rfeib r8! +# CHECK-NEXT: - - - - - - - - rfeia r1 +# CHECK-NEXT: - - - - - - - - rfeia r1! +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - rsblo r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsble r6, r7, r8, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsbne r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - rsbgt r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, ror r9 +# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, rrx +# CHECK-NEXT: - 0.50 0.50 - - - - - rsbs r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsbs r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - rsclo r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - rscle r6, r7, r8, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rscne r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - rscgt r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - rrx r0, r1 +# CHECK-NEXT: - 0.50 0.50 - - - - - rrx sp, pc +# CHECK-NEXT: - 0.50 0.50 - - - - - rrx pc, lr +# CHECK-NEXT: - 0.50 0.50 - - - - - rrx lr, sp +# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs r0, r1 +# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs sp, pc +# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs pc, lr +# CHECK-NEXT: - 0.50 0.50 - - - - - rrxs lr, sp +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd16 r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd16gt r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd8 r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sadd8le r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sasx r9, r12, r0 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - sasxeq r9, r12, r0 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r7, r8, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbc r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - sbc r6, r6, r7, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbfx r4, r5, #16, #1 +# CHECK-NEXT: - 0.50 0.50 - - - - - sbfxgt r4, r5, #16, #16 +# CHECK-NEXT: - 0.50 0.50 - - - - - sel r9, r2, r1 +# CHECK-NEXT: - 0.50 0.50 - - - - - selne r9, r2, r1 +# CHECK-NEXT: - - - - - - - - setend be +# CHECK-NEXT: - - - - - - - - setend le +# CHECK-NEXT: - - - - - - - - sev +# CHECK-NEXT: - - - - - - - - seveq +# CHECK-NEXT: - - - - 1.00 - - - shadd16 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shadd16gt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shadd8 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shadd8gt r4, r8, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - shasx r4, r8, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - shasxgt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shsub16 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shsub16gt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shsub8 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - shsub8gt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - smlabb r3, r1, r9, r0 +# CHECK-NEXT: - - - - 1.00 - - - smlabt r5, r6, r4, r1 +# CHECK-NEXT: - - - - 1.00 - - - smlatb r4, r2, r3, r2 +# CHECK-NEXT: - - - - 1.00 - - - smlatt r8, r3, r8, r4 +# CHECK-NEXT: - - - - 1.00 - - - smlabbge r3, r1, r9, r0 +# CHECK-NEXT: - - - - 1.00 - - - smlabtle r5, r6, r4, r1 +# CHECK-NEXT: - - - - 1.00 - - - smlatbne r4, r2, r3, r2 +# CHECK-NEXT: - - - - 1.00 - - - smlatteq r8, r3, r8, r4 +# CHECK-NEXT: - - - - 1.00 - - - smlad r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smladx r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smladeq r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smladxhi r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlal r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlals r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlaleq r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlalshi r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlalbb r3, r1, r9, r0 +# CHECK-NEXT: - - - - 2.00 - - - smlalbt r5, r6, r4, r1 +# CHECK-NEXT: - - - - 2.00 - - - smlaltb r4, r2, r3, r2 +# CHECK-NEXT: - - - - 2.00 - - - smlaltt r8, r3, r8, r4 +# CHECK-NEXT: - - - - 2.00 - - - smlalbbge r3, r1, r9, r0 +# CHECK-NEXT: - - - - 2.00 - - - smlalbtle r5, r6, r4, r1 +# CHECK-NEXT: - - - - 2.00 - - - smlaltbne r4, r2, r3, r2 +# CHECK-NEXT: - - - - 2.00 - - - smlaltteq r8, r3, r8, r4 +# CHECK-NEXT: - - - - 2.00 - - - smlald r2, r3, r5, r8 +# CHECK-NEXT: - - - 2.00 - - - - smlaldx r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlaldeq r2, r3, r5, r8 +# CHECK-NEXT: - - - 2.00 - - - - smlaldxhi r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlawb r2, r3, r10, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlawt r8, r3, r5, r9 +# CHECK-NEXT: - - - - 1.00 - - - smlawbeq r2, r7, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlawthi r1, r3, r0, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlsd r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlsdx r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlsdeq r2, r3, r5, r8 +# CHECK-NEXT: - - - - 1.00 - - - smlsdxhi r2, r3, r5, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlsld r2, r9, r5, r1 +# CHECK-NEXT: - - - 2.00 - - - - smlsldx r4, r11, r2, r8 +# CHECK-NEXT: - - - - 2.00 - - - smlsldeq r8, r2, r5, r6 +# CHECK-NEXT: - - - 2.00 - - - - smlsldxhi r1, r0, r3, r8 +# CHECK-NEXT: - - - - 1.00 - - - smmla r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmlar r4, r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smmlalo r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmlarhs r4, r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smmls r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmlsr r4, r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smmlslo r1, r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmlsrhs r4, r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smmul r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmulr r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smmullo r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smmulrhs r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smuad r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smuadx r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smuadlt r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smuadxge r3, r2, r1 +# CHECK-NEXT: - - - - 1.00 - - - smulbb r3, r9, r0 +# CHECK-NEXT: - - - - 1.00 - - - smulbt r5, r4, r1 +# CHECK-NEXT: - - - - 1.00 - - - smultb r4, r2, r2 +# CHECK-NEXT: - - - - 1.00 - - - smultt r8, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - smulbbge r1, r9, r0 +# CHECK-NEXT: - - - - 1.00 - - - smulbtle r5, r6, r4 +# CHECK-NEXT: - - - - 1.00 - - - smultbne r2, r3, r2 +# CHECK-NEXT: - - - - 1.00 - - - smultteq r8, r3, r4 +# CHECK-NEXT: - - - 2.00 - - - - smull r3, r9, r0, r1 +# CHECK-NEXT: - - - 2.00 - - - - smulls r3, r9, r0, r2 +# CHECK-NEXT: - - - 2.00 - - - - smulleq r8, r3, r4, r5 +# CHECK-NEXT: - - - 2.00 - - - - smullseq r8, r3, r4, r3 +# CHECK-NEXT: - - - - 1.00 - - - smulwb r3, r9, r0 +# CHECK-NEXT: - - - - 1.00 - - - smulwt r3, r9, r2 +# CHECK-NEXT: - - - - 1.00 - - - smusd r3, r0, r1 +# CHECK-NEXT: - - - - 1.00 - - - smusdx r3, r9, r2 +# CHECK-NEXT: - - - - 1.00 - - - smusdeq r8, r3, r2 +# CHECK-NEXT: - - - - 1.00 - - - smusdxne r7, r4, r3 +# CHECK-NEXT: - - - - - - - - srsda sp, #5 +# CHECK-NEXT: - - - - - - - - srsdb sp, #1 +# CHECK-NEXT: - - - - - - - - srsia sp, #0 +# CHECK-NEXT: - - - - - - - - srsib sp, #15 +# CHECK-NEXT: - - - - - - - - srsda sp!, #31 +# CHECK-NEXT: - - - - - - - - srsdb sp!, #19 +# CHECK-NEXT: - - - - - - - - srsia sp!, #2 +# CHECK-NEXT: - - - - - - - - srsib sp!, #14 +# CHECK-NEXT: - - - - - - - - srsda sp, #11 +# CHECK-NEXT: - - - - - - - - srsdb sp, #10 +# CHECK-NEXT: - - - - - - - - srsia sp, #9 +# CHECK-NEXT: - - - - - - - - srsib sp, #5 +# CHECK-NEXT: - - - - - - - - srsda sp!, #5 +# CHECK-NEXT: - - - - - - - - srsdb sp!, #5 +# CHECK-NEXT: - - - - - - - - srsia sp!, #5 +# CHECK-NEXT: - - - - - - - - srsib sp!, #5 +# CHECK-NEXT: - - - - - - - - srsia sp, #5 +# CHECK-NEXT: - - - - - - - - srsia sp!, #5 +# CHECK-NEXT: - - - - 1.00 - - - ssat r8, #1, r10 +# CHECK-NEXT: - - - - 1.00 - - - ssat r8, #1, r10, lsl #31 +# CHECK-NEXT: - - - - 1.00 - - - ssat r8, #1, r10, asr #32 +# CHECK-NEXT: - - - - 1.00 - - - ssat r8, #1, r10, asr #1 +# CHECK-NEXT: - - - - 1.00 - - - ssat16 r2, #1, r7 +# CHECK-NEXT: - - - - 1.00 - - - ssat16 r3, #16, r5 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssax r2, r3, r4 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssaxlt r2, r3, r4 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssub16 r1, r0, r6 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssub16ne r5, r3, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssub8 r9, r2, r4 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - ssub8eq r5, r1, r2 +# CHECK-NEXT: - - - - - 1.00 - - stm r2, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - - - 1.00 - - stm r3, {r1, r3, r4, r5, r6, lr} +# CHECK-NEXT: - - - - - 1.00 - - stmib r4, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - - - 1.00 - - stmda r5, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - - - - - 1.00 - - stmdb r6, {r1, r3, r4, r5, r6, r8} +# CHECK-NEXT: - - - - - 1.00 - - stmdb sp, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - stm r8!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - stmib r9!, {r1, r3, r4, r5, r6, sp} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - stmda sp!, {r1, r3, r4, r5, r6} +# CHECK-NEXT: - 0.50 0.50 - - 1.00 - - stmdb r0!, {r1, r5, r7, sp} +# CHECK-NEXT: - - - - - - - - strexb r1, r3, [r4] +# CHECK-NEXT: - - - - - - - - strexh r4, r2, [r5] +# CHECK-NEXT: - - - - - - - - strex r2, r1, [r7] +# CHECK-NEXT: - - - - - - - - strexd r6, r2, r3, [r8] +# CHECK-NEXT: - - - - - - - - strexd sp, r0, r1, [r0] +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r4, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r7, r8, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r5, r6, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r5, r6, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r5, r6, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r5, r6, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r7, r8, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r7, r8, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r7, r8, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r7, r8, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r5, r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - sub r4, r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r4, r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - sub r6, r6, r7, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - subs r7, r8, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - subs r7, r8, #40, #2 +# CHECK-NEXT: - - - - - - - - svc #16 +# CHECK-NEXT: - - - - - - - - svc #0 +# CHECK-NEXT: - - - - - - - - svc #16777215 +# CHECK-NEXT: - - - - 1.00 - - - sxtab r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - sxtab r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - sxtablt r6, r2, r9, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxtab r5, r1, r4, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxtab r7, r8, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - sxtab16ge r0, r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r6, r2, r7 +# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - sxtah r1, r3, r9 +# CHECK-NEXT: - - - - 1.00 - - - sxtahhi r6, r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - sxtah r3, r8, r3, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxtahlo r2, r2, r4, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxtah r9, r3, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - sxtbge r2, r4 +# CHECK-NEXT: - - - - 1.00 - - - sxtb r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - sxtb r6, r9, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxtblo r5, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxtb r8, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r6, r7 +# CHECK-NEXT: - - - - 1.00 - - - sxtb16hs r3, r5, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxtb16 r3, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxtb16ge r2, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - sxthne r3, r9 +# CHECK-NEXT: - - - - 1.00 - - - sxth r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - sxth r3, r8, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - sxthle r2, r2, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - sxth r9, r3, ror #24 +# CHECK-NEXT: - 0.50 0.50 - - - - - teq r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - teq r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - teq r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - teq r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - teq r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - teq r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - teq r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - teq r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - teq r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - teq r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - teq r6, r7, ror r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - tst r5, #61440 +# CHECK-NEXT: - 0.50 0.50 - - - - - tst r7, #-2147483638 +# CHECK-NEXT: - 0.50 0.50 - - - - - tst r7, #40, #2 +# CHECK-NEXT: - 0.50 0.50 - - - - - tst r4, r5 +# CHECK-NEXT: - - - - 1.00 - - - tst r4, r5, lsl #5 +# CHECK-NEXT: - - - - 1.00 - - - tst r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - tst r4, r5, lsr #5 +# CHECK-NEXT: - - - - 1.00 - - - tst r4, r5, asr #5 +# CHECK-NEXT: - - - - 1.00 - - - tst r4, r5, ror #5 +# CHECK-NEXT: - - - - 1.00 - - - tst r6, r7, lsl r9 +# CHECK-NEXT: - - - - 1.00 - - - tst r6, r7, lsr r9 +# CHECK-NEXT: - - - - 1.00 - - - tst r6, r7, asr r9 +# CHECK-NEXT: - - - - 1.00 - - - tst r6, r7, ror r9 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd16 r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd16gt r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd8 r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uadd8le r1, r2, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uasx r9, r12, r0 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uasxeq r9, r12, r0 +# CHECK-NEXT: - 0.50 0.50 - - - - - ubfx r4, r5, #16, #1 +# CHECK-NEXT: - 0.50 0.50 - - - - - ubfxgt r4, r5, #16, #16 +# CHECK-NEXT: - - - - 1.00 - - - uhadd16 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhadd16gt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhadd8 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhadd8gt r4, r8, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uhasx r4, r8, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uhasxgt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhsub16 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhsub16gt r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhsub8 r4, r8, r2 +# CHECK-NEXT: - - - - 1.00 - - - uhsub8gt r4, r8, r2 +# CHECK-NEXT: - - - - 2.00 - - - umaal r3, r4, r5, r6 +# CHECK-NEXT: - - - - 2.00 - - - umaallt r3, r4, r5, r6 +# CHECK-NEXT: - - - - 2.00 - - - umlal r2, r4, r6, r8 +# CHECK-NEXT: - - - - 2.00 - - - umlalgt r6, r1, r2, r6 +# CHECK-NEXT: - - - - 2.00 - - - umlals r2, r9, r2, r3 +# CHECK-NEXT: - - - - 2.00 - - - umlalseq r3, r5, r1, r2 +# CHECK-NEXT: - - - - 2.00 - - - umull r2, r4, r6, r8 +# CHECK-NEXT: - - - - 2.00 - - - umullgt r6, r1, r2, r6 +# CHECK-NEXT: - - - - 2.00 - - - umulls r2, r9, r2, r3 +# CHECK-NEXT: - - - - 2.00 - - - umullseq r3, r5, r1, r2 +# CHECK-NEXT: - - - - 1.00 - - - uqadd16 r1, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - uqadd16gt r4, r7, r9 +# CHECK-NEXT: - - - - 1.00 - - - uqadd8 r3, r4, r8 +# CHECK-NEXT: - - - - 1.00 - - - uqadd8le r8, r1, r2 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uqasx r2, r4, r1 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uqasxhi r5, r2, r9 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uqsax r1, r3, r7 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - uqsax r3, r6, r2 +# CHECK-NEXT: - - - - 1.00 - - - uqsub16 r1, r5, r3 +# CHECK-NEXT: - - - - 1.00 - - - uqsub16gt r3, r2, r5 +# CHECK-NEXT: - - - - 1.00 - - - uqsub8 r2, r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - uqsub8le r4, r6, r9 +# CHECK-NEXT: - - - - 1.00 - - - usad8 r2, r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - usad8le r4, r6, r9 +# CHECK-NEXT: - - - - 1.00 - - - usada8 r1, r5, r3, r7 +# CHECK-NEXT: - - - - 1.00 - - - usada8gt r3, r2, r5, r1 +# CHECK-NEXT: - - - - 1.00 - - - usat r8, #1, r10 +# CHECK-NEXT: - - - - 1.00 - - - usat r8, #4, r10 +# CHECK-NEXT: - - - - 1.00 - - - usat r8, #5, r10, lsl #31 +# CHECK-NEXT: - - - - 1.00 - - - usat r8, #31, r10, asr #32 +# CHECK-NEXT: - - - - 1.00 - - - usat r8, #16, r10, asr #1 +# CHECK-NEXT: - - - - 1.00 - - - usat16 r2, #2, r7 +# CHECK-NEXT: - - - - 1.00 - - - usat16 r3, #15, r5 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usax r2, r3, r4 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usaxne r2, r3, r4 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub16 r4, r2, r7 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub16hi r1, r1, r3 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8 r1, r8, r5 +# CHECK-NEXT: - 0.50 0.50 - 1.00 - - - usub8le r9, r2, r3 +# CHECK-NEXT: - - - - 1.00 - - - uxtab r2, r3, r4 +# CHECK-NEXT: - - - - 1.00 - - - uxtab r4, r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - uxtablt r6, r2, r9, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxtab r5, r1, r4, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxtab r7, r8, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - uxtab16ge r0, r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r6, r2, r7 +# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - uxtah r1, r3, r9 +# CHECK-NEXT: - - - - 1.00 - - - uxtahhi r6, r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - uxtah r3, r8, r3, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxtahlo r2, r2, r4, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxtah r9, r3, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - uxtbge r2, r4 +# CHECK-NEXT: - - - - 1.00 - - - uxtb r5, r6 +# CHECK-NEXT: - - - - 1.00 - - - uxtb r6, r9, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxtblo r5, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxtb r8, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r1, r4 +# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r6, r7 +# CHECK-NEXT: - - - - 1.00 - - - uxtb16hs r3, r5, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxtb16 r3, r1, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxtb16ge r2, r3, ror #24 +# CHECK-NEXT: - - - - 1.00 - - - uxthne r3, r9 +# CHECK-NEXT: - - - - 1.00 - - - uxth r1, r6 +# CHECK-NEXT: - - - - 1.00 - - - uxth r3, r8, ror #8 +# CHECK-NEXT: - - - - 1.00 - - - uxthle r2, r2, ror #16 +# CHECK-NEXT: - - - - 1.00 - - - uxth r9, r3, ror #24 +# CHECK-NEXT: - - - - - - - - wfe +# CHECK-NEXT: - - - - - - - - wfehi +# CHECK-NEXT: - - - - - - - - wfi +# CHECK-NEXT: - - - - - - - - wfilt +# CHECK-NEXT: - - - - - - - - yield +# CHECK-NEXT: - - - - - - - - yieldne +# CHECK-NEXT: - - - - - - - - sevl Index: llvm/utils/TableGen/CodeGenSchedule.h =================================================================== --- llvm/utils/TableGen/CodeGenSchedule.h +++ llvm/utils/TableGen/CodeGenSchedule.h @@ -140,6 +140,8 @@ // Instructions should be ignored by this class because they have been split // off to join another inferred class. RecVec InstRWs; + // InstRWs processor indices. Filled in inferFromInstRWs + DenseSet InstRWProcIndices; CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef) : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {} Index: llvm/utils/TableGen/CodeGenSchedule.cpp =================================================================== --- llvm/utils/TableGen/CodeGenSchedule.cpp +++ llvm/utils/TableGen/CodeGenSchedule.cpp @@ -1281,6 +1281,7 @@ findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads); unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index; inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses. + SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx); } } @@ -1639,29 +1640,53 @@ } } +static void addSequences(CodeGenSchedModels &SchedModels, + const SmallVectorImpl> &Seqs, + IdxVec &Result, bool IsRead) { + for (const auto &S : Seqs) + if (!S.empty()) + Result.push_back(SchedModels.findOrInsertRW(S, IsRead)); +} + +static void dumpTransition(const CodeGenSchedModels &SchedModels, + const CodeGenSchedClass &FromSC, + const CodeGenSchedTransition &SCTrans) { + LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "(" + << FromSC.Index << ") to " + << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "(" + << SCTrans.ToClassIdx << ")" + << " on processor indices: ("; + dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n"); +} // Create a new SchedClass for each variant found by inferFromRW. Pass static void inferFromTransitions(ArrayRef LastTransitions, unsigned FromClassIdx, CodeGenSchedModels &SchedModels) { // For each PredTransition, create a new CodeGenSchedTransition, which usually // requires creating a new SchedClass. + const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx); for (ArrayRef::iterator I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) { - IdxVec OperWritesVariant; - transform(I->WriteSequences, std::back_inserter(OperWritesVariant), - [&SchedModels](ArrayRef WS) { - return SchedModels.findOrInsertRW(WS, /*IsRead=*/false); - }); - IdxVec OperReadsVariant; - transform(I->ReadSequences, std::back_inserter(OperReadsVariant), - [&SchedModels](ArrayRef RS) { - return SchedModels.findOrInsertRW(RS, /*IsRead=*/true); - }); + IdxVec OperWritesVariant, OperReadsVariant; + addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false); + addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true); CodeGenSchedTransition SCTrans; - SCTrans.ToClassIdx = - SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, - OperReadsVariant, I->ProcIndices); SCTrans.ProcIndices.assign(I->ProcIndices.begin(), I->ProcIndices.end()); + + // Remove all processor indices from this sched transition for which + // we also have InstRWs. + SCTrans.ProcIndices.erase( + llvm::remove_if(SCTrans.ProcIndices, + [&FromSC](unsigned PIdx) { + return FromSC.InstRWProcIndices.count(PIdx); + }), + SCTrans.ProcIndices.end()); + if (SCTrans.ProcIndices.empty()) + continue; + SCTrans.ToClassIdx = + SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, + OperReadsVariant, I->ProcIndices); + dumpTransition(SchedModels, FromSC, SCTrans); // The final PredTerm is unique set of predicates guarding the transition. RecVec Preds; transform(I->PredTerm, std::back_inserter(Preds), @@ -1684,7 +1709,6 @@ ArrayRef ProcIndices) { LLVM_DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices); dbgs() << ") "); - // Create a seed transition with an empty PredTerm and the expanded sequences // of SchedWrites for the current SchedClass. std::vector LastTransitions;