diff --git a/llvm/test/TableGen/sched-aliases.td b/llvm/test/TableGen/sched-aliases.td new file mode 100644 --- /dev/null +++ b/llvm/test/TableGen/sched-aliases.td @@ -0,0 +1,48 @@ +// REQUIRES: asserts +// REQUIRES: aarch64-registered-target +// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/AArch64 -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s + +// Check that we've defined scheduling classes for FMOVv2f32_ns and FMOVv2f64 for Model0 +// CHECK: InstRW: New SC [[SC:[0-9]+]]:FMOVv2f32_ns on Model0 +// CHECK: InstRW: New SC [[SC2:[0-9]+]]:FMOVv2f64_ns on Model0 + +// Generic transition for WriteV should be defined for Model0 as well as for +// all instructions without explicitly defined scheduling classes. +// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices +// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices + +// Transition from FMOVv2f64_ns should still be added for Model0, +// even though we've defined custom scheduling class. +// CHECK: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices +// CHECK-NEXT: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices + +// Transition from FMOVv2f32_ns should not be added for Model0, +// because custom sched class for it is defined and it's not variant. +// CHECK-NOT: Adding transition from FMOVv2f32_ns([[SC]]) + +include "AArch64.td" + +def Model0 : SchedMachineModel { + let CompleteModel = 0; +} + +def Model0UnitV : ProcResource<1> { let BufferSize = 0; } + +let SchedModel = Model0 in { + +def Model0WriteV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; } +def Model0WriteV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; } +def Model0WriteV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; } + +def Model0QFormPred : MCSchedPredicate; +def Model0WriteV : SchedWriteVariant<[ + SchedVar, + SchedVar]>; + +def : SchedAlias; + +def : InstRW<[Model0WriteV_1cyc], (instrs FMOVv2f32_ns)>; +def : InstRW<[WriteV], (instrs FMOVv2f64_ns)>; +} + +def : ProcessorModel<"foo-0-model", Model0, []>; diff --git a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s --- a/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s @@ -1561,31 +1561,31 @@ # CHECK-NEXT: 1 2 1.00 sxtablt r6, r2, r9, ror #8 # CHECK-NEXT: 1 2 1.00 sxtab r5, r1, r4, ror #16 # CHECK-NEXT: 1 2 1.00 sxtab r7, r8, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 sxtab16ge r0, r1, r4 -# CHECK-NEXT: 1 2 1.00 sxtab16 r6, r2, r7 -# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r5, r8, ror #8 -# CHECK-NEXT: 1 2 1.00 sxtab16 r3, r2, r1, ror #16 -# CHECK-NEXT: 1 2 1.00 sxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: 1 4 1.00 sxtab16ge r0, r1, r4 +# CHECK-NEXT: 1 4 1.00 sxtab16 r6, r2, r7 +# CHECK-NEXT: 1 4 1.00 sxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: 1 4 1.00 sxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: 1 4 1.00 sxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: 1 2 1.00 sxtah r1, r3, r9 # CHECK-NEXT: 1 2 1.00 sxtahhi r6, r1, r6 # CHECK-NEXT: 1 2 1.00 sxtah r3, r8, r3, ror #8 # CHECK-NEXT: 1 2 1.00 sxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: 1 2 1.00 sxtah r9, r3, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 sxtbge r2, r4 -# CHECK-NEXT: 1 2 1.00 sxtb r5, r6 -# CHECK-NEXT: 1 2 1.00 sxtb r6, r9, ror #8 -# CHECK-NEXT: 1 2 1.00 sxtblo r5, r1, ror #16 -# CHECK-NEXT: 1 2 1.00 sxtb r8, r3, ror #24 +# CHECK-NEXT: 1 1 0.50 sxtbge r2, r4 +# CHECK-NEXT: 1 1 0.50 sxtb r5, r6 +# CHECK-NEXT: 1 1 0.50 sxtb r6, r9, ror #8 +# CHECK-NEXT: 1 1 0.50 sxtblo r5, r1, ror #16 +# CHECK-NEXT: 1 1 0.50 sxtb r8, r3, ror #24 # CHECK-NEXT: 1 2 1.00 sxtb16 r1, r4 # CHECK-NEXT: 1 2 1.00 sxtb16 r6, r7 # CHECK-NEXT: 1 2 1.00 sxtb16hs r3, r5, ror #8 # CHECK-NEXT: 1 2 1.00 sxtb16 r3, r1, ror #16 # CHECK-NEXT: 1 2 1.00 sxtb16ge r2, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 sxthne r3, r9 -# CHECK-NEXT: 1 2 1.00 sxth r1, r6 -# CHECK-NEXT: 1 2 1.00 sxth r3, r8, ror #8 -# CHECK-NEXT: 1 2 1.00 sxthle r2, r2, ror #16 -# CHECK-NEXT: 1 2 1.00 sxth r9, r3, ror #24 +# CHECK-NEXT: 1 1 0.50 sxthne r3, r9 +# CHECK-NEXT: 1 1 0.50 sxth r1, r6 +# CHECK-NEXT: 1 1 0.50 sxth r3, r8, ror #8 +# CHECK-NEXT: 1 1 0.50 sxthle r2, r2, ror #16 +# CHECK-NEXT: 1 1 0.50 sxth r9, r3, ror #24 # CHECK-NEXT: 1 1 0.50 teq r5, #61440 # CHECK-NEXT: 1 1 0.50 teq r7, #-2147483638 # CHECK-NEXT: 1 1 0.50 teq r7, #40, #2 @@ -1674,31 +1674,31 @@ # CHECK-NEXT: 1 2 1.00 uxtablt r6, r2, r9, ror #8 # CHECK-NEXT: 1 2 1.00 uxtab r5, r1, r4, ror #16 # CHECK-NEXT: 1 2 1.00 uxtab r7, r8, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 uxtab16ge r0, r1, r4 -# CHECK-NEXT: 1 2 1.00 uxtab16 r6, r2, r7 -# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r5, r8, ror #8 -# CHECK-NEXT: 1 2 1.00 uxtab16 r3, r2, r1, ror #16 -# CHECK-NEXT: 1 2 1.00 uxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: 1 4 1.00 uxtab16ge r0, r1, r4 +# CHECK-NEXT: 1 4 1.00 uxtab16 r6, r2, r7 +# CHECK-NEXT: 1 4 1.00 uxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: 1 4 1.00 uxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: 1 4 1.00 uxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: 1 2 1.00 uxtah r1, r3, r9 # CHECK-NEXT: 1 2 1.00 uxtahhi r6, r1, r6 # CHECK-NEXT: 1 2 1.00 uxtah r3, r8, r3, ror #8 # CHECK-NEXT: 1 2 1.00 uxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: 1 2 1.00 uxtah r9, r3, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 uxtbge r2, r4 -# CHECK-NEXT: 1 2 1.00 uxtb r5, r6 -# CHECK-NEXT: 1 2 1.00 uxtb r6, r9, ror #8 -# CHECK-NEXT: 1 2 1.00 uxtblo r5, r1, ror #16 -# CHECK-NEXT: 1 2 1.00 uxtb r8, r3, ror #24 +# CHECK-NEXT: 1 1 0.50 uxtbge r2, r4 +# CHECK-NEXT: 1 1 0.50 uxtb r5, r6 +# CHECK-NEXT: 1 1 0.50 uxtb r6, r9, ror #8 +# CHECK-NEXT: 1 1 0.50 uxtblo r5, r1, ror #16 +# CHECK-NEXT: 1 1 0.50 uxtb r8, r3, ror #24 # CHECK-NEXT: 1 2 1.00 uxtb16 r1, r4 # CHECK-NEXT: 1 2 1.00 uxtb16 r6, r7 # CHECK-NEXT: 1 2 1.00 uxtb16hs r3, r5, ror #8 # CHECK-NEXT: 1 2 1.00 uxtb16 r3, r1, ror #16 # CHECK-NEXT: 1 2 1.00 uxtb16ge r2, r3, ror #24 -# CHECK-NEXT: 1 2 1.00 uxthne r3, r9 -# CHECK-NEXT: 1 2 1.00 uxth r1, r6 -# CHECK-NEXT: 1 2 1.00 uxth r3, r8, ror #8 -# CHECK-NEXT: 1 2 1.00 uxthle r2, r2, ror #16 -# CHECK-NEXT: 1 2 1.00 uxth r9, r3, ror #24 +# CHECK-NEXT: 1 1 0.50 uxthne r3, r9 +# CHECK-NEXT: 1 1 0.50 uxth r1, r6 +# CHECK-NEXT: 1 1 0.50 uxth r3, r8, ror #8 +# CHECK-NEXT: 1 1 0.50 uxthle r2, r2, ror #16 +# CHECK-NEXT: 1 1 0.50 uxth r9, r3, ror #24 # CHECK-NEXT: 0 0 0.00 * * U wfe # CHECK-NEXT: 0 0 0.00 * * U wfehi # CHECK-NEXT: 0 0 0.00 * * U wfi @@ -1719,7 +1719,7 @@ # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] -# CHECK-NEXT: 8.00 148.50 148.50 161.00 527.00 12.00 - - +# CHECK-NEXT: 8.00 158.50 158.50 171.00 497.00 12.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: @@ -2425,31 +2425,31 @@ # CHECK-NEXT: - - - - 1.00 - - - sxtablt r6, r2, r9, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtab r5, r1, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtab r7, r8, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - sxtab16ge r0, r1, r4 -# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r6, r2, r7 -# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r5, r8, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - sxtab16 r3, r2, r1, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - sxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: - - - 1.00 - - - - sxtab16ge r0, r1, r4 +# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r6, r2, r7 +# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: - - - 1.00 - - - - sxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: - - - 1.00 - - - - sxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - sxtah r1, r3, r9 # CHECK-NEXT: - - - - 1.00 - - - sxtahhi r6, r1, r6 # CHECK-NEXT: - - - - 1.00 - - - sxtah r3, r8, r3, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtah r9, r3, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - sxtbge r2, r4 -# CHECK-NEXT: - - - - 1.00 - - - sxtb r5, r6 -# CHECK-NEXT: - - - - 1.00 - - - sxtb r6, r9, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - sxtblo r5, r1, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - sxtb r8, r3, ror #24 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxtbge r2, r4 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r5, r6 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r6, r9, ror #8 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxtblo r5, r1, ror #16 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxtb r8, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - sxtb16 r1, r4 # CHECK-NEXT: - - - - 1.00 - - - sxtb16 r6, r7 # CHECK-NEXT: - - - - 1.00 - - - sxtb16hs r3, r5, ror #8 # CHECK-NEXT: - - - - 1.00 - - - sxtb16 r3, r1, ror #16 # CHECK-NEXT: - - - - 1.00 - - - sxtb16ge r2, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - sxthne r3, r9 -# CHECK-NEXT: - - - - 1.00 - - - sxth r1, r6 -# CHECK-NEXT: - - - - 1.00 - - - sxth r3, r8, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - sxthle r2, r2, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - sxth r9, r3, ror #24 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxthne r3, r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r1, r6 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r3, r8, ror #8 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxthle r2, r2, ror #16 +# CHECK-NEXT: - 0.50 0.50 - - - - - sxth r9, r3, ror #24 # CHECK-NEXT: - 0.50 0.50 - - - - - teq r5, #61440 # CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #-2147483638 # CHECK-NEXT: - 0.50 0.50 - - - - - teq r7, #40, #2 @@ -2538,31 +2538,31 @@ # CHECK-NEXT: - - - - 1.00 - - - uxtablt r6, r2, r9, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtab r5, r1, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtab r7, r8, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - uxtab16ge r0, r1, r4 -# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r6, r2, r7 -# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r5, r8, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - uxtab16 r3, r2, r1, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - uxtab16eq r1, r2, r3, ror #24 +# CHECK-NEXT: - - - 1.00 - - - - uxtab16ge r0, r1, r4 +# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r6, r2, r7 +# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r5, r8, ror #8 +# CHECK-NEXT: - - - 1.00 - - - - uxtab16 r3, r2, r1, ror #16 +# CHECK-NEXT: - - - 1.00 - - - - uxtab16eq r1, r2, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - uxtah r1, r3, r9 # CHECK-NEXT: - - - - 1.00 - - - uxtahhi r6, r1, r6 # CHECK-NEXT: - - - - 1.00 - - - uxtah r3, r8, r3, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtahlo r2, r2, r4, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtah r9, r3, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - uxtbge r2, r4 -# CHECK-NEXT: - - - - 1.00 - - - uxtb r5, r6 -# CHECK-NEXT: - - - - 1.00 - - - uxtb r6, r9, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - uxtblo r5, r1, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - uxtb r8, r3, ror #24 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxtbge r2, r4 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r5, r6 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r6, r9, ror #8 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxtblo r5, r1, ror #16 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxtb r8, r3, ror #24 # CHECK-NEXT: - - - - 1.00 - - - uxtb16 r1, r4 # CHECK-NEXT: - - - - 1.00 - - - uxtb16 r6, r7 # CHECK-NEXT: - - - - 1.00 - - - uxtb16hs r3, r5, ror #8 # CHECK-NEXT: - - - - 1.00 - - - uxtb16 r3, r1, ror #16 # CHECK-NEXT: - - - - 1.00 - - - uxtb16ge r2, r3, ror #24 -# CHECK-NEXT: - - - - 1.00 - - - uxthne r3, r9 -# CHECK-NEXT: - - - - 1.00 - - - uxth r1, r6 -# CHECK-NEXT: - - - - 1.00 - - - uxth r3, r8, ror #8 -# CHECK-NEXT: - - - - 1.00 - - - uxthle r2, r2, ror #16 -# CHECK-NEXT: - - - - 1.00 - - - uxth r9, r3, ror #24 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxthne r3, r9 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r1, r6 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r3, r8, ror #8 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxthle r2, r2, ror #16 +# CHECK-NEXT: - 0.50 0.50 - - - - - uxth r9, r3, ror #24 # CHECK-NEXT: - - - - - - - - wfe # CHECK-NEXT: - - - - - - - - wfehi # CHECK-NEXT: - - - - - - - - wfi diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -140,6 +140,8 @@ // Instructions should be ignored by this class because they have been split // off to join another inferred class. RecVec InstRWs; + // InstRWs processor indices. Filled in inferFromInstRWs + DenseSet InstRWProcIndices; CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef) : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {} diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -1281,6 +1281,7 @@ findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads); unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index; inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses. + SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx); } } @@ -1639,29 +1640,50 @@ } } +static void addSequences(CodeGenSchedModels &SchedModels, + const SmallVectorImpl> &Seqs, + IdxVec &Result, bool IsRead) { + for (const auto &S : Seqs) + if (!S.empty()) + Result.push_back(SchedModels.findOrInsertRW(S, IsRead)); +} + +static void dumpTransition(const CodeGenSchedModels &SchedModels, + const CodeGenSchedClass &FromSC, + const CodeGenSchedTransition &SCTrans) { + LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "(" + << FromSC.Index << ") to " + << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "(" + << SCTrans.ToClassIdx << ")" + << " on processor indices: ("; + dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n"); +} // Create a new SchedClass for each variant found by inferFromRW. Pass static void inferFromTransitions(ArrayRef LastTransitions, unsigned FromClassIdx, CodeGenSchedModels &SchedModels) { // For each PredTransition, create a new CodeGenSchedTransition, which usually // requires creating a new SchedClass. + const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx); for (ArrayRef::iterator I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) { - IdxVec OperWritesVariant; - transform(I->WriteSequences, std::back_inserter(OperWritesVariant), - [&SchedModels](ArrayRef WS) { - return SchedModels.findOrInsertRW(WS, /*IsRead=*/false); - }); - IdxVec OperReadsVariant; - transform(I->ReadSequences, std::back_inserter(OperReadsVariant), - [&SchedModels](ArrayRef RS) { - return SchedModels.findOrInsertRW(RS, /*IsRead=*/true); - }); + IdxVec OperWritesVariant, OperReadsVariant; + addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false); + addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true); CodeGenSchedTransition SCTrans; + + // Transition should not contain processor indices already assigned to + // InstRWs in this scheduling class. + llvm::copy_if(I->ProcIndices, std::back_inserter(SCTrans.ProcIndices), + [&FromSC](unsigned PIdx) { + return !FromSC.InstRWProcIndices.count(PIdx); + }); + if (SCTrans.ProcIndices.empty()) + continue; SCTrans.ToClassIdx = - SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, - OperReadsVariant, I->ProcIndices); - SCTrans.ProcIndices.assign(I->ProcIndices.begin(), I->ProcIndices.end()); + SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant, + OperReadsVariant, I->ProcIndices); + dumpTransition(SchedModels, FromSC, SCTrans); // The final PredTerm is unique set of predicates guarding the transition. RecVec Preds; transform(I->PredTerm, std::back_inserter(Preds), @@ -1684,7 +1706,6 @@ ArrayRef ProcIndices) { LLVM_DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices); dbgs() << ") "); - // Create a seed transition with an empty PredTerm and the expanded sequences // of SchedWrites for the current SchedClass. std::vector LastTransitions;