Index: llvm/test/TableGen/sched-aliases.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/sched-aliases.td
@@ -0,0 +1,50 @@
+// REQUIRES: aarch64-registered-target
+// RUN: llvm-tblgen -gen-instr-info %s -I%p/../../include -I%p/../../lib/Target/AArch64 -o %t -debug-only=subtarget-emitter 2>&1 | FileCheck %s 
+
+// Check that we've defined scheduling classes for FMOVv2f32_ns and FMOVv2f64 for Model0
+// CHECK: InstRW: New SC [[SC:[0-9]+]]:FMOVv2f32_ns on Model0
+// CHECK: InstRW: New SC [[SC2:[0-9]+]]:FMOVv2f64_ns on Model0
+
+// Generic transition for WriteV should be defined for Model0/ProcFoo0 as well as for
+// all instructions without explicitly defined scheduling classes.
+// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
+// CHECK: Adding transition from WriteV({{[0-9]+}}) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
+
+// Transition from FMOVv2f64_ns should still be added for Model0/ProcFoo0,
+// even though we've defined custom scheduling class.
+// CHECK: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_4cyc({{[0-9]+}}) on processor indices
+// CHECK-NEXT: Adding transition from FMOVv2f64_ns([[SC2]]) to Model0WriteV_2cyc({{[0-9]+}}) on processor indices
+
+// Transition from FMOVv2f32_ns should not be added for Model0/ProcFoo0,
+// because custom sched class for it is defined and it's not variant.
+// CHECK-NOT: Adding transition from FMOVv2f32_ns([[SC]])
+
+include "AArch64.td"
+
+def Model0 : SchedMachineModel {
+  let CompleteModel = 0;
+}
+
+def Model0UnitV    : ProcResource<1> { let BufferSize = 0; }
+
+let SchedModel = Model0 in {
+
+def Model0WriteV_4cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 4; }
+def Model0WriteV_2cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 2; }
+def Model0WriteV_1cyc : SchedWriteRes<[Model0UnitV]> { let Latency = 1; }
+
+def Model0QFormPred : MCSchedPredicate<CheckQForm>;
+def Model0WriteV : SchedWriteVariant<[
+       SchedVar<Model0QFormPred, [Model0WriteV_4cyc]>,
+       SchedVar<NoSchedPred, [Model0WriteV_2cyc]>]>;
+
+def : SchedAlias<WriteV, Model0WriteV>;
+
+def : InstRW<[Model0WriteV_1cyc], (instrs FMOVv2f32_ns)>;
+def : InstRW<[WriteV], (instrs FMOVv2f64_ns)>;
+}
+
+def ProcFoo0 : SubtargetFeature<"foo-0", "ARMProcFamily", "foo-0",
+                                "Test Processor #1", []>;
+
+def : ProcessorModel<"foo-0-model", Model0, [ProcFoo0]>;
Index: llvm/utils/TableGen/CodeGenSchedule.h
===================================================================
--- llvm/utils/TableGen/CodeGenSchedule.h
+++ llvm/utils/TableGen/CodeGenSchedule.h
@@ -140,6 +140,8 @@
   // Instructions should be ignored by this class because they have been split
   // off to join another inferred class.
   RecVec InstRWs;
+  // InstRWs processor indices. Filled in inferFromInstRWs
+  DenseSet<unsigned> InstRWProcIndices;
 
   CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
     : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
Index: llvm/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1281,6 +1281,7 @@
     findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
     unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index;
     inferFromRW(Writes, Reads, SCIdx, PIdx); // May mutate SchedClasses.
+    SchedClasses[SCIdx].InstRWProcIndices.insert(PIdx);
   }
 }
 
@@ -1639,29 +1640,53 @@
   }
 }
 
+static void addSequences(CodeGenSchedModels &SchedModels,
+                         const SmallVectorImpl<SmallVector<unsigned, 4>> &Seqs,
+                         IdxVec &Result, bool IsRead) {
+  for (const auto &S : Seqs)
+    if (!S.empty())
+      Result.push_back(SchedModels.findOrInsertRW(S, IsRead));
+}
+
+static void dumpTransition(const CodeGenSchedModels &SchedModels,
+                           const CodeGenSchedClass &FromSC,
+                           const CodeGenSchedTransition &SCTrans) {
+  LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "("
+                    << FromSC.Index << ") to "
+                    << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "("
+                    << SCTrans.ToClassIdx << ")"
+                    << " on processor indices: (";
+             dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n");
+}
 // Create a new SchedClass for each variant found by inferFromRW. Pass
 static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
                                  unsigned FromClassIdx,
                                  CodeGenSchedModels &SchedModels) {
   // For each PredTransition, create a new CodeGenSchedTransition, which usually
   // requires creating a new SchedClass.
+  const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
   for (ArrayRef<PredTransition>::iterator
          I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) {
-    IdxVec OperWritesVariant;
-    transform(I->WriteSequences, std::back_inserter(OperWritesVariant),
-              [&SchedModels](ArrayRef<unsigned> WS) {
-                return SchedModels.findOrInsertRW(WS, /*IsRead=*/false);
-              });
-    IdxVec OperReadsVariant;
-    transform(I->ReadSequences, std::back_inserter(OperReadsVariant),
-              [&SchedModels](ArrayRef<unsigned> RS) {
-                return SchedModels.findOrInsertRW(RS, /*IsRead=*/true);
-              });
+    IdxVec OperWritesVariant, OperReadsVariant;
+    addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false);
+    addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true);
     CodeGenSchedTransition SCTrans;
-    SCTrans.ToClassIdx =
-      SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
-                                OperReadsVariant, I->ProcIndices);
     SCTrans.ProcIndices.assign(I->ProcIndices.begin(), I->ProcIndices.end());
+
+    // Remove all processor indices from this sched transition for which
+    // we also have InstRWs.
+    SCTrans.ProcIndices.erase(
+        llvm::remove_if(SCTrans.ProcIndices,
+                        [&FromSC](unsigned PIdx) {
+                          return FromSC.InstRWProcIndices.count(PIdx);
+                        }),
+        SCTrans.ProcIndices.end());
+    if (SCTrans.ProcIndices.empty())
+      continue;
+    SCTrans.ToClassIdx =
+        SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
+                                  OperReadsVariant, I->ProcIndices);
+    dumpTransition(SchedModels, FromSC, SCTrans);
     // The final PredTerm is unique set of predicates guarding the transition.
     RecVec Preds;
     transform(I->PredTerm, std::back_inserter(Preds),
@@ -1684,7 +1709,6 @@
                                      ArrayRef<unsigned> ProcIndices) {
   LLVM_DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices);
              dbgs() << ") ");
-
   // Create a seed transition with an empty PredTerm and the expanded sequences
   // of SchedWrites for the current SchedClass.
   std::vector<PredTransition> LastTransitions;