diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td --- a/llvm/lib/Target/PowerPC/PPCCallingConv.td +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td @@ -291,6 +291,8 @@ F27, F28, F29, F30, F31, CR2, CR3, CR4 )>; +def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>; + // Common CalleeSavedRegs for SVR4 and AIX. def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -223,13 +223,13 @@ CALLEE_SAVED_GPRS32, // Add AIX's extra CSR. {PPC::R13, -76}, - // TODO: Update when we add vector support for AIX. + CALLEE_SAVED_VRS }; static const SpillSlot AIXOffsets64[] = { CALLEE_SAVED_FPRS, CALLEE_SAVED_GPRS64, - // TODO: Update when we add vector support for AIX. + CALLEE_SAVED_VRS }; if (Subtarget.is64BitELFABI()) { diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -188,7 +188,8 @@ } // 32-bit targets. if (Subtarget.isAIXABI()) - return CSR_AIX32_SaveList; + return (Subtarget.hasAltivec()) ? CSR_AIX32_Altivec_SaveList + : CSR_AIX32_SaveList; if (Subtarget.hasAltivec()) return CSR_SVR432_Altivec_SaveList; else if (Subtarget.hasSPE()) @@ -209,8 +210,11 @@ } if (Subtarget.isAIXABI()) { - assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet."); - return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask; + return TM.isPPC64() + ? (Subtarget.hasAltivec() ? CSR_64_AllRegs_Altivec_RegMask + : CSR_PPC64_RegMask) + : (Subtarget.hasAltivec() ? CSR_AIX32_Altivec_RegMask + : CSR_AIX32_RegMask); } if (CC == CallingConv::Cold) { diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll @@ -0,0 +1,222 @@ +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \ +; RUN: FileCheck --check-prefix=MIR32 %s + +; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec < %s | FileCheck --check-prefix=ASM32 %s + +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \ +; RUN: FileCheck --check-prefix=MIR64 %s + +; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \ +; RUN: -mcpu=pwr7 -mattr=+altivec < %s | FileCheck --check-prefix=ASM64 %s + + + +define dso_local void @vec_regs() { +entry: + call void asm sideeffect "", "~{v13},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() + ret void +} + +; MIR32: name: vec_regs + +; MIR32-LABEL: fixedStack: +; MIR32-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 1, type: spill-slot, offset: -32, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 2, type: spill-slot, offset: -48, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 3, type: spill-slot, offset: -64, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 4, type: spill-slot, offset: -80, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 5, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 6, type: spill-slot, offset: -112, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 7, type: spill-slot, offset: -128, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 8, type: spill-slot, offset: -144, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 9, type: spill-slot, offset: -160, size: 16, alignment: 16, stack-id: default, +; MIR32-NEXT: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '', +; MIR32-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 10, type: spill-slot, offset: -176, size: 16, alignment: 16, +; MIR32-NEXT: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true, +; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: - { id: 11, type: spill-slot, offset: -192, size: 16, alignment: 16, +; MIR32-NEXT: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true, +; MIR32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +; MIR32-NEXT: stack: + +; MIR32: liveins: $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31 + +; MIR32-DAG: STXVD2X killed $v20, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.11) +; MIR32-DAG: STXVD2X killed $v21, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.10) +; MIR32-DAG: STXVD2X killed $v22, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.9) +; MIR32-DAG: STXVD2X killed $v23, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.8) +; MIR32-DAG: STXVD2X killed $v24, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.7) +; MIR32-DAG: STXVD2X killed $v25, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.6) +; MIR32-DAG: STXVD2X killed $v26, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.5) +; MIR32-DAG: STXVD2X killed $v27, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.4) +; MIR32-DAG: STXVD2X killed $v28, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.3) +; MIR32-DAG: STXVD2X killed $v29, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR32-DAG: STXVD2X killed $v30, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR32-DAG: STXVD2X killed $v31, $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (store 16 into %fixed-stack.0) + +; MIR32: INLINEASM + +; MIR32-DAG: $v31 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR32-DAG: $v30 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR32-DAG: $v29 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR32-DAG: $v28 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.3) +; MIR32-DAG: $v27 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.4) +; MIR32-DAG: $v26 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.5) +; MIR32-DAG: $v25 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.6) +; MIR32-DAG: $v24 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.7) +; MIR32-DAG: $v23 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.8) +; MIR32-DAG: $v22 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.9) +; MIR32-DAG: $v21 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.10) +; MIR32-DAG: $v20 = LXVD2X $r{{[0-9]+}}, killed $r{{[0-9]+}} :: (load 16 from %fixed-stack.11) +; MIR32: BLR implicit $lr, implicit $rm + +; MIR64: name: vec_regs + +; MIR64-LABEL: fixedStack: +; MIR64-NEXT: - { id: 0, type: spill-slot, offset: -16, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v31', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 1, type: spill-slot, offset: -32, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v30', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 2, type: spill-slot, offset: -48, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v29', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 3, type: spill-slot, offset: -64, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v28', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 4, type: spill-slot, offset: -80, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v27', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 5, type: spill-slot, offset: -96, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v26', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 6, type: spill-slot, offset: -112, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v25', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 7, type: spill-slot, offset: -128, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v24', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 8, type: spill-slot, offset: -144, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v23', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 9, type: spill-slot, offset: -160, size: 16, alignment: 16, stack-id: default, +; MIR64-NEXT: callee-saved-register: '$v22', callee-saved-restored: true, debug-info-variable: '', +; MIR64-NEXT: debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 10, type: spill-slot, offset: -176, size: 16, alignment: 16, +; MIR64-NEXT: stack-id: default, callee-saved-register: '$v21', callee-saved-restored: true, +; MIR64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: - { id: 11, type: spill-slot, offset: -192, size: 16, alignment: 16, +; MIR64-NEXT: stack-id: default, callee-saved-register: '$v20', callee-saved-restored: true, +; MIR64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +; MIR64-NEXT: stack: + +; MIR64: liveins: $v20, $v21, $v22, $v23, $v24, $v25, $v26, $v27, $v28, $v29, $v30, $v31 + +; MIR64-DAG: STXVD2X killed $v20, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.11) +; MIR64-DAG: STXVD2X killed $v21, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.10) +; MIR64-DAG: STXVD2X killed $v22, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.9) +; MIR64-DAG: STXVD2X killed $v23, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.8) +; MIR64-DAG: STXVD2X killed $v24, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.7) +; MIR64-DAG: STXVD2X killed $v25, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.6) +; MIR64-DAG: STXVD2X killed $v26, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.5) +; MIR64-DAG: STXVD2X killed $v27, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.4) +; MIR64-DAG: STXVD2X killed $v28, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.3) +; MIR64-DAG: STXVD2X killed $v29, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.2) +; MIR64-DAG: STXVD2X killed $v30, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.1) +; MIR64-DAG: STXVD2X killed $v31, $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (store 16 into %fixed-stack.0) + +; MIR64: INLINEASM + +; MIR64-DAG: $v31 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.0) +; MIR64-DAG: $v30 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.1) +; MIR64-DAG: $v29 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.2) +; MIR64-DAG: $v28 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.3) +; MIR64-DAG: $v27 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.4) +; MIR64-DAG: $v26 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.5) +; MIR64-DAG: $v25 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.6) +; MIR64-DAG: $v24 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.7) +; MIR64-DAG: $v23 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.8) +; MIR64-DAG: $v22 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.9) +; MIR64-DAG: $v21 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.10) +; MIR64-DAG: $v20 = LXVD2X $x{{[0-9]+}}, killed $x{{[0-9]+}} :: (load 16 from %fixed-stack.11) +; MIR64: BLR8 implicit $lr8, implicit $rm + + +; ASM32-LABEL: .vec_regs: + +; ASM32: stxvd2x 52, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 53, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 54, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 55, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 56, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 57, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 58, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 59, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 60, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 61, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 62, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: stxvd2x 63, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM32-DAG: lxvd2x 63, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 62, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 61, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 60, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 59, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 58, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 57, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 56, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 55, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 54, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 53, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32-DAG: lxvd2x 52, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM32: blr + +; ASM64-LABEL: .vec_regs: + +; ASM64-DAG: stxvd2x 52, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 53, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 54, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 55, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 56, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 57, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 58, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 59, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 60, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 61, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 62, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: stxvd2x 63, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Spill +; ASM64-DAG: lxvd2x 63, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 62, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 61, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 60, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 59, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 58, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 57, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 56, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 55, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 54, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 53, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64-DAG: lxvd2x 52, {{[0-9]+}}, {{[0-9]+}} # 16-byte Folded Reload +; ASM64: blr