Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1525,8 +1525,7 @@ bool HasWinCFI = false; bool IsFunclet = false; auto WinCFI = make_scope_exit([&]() { - if (!MF.hasWinCFI()) - MF.setHasWinCFI(HasWinCFI); + assert(HasWinCFI == MF.hasWinCFI()); }); if (MBB.end() != MBBI) { @@ -1627,7 +1626,13 @@ NeedsWinCFI, &HasWinCFI); } - if (NeedsWinCFI) { + if (MF.hasWinCFI()) { + // If the prologue didn't contain any SEH opcodes and didn't set the + // MF.hasWinCFI() flag, assume the epilogue won't either, and skip the + // EpilogStart - to avoid generating CFI for functions that don't need it. + // (And as we didn't generate any prologue at all, it would be assymetrical + // to the epilogue.) By the end of the function, we assert that + // HasWinCFI is equal to MF.hasWinCFI(), to verify this assumption. HasWinCFI = true; BuildMI(MBB, LastPopI, DL, TII->get(AArch64::SEH_EpilogStart)) .setMIFlag(MachineInstr::FrameDestroy); @@ -1641,7 +1646,7 @@ emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP, {NumBytes + (int64_t)AfterCSRPopSize, MVT::i8}, TII, MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI); - if (NeedsWinCFI && HasWinCFI) + if (HasWinCFI) BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd)) .setMIFlag(MachineInstr::FrameDestroy); @@ -1720,8 +1725,7 @@ {StackRestoreBytes, MVT::i8}, TII, MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI); if (Done) { - if (NeedsWinCFI) { - HasWinCFI = true; + if (HasWinCFI) { BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd)) .setMIFlag(MachineInstr::FrameDestroy); @@ -1767,7 +1771,7 @@ {(int64_t)AfterCSRPopSize, MVT::i8}, TII, MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI); } - if (NeedsWinCFI && HasWinCFI) + if (HasWinCFI) BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd)) .setMIFlag(MachineInstr::FrameDestroy); } Index: llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll =================================================================== --- llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll +++ llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll @@ -3,8 +3,6 @@ ; CHECK-LABEL: testmhhs: ; CHECK: frintx h0, h0 ; CHECK-NEXT: fcvtzs w0, h0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i16 @testmhhs(half %x) { entry: @@ -16,8 +14,6 @@ ; CHECK-LABEL: testmhws: ; CHECK: frintx h0, h0 ; CHECK-NEXT: fcvtzs w0, h0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i32 @testmhws(half %x) { entry: @@ -29,8 +25,6 @@ ; CHECK: frintx h0, h0 ; CHECK-NEXT: fcvtzs w8, h0 ; CHECK-NEXT: sxtw x0, w8 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmhxs(half %x) { entry: Index: llvm/test/CodeGen/AArch64/lrint-conv-win.ll =================================================================== --- llvm/test/CodeGen/AArch64/lrint-conv-win.ll +++ llvm/test/CodeGen/AArch64/lrint-conv-win.ll @@ -4,8 +4,6 @@ ; CHECK: frintx [[SREG:s[0-9]+]], s0 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]] ; CHECK-NEXT: sxtw x0, [[WREG]] -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmsxs(float %x) { entry: @@ -17,8 +15,6 @@ ; CHECK-LABEL: testmsws: ; CHECK: frintx [[SREG:s[0-9]+]], s0 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]] -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i32 @testmsws(float %x) { entry: @@ -30,8 +26,6 @@ ; CHECK: frintx [[DREG:d[0-9]+]], d0 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]] ; CHECK-NEXT: sxtw x0, [[WREG]] -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmsxd(double %x) { entry: @@ -43,8 +37,6 @@ ; CHECK-LABEL: testmswd: ; CHECK: frintx [[DREG:d[0-9]+]], d0 ; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]] -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i32 @testmswd(double %x) { entry: Index: llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll =================================================================== --- llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll +++ llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll @@ -22,8 +22,6 @@ ; CHECK-LABEL: testmhxs: ; CHECK: fcvtas w8, h0 ; CHECK-NEXT: sxtw x0, w8 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmhxs(half %x) { entry: Index: llvm/test/CodeGen/AArch64/lround-conv-win.ll =================================================================== --- llvm/test/CodeGen/AArch64/lround-conv-win.ll +++ llvm/test/CodeGen/AArch64/lround-conv-win.ll @@ -3,8 +3,6 @@ ; CHECK-LABEL: testmsxs: ; CHECK: fcvtas w8, s0 ; CHECK-NEXT: sxtw x0, w8 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmsxs(float %x) { entry: @@ -15,8 +13,6 @@ ; CHECK-LABEL: testmsws: ; CHECK: fcvtas w0, s0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i32 @testmsws(float %x) { entry: @@ -27,8 +23,6 @@ ; CHECK-LABEL: testmsxd: ; CHECK: fcvtas w8, d0 ; CHECK-NEXT: sxtw x0, w8 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i64 @testmsxd(double %x) { entry: @@ -39,8 +33,6 @@ ; CHECK-LABEL: testmswd: ; CHECK: fcvtas w0, d0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret define i32 @testmswd(double %x) { entry: Index: llvm/test/CodeGen/AArch64/powi-windows.ll =================================================================== --- llvm/test/CodeGen/AArch64/powi-windows.ll +++ llvm/test/CodeGen/AArch64/powi-windows.ll @@ -11,8 +11,6 @@ ; CHECK-LABEL: d: ; CHECK: scvtf d1, w0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: b pow define float @f(float %f, i32 %i) { @@ -23,8 +21,6 @@ ; CHECK-LABEL: f: ; CHECK: scvtf s1, w0 -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: b powf define float @g(double %d, i32 %i) { Index: llvm/test/CodeGen/AArch64/win64-nocfi.ll =================================================================== --- llvm/test/CodeGen/AArch64/win64-nocfi.ll +++ llvm/test/CodeGen/AArch64/win64-nocfi.ll @@ -11,3 +11,14 @@ } declare void @llvm.trap() noreturn nounwind + +define dso_local i32 @getValue() nounwind sspstrong uwtable { +; CHECK-LABEL: getValue +; CHECK-NOT: .seh_proc +; CHECK-NOT: .seh_endprologue +; CHECK-NOT: .seh_startepilogue +; CHECK-NOT: .seh_endepilogue +; CHECK-NOT: .seh_endproc +entry: + ret i32 42 +} Index: llvm/test/CodeGen/AArch64/win_cst_pool.ll =================================================================== --- llvm/test/CodeGen/AArch64/win_cst_pool.ll +++ llvm/test/CodeGen/AArch64/win_cst_pool.ll @@ -12,8 +12,6 @@ ; CHECK: double: ; CHECK: adrp x8, __real@2000000000800001 ; CHECK-NEXT: ldr d0, [x8, __real@2000000000800001] -; CHECK-NEXT: .seh_startepilogue -; CHECK-NEXT: .seh_endepilogue ; CHECK-NEXT: ret ; MINGW: .section .rdata,"dr" @@ -23,6 +21,4 @@ ; MINGW: double: ; MINGW: adrp x8, [[LABEL]] ; MINGW-NEXT: ldr d0, [x8, [[LABEL]]] -; MINGW-NEXT: .seh_startepilogue -; MINGW-NEXT: .seh_endepilogue ; MINGW-NEXT: ret