diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1322,15 +1322,31 @@
   MachineInstr *CCMI = MRI.getVRegDef(CondReg);
   if (CCMI->getOpcode() == TargetOpcode::G_TRUNC)
     CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg());
-  if (CCMI->getOpcode() != TargetOpcode::G_ICMP)
+
+  unsigned CCMIOpc = CCMI->getOpcode();
+  if (CCMIOpc != TargetOpcode::G_ICMP && CCMIOpc != TargetOpcode::G_FCMP)
     return false;
 
+  MachineIRBuilder MIB(I);
   Register LHS = CCMI->getOperand(2).getReg();
   Register RHS = CCMI->getOperand(3).getReg();
+  auto Pred =
+      static_cast<CmpInst::Predicate>(CCMI->getOperand(1).getPredicate());
+
+  if (CCMIOpc == TargetOpcode::G_FCMP) {
+    // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
+    // totally clean.  Some of them require two branches to implement.
+    emitFPCompare(LHS, RHS, MIB);
+    AArch64CC::CondCode CC1, CC2;
+    changeFCMPPredToAArch64CC(Pred, CC1, CC2);
+    MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC1).addMBB(DestMBB);
+    if (CC2 != AArch64CC::AL)
+      MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC2).addMBB(DestMBB);
+    I.eraseFromParent();
+    return true;
+  }
+
   auto VRegAndVal = getConstantVRegValWithLookThrough(RHS, MRI);
-  MachineIRBuilder MIB(I);
-  CmpInst::Predicate Pred =
-      (CmpInst::Predicate)CCMI->getOperand(1).getPredicate();
   MachineInstr *LHSMI = getDefIgnoringCopies(LHS, MRI);
 
   // When we can emit a TB(N)Z, prefer that.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
@@ -0,0 +1,555 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Test that we don't have to emit a CSINC when emitting a G_FCMP being used by
+# a G_BRCOND.
+#
+# Condition codes which require more than one instruction should have two Bccs.
+
+...
+---
+name:            oeq
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: oeq
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(oeq), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ogt
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ogt
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 12, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ogt), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            oge
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: oge
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 10, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(oge), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            olt
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: olt
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 4, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(olt), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ole
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ole
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 9, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ole), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            one
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: one
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 4, %bb.2, implicit $nzcv
+  ; CHECK:   Bcc 12, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(one), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ord
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ord
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 7, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ord), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            uno
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: uno
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 6, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(uno), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ueq
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ueq
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
+  ; CHECK:   Bcc 6, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ueq), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ugt
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ugt
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 8, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ugt), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            uge
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: uge
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 5, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(uge), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ult
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ult
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ult), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            ule
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: ule
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 13, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(ule), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1
+
+...
+---
+name:            une
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: une
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK:   liveins: $s0, $s1, $w0, $w1
+  ; CHECK:   %cmp_lhs:fpr32 = COPY $s0
+  ; CHECK:   %cmp_rhs:fpr32 = COPY $s1
+  ; CHECK:   FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+  ; CHECK:   Bcc 1, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   $s0 = COPY %cmp_lhs
+  ; CHECK:   RET_ReallyLR implicit $s0
+  ; CHECK: bb.2:
+  ; CHECK:   $s1 = COPY %cmp_rhs
+  ; CHECK:   RET_ReallyLR implicit $s1
+  bb.0:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $s0, $s1, $w0, $w1
+
+    %cmp_lhs:fpr(s32) = COPY $s0
+    %cmp_rhs:fpr(s32) = COPY $s1
+    %fcmp:gpr(s32) = G_FCMP floatpred(une), %cmp_lhs(s32), %cmp_rhs
+    %trunc:gpr(s1) = G_TRUNC %fcmp(s32)
+    G_BRCOND %trunc(s1), %bb.2
+    G_BR %bb.1
+  bb.1:
+    $s0 = COPY %cmp_lhs
+    RET_ReallyLR implicit $s0
+  bb.2:
+    $s1 = COPY %cmp_rhs
+    RET_ReallyLR implicit $s1