diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1399,8 +1399,13 @@ /// If the specified instruction defines any predicate /// or condition code register(s) used for predication, returns true as well /// as the definition predicate(s) by reference. - virtual bool DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const { + /// SkipDead should be set to false at any point that dead + /// predicate instructions should be considered as being defined. + /// A dead predicate instruction is one that is guaranteed to be removed + /// after a call to PredicateInstruction. + virtual bool ClobbersPredicate(MachineInstr &MI, + std::vector &Pred, + bool SkipDead) const { return false; } diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -751,7 +751,7 @@ // A pred-clobbering instruction in the shared portion prevents // if-conversion. std::vector PredDefs; - if (TII->DefinesPredicate(*TIB, PredDefs)) + if (TII->ClobbersPredicate(*TIB, PredDefs, false)) return false; // If we get all the way to the branch instructions, don't count them. if (!TIB->isBranch()) @@ -1146,7 +1146,7 @@ // FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are // still potentially predicable. std::vector PredDefs; - if (TII->DefinesPredicate(MI, PredDefs)) + if (TII->ClobbersPredicate(MI, PredDefs, true)) BBI.ClobbersPred = true; if (!TII->isPredicable(MI)) { diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -194,8 +194,8 @@ unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override; - bool DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const override; + bool ClobbersPredicate(MachineInstr &MI, std::vector &Pred, + bool SkipDead) const override; bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override; diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -963,8 +963,9 @@ return false; } -bool R600InstrInfo::DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const { +bool R600InstrInfo::ClobbersPredicate(MachineInstr &MI, + std::vector &Pred, + bool SkipDead) const { return isPredicateSetter(MI.getOpcode()); } diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -171,8 +171,8 @@ bool SubsumesPredicate(ArrayRef Pred1, ArrayRef Pred2) const override; - bool DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const override; + bool ClobbersPredicate(MachineInstr &MI, std::vector &Pred, + bool SkipDead) const override; bool isPredicable(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -589,8 +589,9 @@ } } -bool ARMBaseInstrInfo::DefinesPredicate( - MachineInstr &MI, std::vector &Pred) const { +bool ARMBaseInstrInfo::ClobbersPredicate(MachineInstr &MI, + std::vector &Pred, + bool SkipDead) const { bool Found = false; for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -238,8 +238,8 @@ /// If the specified instruction defines any predicate /// or condition code register(s) used for predication, returns true as well /// as the definition predicate(s) by reference. - bool DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const override; + bool ClobbersPredicate(MachineInstr &MI, std::vector &Pred, + bool SkipDead) const override; /// Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1639,8 +1639,9 @@ return false; } -bool HexagonInstrInfo::DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const { +bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI, + std::vector &Pred, + bool SkipDead) const { const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) { diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -472,8 +472,8 @@ bool SubsumesPredicate(ArrayRef Pred1, ArrayRef Pred2) const override; - bool DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const override; + bool ClobbersPredicate(MachineInstr &MI, std::vector &Pred, + bool SkipDead) const override; // Comparison optimization. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1802,8 +1802,9 @@ return false; } -bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI, - std::vector &Pred) const { +bool PPCInstrInfo::ClobbersPredicate(MachineInstr &MI, + std::vector &Pred, + bool SkipDead) const { // Note: At the present time, the contents of Pred from this function is // unused by IfConversion. This implementation follows ARM by pushing the // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of