Index: llvm/lib/CodeGen/ReachingDefAnalysis.cpp =================================================================== --- llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -594,30 +594,59 @@ bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &Visited, InstSet &ToRemove, InstSet &Ignore) const { - if (Visited.count(MI) || Ignore.count(MI)) - return true; - else if (mayHaveSideEffects(*MI)) { - // Unless told to ignore the instruction, don't remove anything which has - // side effects. - return false; - } + // Recursively collect uses of a MachineInstr's definitions. + std::function collectDefChain = + [this, &collectDefChain, &Visited, &Ignore](MachineInstr *MI) -> void { + if (Ignore.count(MI)) + return; - Visited.insert(MI); - for (auto &MO : MI->operands()) { - if (!isValidRegDef(MO)) - continue; + Visited.insert(MI); + for (auto &MO : MI->operands()) { + if (!isValidRegDef(MO)) + continue; - SmallPtrSet Uses; - getGlobalUses(MI, MO.getReg(), Uses); + SmallPtrSet Uses; + getGlobalUses(MI, MO.getReg(), Uses); + for (auto *Use : Uses) + if (!Visited.count(Use) && !Ignore.count(Use)) + collectDefChain(Use); + } + }; - for (auto I : Uses) { - if (Ignore.count(I) || ToRemove.count(I)) - continue; - if (!isSafeToRemove(I, Visited, ToRemove, Ignore)) - return false; + // Collect a def chain beginning from MI. + collectDefChain(MI); + + // If we remove all of Visited, then collect the possible operands that would + // be dead too. + SmallPtrSet Dead; + for (auto *I : Visited) + if (!Ignore.count(I)) + collectKilledOperands(I, Dead); + + // Inspect the chain of uses. + for (auto *Use : Visited) { + if (Use == MI || Ignore.count(Use)) + continue; + // Unless told to ignore the instruction, don't remove anything which has + // side effects. + if (mayHaveSideEffects(*Use)) + return false; + + // Inspect each incoming reaching def for the register(s) that this + // instruction defines. If we remove Use, would there be instructions left + // remaining that would alter the program incorrectly? + for (auto &MO : Use->operands()) { + if (isValidRegDef(MO)) { + SmallPtrSet Defs; + getGlobalReachingDefs(Use, MO.getReg(), Defs); + + for (auto *Def : Defs) + if (!Visited.count(Def) && !Dead.count(Def) && !Ignore.count(Def)) + return false; + } } } - ToRemove.insert(MI); + ToRemove.insert(Visited.begin(), Visited.end()); return true; } Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp =================================================================== --- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -1198,14 +1198,16 @@ return false; } - // Check that the only instruction using LoopDec is LoopEnd. - // TODO: Check for copy chains that really have no effect. - SmallPtrSet Uses; - RDA->getReachingLocalUses(LoLoop.Dec, ARM::LR, Uses); - if (Uses.size() > 1 || !Uses.count(LoLoop.End)) { + // See if it's possible to remove the chain of instructions that performs the + // iteration counting. + SmallPtrSet Uses; + SmallPtrSet Killed = { LoLoop.End }; + if (!RDA->isSafeToRemove(LoLoop.Dec, Uses, Killed)) { LLVM_DEBUG(dbgs() << "ARM Loops: Unable to remove LoopDec.\n"); LoLoop.Revert = true; + return false; } + LoLoop.ToRemove.insert(Uses.begin(), Uses.end()); LoLoop.CheckLegality(BBUtils.get()); Expand(LoLoop); return true; Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -126,7 +126,7 @@ ; CHECK-LABEL: name: size_limit ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $lr ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -144,21 +144,22 @@ ; CHECK: bb.1.for.body: ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load 4 from %stack.4) - ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %stack.5) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg ; CHECK: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load 4 from %stack.6) - ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3) + ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3) ; CHECK: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.7) ; CHECK: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg ; CHECK: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) ; CHECK: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) ; CHECK: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store 4 into %stack.3) - ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr + ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.3, 1 /* CC::ne */, $cpsr ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg ; CHECK: bb.2.for.cond.cleanup: ; CHECK: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir @@ -223,7 +223,7 @@ ; CHECK-LABEL: name: test1 ; CHECK: bb.0.bb: ; CHECK: successors: %bb.8(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -268,7 +268,7 @@ ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418) - ; CHECK: $lr = tMOVr killed $r12, 14 /* CC::al */, $noreg + ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219) @@ -296,8 +296,8 @@ ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1) - ; CHECK: t2CMPri killed $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr + ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.4, 1 /* CC::ne */, $cpsr ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg ; CHECK: bb.5.bb13: ; CHECK: successors: %bb.8(0x30000000), %bb.6(0x50000000) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir @@ -224,7 +224,7 @@ ; CHECK-LABEL: name: test1 ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -265,18 +265,19 @@ ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $r3 + ; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: bb.5.bb28: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $lr ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418) - ; CHECK: dead $r12 = tMOVr $lr, 14 /* CC::al */, $noreg + ; CHECK: $r12 = tMOVr $lr, 14 /* CC::al */, $noreg ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219) ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg @@ -299,7 +300,9 @@ ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 + ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.5, 1 /* CC::ne */, $cpsr + ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg ; CHECK: bb.6.bb13: ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir @@ -224,7 +224,7 @@ ; CHECK-LABEL: name: test1 ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -265,17 +265,18 @@ ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r8 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg - ; CHECK: $lr = t2DLS killed renamable $r3 + ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: bb.5.bb28: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 + ; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $lr ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep617) ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep418) ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep219) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 /* CC::al */, $noreg ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep219) ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg @@ -298,7 +299,9 @@ ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 /* CC::al */, $noreg ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep1) - ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 + ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.5, 1 /* CC::ne */, $cpsr + ; CHECK: tB %bb.6, 14 /* CC::al */, $noreg ; CHECK: bb.6.bb13: ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir @@ -84,15 +84,23 @@ ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r2 + ; CHECK: renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg + ; CHECK: renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg + ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) - ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK: dead $lr = MVE_DLSTP_32 killed renamable $r2 + ; CHECK: $r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0 + ; CHECK: liveins: $q0, $r0, $r1 + ; CHECK: $lr = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK: renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, undef renamable $q1 - ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: tB %bb.4, 14 /* CC::al */, $noreg ; CHECK: bb.3: ; CHECK: successors: %bb.4(0x80000000) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir @@ -143,7 +143,7 @@ ; CHECK-LABEL: name: remove_mov_lr_chain ; CHECK: bb.0.entry: ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 + ; CHECK: liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -187,8 +187,9 @@ ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4) ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK: $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg - ; CHECK: tBcc %bb.4, 1 /* CC::ne */, killed $cpsr + ; CHECK: $r5 = tMOVr $lr, 14 /* CC::al */, $noreg + ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.4, 1 /* CC::ne */, $cpsr ; CHECK: tB %bb.5, 14 /* CC::al */, $noreg ; CHECK: bb.5.middle.block: ; CHECK: successors: %bb.7(0x80000000) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir @@ -128,19 +128,15 @@ ; CHECK: bb.1.loop.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: dead $lr = MVE_DLSTP_32 killed renamable $r3 - ; CHECK: $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg + ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.2.loop.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.addr.b, align 4) ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.addr.a, align 4) ; CHECK: renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg ; CHECK: renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg :: (store 16 into %ir.addr.c, align 4) - ; CHECK: dead $lr = MVE_LETP killed renamable $lr, %bb.2 + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.exit: ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc bb.0.entry: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir @@ -94,7 +94,7 @@ ; CHECK-LABEL: name: do_copy ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r1, $r2, $r7 + ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 @@ -110,11 +110,11 @@ ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: t2IT 2, 8, implicit-def $itstate - ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate + ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 /* CC::hs */, killed $cpsr, implicit renamable $r3, implicit killed $itstate ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep4) - ; CHECK: renamable $lr = tMOVr killed $lr, 14 /* CC::al */, $noreg + ; CHECK: renamable $lr = tMOVr $lr, 14 /* CC::al */, $noreg ; CHECK: t2CMPri $lr, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr + ; CHECK: tBcc %bb.1, 1 /* CC::ne */, $cpsr ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg ; CHECK: bb.2.while.end: ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg Index: llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll +++ llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll @@ -256,7 +256,6 @@ ; CHECK-NEXT: adr r7, .LCPI1_1 ; CHECK-NEXT: add.w r12, r0, r3, lsl #2 ; CHECK-NEXT: vldrw.u32 q1, [r7] -; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: str r3, [sp] @ 4-byte Spill ; CHECK-NEXT: mov.w r3, #-1 ; CHECK-NEXT: mvn r9, #-2147483648 @@ -300,6 +299,7 @@ ; CHECK-NEXT: csetm r4, ne ; CHECK-NEXT: mov lr, r2 ; CHECK-NEXT: vmov.32 q4[2], r4 +; CHECK-NEXT: sub.w lr, lr, #1 ; CHECK-NEXT: vmov.32 q4[3], r4 ; CHECK-NEXT: vmov r4, s14 ; CHECK-NEXT: vbic q5, q0, q4 @@ -389,8 +389,10 @@ ; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s11, s18 ; CHECK-NEXT: vstrb.8 q2, [r8], #16 -; CHECK-NEXT: le lr, .LBB1_4 -; CHECK-NEXT: @ %bb.5: @ %middle.block +; CHECK-NEXT: cmp.w lr, #0 +; CHECK-NEXT: bne.w .LBB1_4 +; CHECK-NEXT: b .LBB1_5 +; CHECK-NEXT: .LBB1_5: @ %middle.block ; CHECK-NEXT: ldrd r2, r3, [sp] @ 8-byte Folded Reload ; CHECK-NEXT: cmp r2, r3 ; CHECK-NEXT: beq .LBB1_8