Index: clang/include/clang/Basic/Attr.td
===================================================================
--- clang/include/clang/Basic/Attr.td
+++ clang/include/clang/Basic/Attr.td
@@ -364,6 +364,7 @@
 def TargetMips32 : TargetArch<["mips", "mipsel"]>;
 def TargetAnyMips : TargetArch<["mips", "mipsel", "mips64", "mips64el"]>;
 def TargetMSP430 : TargetArch<["msp430"]>;
+def TargetM680x0 : TargetArch<["m680x0"]>;
 def TargetRISCV : TargetArch<["riscv32", "riscv64"]>;
 def TargetX86 : TargetArch<["x86"]>;
 def TargetAnyX86 : TargetArch<["x86", "x86_64"]>;
@@ -1514,6 +1515,16 @@
   let Documentation = [MipsShortCallStyleDocs];
 }
 
+def M680x0Interrupt : InheritableAttr, TargetSpecificAttr<TargetM680x0> {
+  // NOTE: If you add any additional spellings, ARMInterrupt's, MipsInterrupt's
+  // and AnyX86Interrupt's spellings must match.
+  let Spellings = [GNU<"interrupt">];
+  let Args = [UnsignedArgument<"Number">];
+  let ParseKind = "Interrupt";
+  let HasCustomParsing = 1;
+  let Documentation = [Undocumented];
+}
+
 def Mode : Attr {
   let Spellings = [GCC<"mode">];
   let Subjects = SubjectList<[Var, Enum, TypedefName, Field], ErrorDiag>;
Index: clang/lib/Basic/CMakeLists.txt
===================================================================
--- clang/lib/Basic/CMakeLists.txt
+++ clang/lib/Basic/CMakeLists.txt
@@ -75,6 +75,7 @@
   Targets/Le64.cpp
   Targets/MSP430.cpp
   Targets/Mips.cpp
+  Targets/M680x0.cpp
   Targets/NVPTX.cpp
   Targets/OSTargets.cpp
   Targets/PNaCl.cpp
Index: clang/lib/Basic/Targets.cpp
===================================================================
--- clang/lib/Basic/Targets.cpp
+++ clang/lib/Basic/Targets.cpp
@@ -22,6 +22,7 @@
 #include "Targets/Hexagon.h"
 #include "Targets/Lanai.h"
 #include "Targets/Le64.h"
+#include "Targets/M680x0.h"
 #include "Targets/MSP430.h"
 #include "Targets/Mips.h"
 #include "Targets/NVPTX.h"
@@ -303,6 +304,16 @@
       return new MipsTargetInfo(Triple, Opts);
     }
 
+  case llvm::Triple::m680x0:
+    switch (os) {
+    case llvm::Triple::Linux:
+      return new LinuxTargetInfo<M680x0TargetInfo>(Triple, Opts);
+    case llvm::Triple::NetBSD:
+      return new NetBSDTargetInfo<M680x0TargetInfo>(Triple, Opts);
+    default:
+      return new M680x0TargetInfo(Triple, Opts);
+    }
+
   case llvm::Triple::le32:
     switch (os) {
     case llvm::Triple::NaCl:
Index: clang/lib/Basic/Targets/M680x0.h
===================================================================
--- /dev/null
+++ clang/lib/Basic/Targets/M680x0.h
@@ -0,0 +1,57 @@
+//===--- M680x0.h - Declare M680x0 target feature support -------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares M680x0 TargetInfo objects.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef M680X0_H_LTNCIPAD
+#define M680X0_H_LTNCIPAD
+
+#include "OSTargets.h"
+#include "clang/Basic/TargetInfo.h"
+#include "clang/Basic/TargetOptions.h"
+#include "llvm/ADT/Triple.h"
+#include "llvm/Support/Compiler.h"
+
+namespace clang {
+namespace targets {
+
+class LLVM_LIBRARY_VISIBILITY M680x0TargetInfo : public TargetInfo {
+  static const char *const GCCRegNames[];
+
+  enum CPUKind {
+    CK_Unknown,
+    CK_68000,
+    CK_68010,
+    CK_68020,
+    CK_68030,
+    CK_68040,
+    CK_68060
+  } CPU = CK_Unknown;
+
+public:
+  M680x0TargetInfo(const llvm::Triple &Triple, const TargetOptions &);
+
+  void getTargetDefines(const LangOptions &Opts,
+                        MacroBuilder &Builder) const override;
+  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
+  bool hasFeature(StringRef Feature) const override;
+  ArrayRef<const char *> getGCCRegNames() const override;
+  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
+  bool validateAsmConstraint(const char *&Name,
+                             TargetInfo::ConstraintInfo &info) const override;
+  const char *getClobbers() const override;
+  BuiltinVaListKind getBuiltinVaListKind() const override;
+  bool setCPU(const std::string &Name) override;
+};
+
+} // namespace targets
+} // namespace clang
+
+#endif /* end of include guard: M680X0_H_LTNCIPAD */
Index: clang/lib/Basic/Targets/M680x0.cpp
===================================================================
--- /dev/null
+++ clang/lib/Basic/Targets/M680x0.cpp
@@ -0,0 +1,163 @@
+//===--- M680x0.cpp - Implement M680x0 targets feature support-------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements M680x0 TargetInfo objects.
+//
+//===----------------------------------------------------------------------===//
+
+#include "M680x0.h"
+#include "clang/Basic/Builtins.h"
+#include "clang/Basic/Diagnostic.h"
+#include "clang/Basic/TargetBuiltins.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/TargetParser.h"
+#include <cstring>
+
+namespace clang {
+namespace targets {
+
+M680x0TargetInfo::M680x0TargetInfo(const llvm::Triple &Triple,
+                                   const TargetOptions &)
+    : TargetInfo(Triple) {
+
+  std::string Layout = "";
+
+  // M680x0 is Big Endian
+  Layout += "E";
+
+  // FIXME how to wire it with the used object format?
+  Layout += "-m:e";
+
+  // M680x0 pointers are always 32 bit wide even for 16 bit cpus
+  Layout += "-p:32:32";
+
+  // M680x0 integer data types
+  Layout += "-i8:8:8-i16:16:16-i32:32:32";
+
+  // FIXME no floats at the moment
+
+  // The registers can hold 8, 16, 32 bits
+  Layout += "-n8:16:32";
+
+  // Aggregates are 32 bit aligned and stack is 16 bit aligned
+  Layout += "-a:0:32-S16";
+
+  resetDataLayout(Layout);
+
+  SizeType = UnsignedInt;
+  PtrDiffType = SignedInt;
+  IntPtrType = SignedInt;
+}
+
+bool M680x0TargetInfo::setCPU(const std::string &Name) {
+  StringRef N = Name;
+  CPU = llvm::StringSwitch<CPUKind>(N.lower())
+            .Case("generic", CK_68000)
+            .Case("68000", CK_68000)
+            .Case("68010", CK_68010)
+            .Case("68020", CK_68020)
+            .Case("68030", CK_68030)
+            .Case("68040", CK_68040)
+            .Case("68060", CK_68060)
+            .Default(CK_Unknown);
+  return CPU != CK_Unknown;
+}
+
+void M680x0TargetInfo::getTargetDefines(const LangOptions &Opts,
+                                        MacroBuilder &Builder) const {
+  using llvm::Twine;
+
+  Builder.defineMacro("M680x0");
+  Builder.defineMacro("__M680x0__");
+  Builder.defineMacro("__M68K__");
+  Builder.defineMacro("__m68k__");
+
+  Builder.defineMacro("mc68000");
+  Builder.defineMacro("__mc68000");
+  Builder.defineMacro("__mc68000__");
+
+  // For sub-architecture
+  const char *RawDef = "";
+  switch (CPU) {
+  case CK_68010:
+    RawDef = "mc68010";
+    break;
+  case CK_68020:
+    RawDef = "mc68020";
+    break;
+  case CK_68030:
+    RawDef = "mc68030";
+    break;
+  case CK_68040:
+    RawDef = "mc68040";
+    break;
+  case CK_68060:
+    RawDef = "mc68060";
+    break;
+  default:
+    RawDef = "";
+  }
+  if (::strlen(RawDef) > 0) {
+    Builder.defineMacro(RawDef);
+    Twine Def = Twine("__") + RawDef;
+    Builder.defineMacro(Def);
+    Builder.defineMacro(Def + "__");
+  }
+}
+
+ArrayRef<Builtin::Info> M680x0TargetInfo::getTargetBuiltins() const {
+  // FIXME: Implement.
+  return None;
+}
+
+bool M680x0TargetInfo::hasFeature(StringRef Feature) const {
+  // FIXME elaborate moar
+  return Feature == "M68000";
+}
+
+const char *const M680x0TargetInfo::GCCRegNames[] = {
+    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+    "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7"};
+
+ArrayRef<const char *> M680x0TargetInfo::getGCCRegNames() const {
+  return llvm::makeArrayRef(GCCRegNames);
+}
+
+ArrayRef<TargetInfo::GCCRegAlias> M680x0TargetInfo::getGCCRegAliases() const {
+  // No aliases.
+  return None;
+}
+
+bool M680x0TargetInfo::validateAsmConstraint(
+    const char *&Name, TargetInfo::ConstraintInfo &info) const {
+  // FIXME: implement
+  switch (*Name) {
+  case 'K': // the constant 1
+  case 'L': // constant -1^20 .. 1^19
+  case 'M': // constant 1-4:
+    return true;
+  }
+  // No targets constraints for now.
+  return false;
+}
+
+const char *M680x0TargetInfo::getClobbers() const {
+  // FIXME: Is this really right?
+  return "";
+}
+
+M680x0TargetInfo::BuiltinVaListKind
+M680x0TargetInfo::getBuiltinVaListKind() const {
+  // FIXME: implement
+  return TargetInfo::CharPtrBuiltinVaList;
+}
+
+} // namespace targets
+} // namespace clang
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -8064,6 +8064,45 @@
   return false;
 }
 
+//===----------------------------------------------------------------------===//
+// M680x0 ABI Implementation
+//===----------------------------------------------------------------------===//
+
+namespace {
+
+class M680x0TargetCodeGenInfo : public TargetCodeGenInfo {
+public:
+  M680x0TargetCodeGenInfo(CodeGenTypes &CGT)
+      : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {}
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+                           CodeGen::CodeGenModule &M) const override;
+};
+
+} // namespace
+
+// TODO Does not actually work right now
+void M680x0TargetCodeGenInfo::setTargetAttributes(
+    const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
+  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
+    if (const M680x0InterruptAttr *attr = FD->getAttr<M680x0InterruptAttr>()) {
+      // Handle 'interrupt' attribute:
+      llvm::Function *F = cast<llvm::Function>(GV);
+
+      // Step 1: Set ISR calling convention.
+      F->setCallingConv(llvm::CallingConv::M680x0_INTR);
+
+      // Step 2: Add attributes goodness.
+      F->addFnAttr(llvm::Attribute::NoInline);
+
+      // ??? is this right
+      // Step 3: Emit ISR vector alias.
+      unsigned Num = attr->getNumber() / 2;
+      llvm::GlobalAlias::create(llvm::Function::ExternalLinkage,
+                                "__isr_" + Twine(Num), F);
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // AVR ABI Implementation.
 //===----------------------------------------------------------------------===//
Index: clang/lib/Sema/SemaDeclAttr.cpp
===================================================================
--- clang/lib/Sema/SemaDeclAttr.cpp
+++ clang/lib/Sema/SemaDeclAttr.cpp
@@ -5797,6 +5797,39 @@
   D->addAttr(::new (S.Context) MipsInterruptAttr(S.Context, AL, Kind));
 }
 
+static void handleM680x0InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
+  if (!checkAttributeNumArgs(S, AL, 1))
+    return;
+
+  if (!AL.isArgExpr(0)) {
+    S.Diag(AL.getLoc(), diag::err_attribute_argument_type)
+        << AL << AANT_ArgumentIntegerConstant;
+    return;
+  }
+
+  // FIXME: Check for decl - it should be void ()(void).
+
+  Expr *NumParamsExpr = static_cast<Expr *>(AL.getArgAsExpr(0));
+  auto MaybeNumParams = NumParamsExpr->getIntegerConstantExpr(S.Context);
+  if (!MaybeNumParams) {
+    S.Diag(AL.getLoc(), diag::err_attribute_argument_type)
+        << AL << AANT_ArgumentIntegerConstant
+        << NumParamsExpr->getSourceRange();
+    return;
+  }
+
+  unsigned Num = MaybeNumParams->getLimitedValue(255);
+  if ((Num & 1) || Num > 30) {
+    S.Diag(AL.getLoc(), diag::err_attribute_argument_out_of_bounds)
+        << AL << (int)MaybeNumParams->getSExtValue()
+        << NumParamsExpr->getSourceRange();
+    return;
+  }
+
+  D->addAttr(::new (S.Context) M680x0InterruptAttr(S.Context, AL, Num));
+  D->addAttr(UsedAttr::CreateImplicit(S.Context));
+}
+
 static void handleAnyX86InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) {
   // Semantic checks for a function with the 'interrupt' attribute.
   // a) Must be a function.
@@ -6069,6 +6102,9 @@
   case llvm::Triple::mips:
     handleMipsInterruptAttr(S, D, AL);
     break;
+  case llvm::Triple::m680x0:
+    handleM680x0InterruptAttr(S, D, AL);
+    break;
   case llvm::Triple::x86:
   case llvm::Triple::x86_64:
     handleAnyX86InterruptAttr(S, D, AL);