Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -312,6 +312,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMMR6LlSc(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, @@ -1436,6 +1441,28 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeMMR6LlSc(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int64_t Offset = SignExtend64<12>(Insn & 0xfff); + unsigned Rt = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + if (Inst.getOpcode() == Mips::SC_MMR6) { + Inst.addOperand(MCOperand::CreateReg(Rt)); + } + + Inst.addOperand(MCOperand::CreateReg(Rt)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -111,3 +111,18 @@ let Inst{20-16} = rs; let Inst{15-0} = imm; } + +class POOL32C_LL_SC_FM funct> : MipsR6Inst { + bits<5> rt; + bits<21> addr; + + bits<32> Inst; + + let Inst{31-26} = 0b011000; + let Inst{25-21} = rt; + let Inst{20-16} = addr{20-16}; + let Inst{15-12} = funct; + let Inst{11-0} = addr{11-0}; + + string DecoderMethod = "DecodeMMR6LlSc"; +} Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -28,7 +28,9 @@ class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>; class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101001>; class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>; +class LL_MMR6_ENC : POOL32C_LL_SC_FM<0b0011>; class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>; +class SC_MMR6_ENC : POOL32C_LL_SC_FM<0b1011>; class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>; class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>; @@ -126,6 +128,29 @@ list Defs = [AT]; } +class LL_MMR6_DESC_BASE + : MMR6Arch { + dag OutOperandList = (outs GPROpnd:$rt); + dag InOperandList = (ins mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + bit mayLoad = 1; +} + +class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", GPR32Opnd>; + +class SC_MMR6_DESC_BASE + : MMR6Arch { + dag OutOperandList = (outs GPROpnd:$dst); + dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); + string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); + list Pattern = []; + bit mayStore = 1; + string Constraints = "$rt = $dst"; +} + +class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", GPR32Opnd>; + class SELEQNE_Z_MMR6_DESC_BASE : MMR6Arch { dag OutOperandList = (outs GPROpnd:$rd); @@ -157,7 +182,9 @@ def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6; def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6; def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6; +def LL_MMR6 : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6; def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6; +def SC_MMR6 : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6; def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, ISA_MICROMIPS32R6; def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -594,7 +594,8 @@ class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2>; -class LL_R6_DESC_BASE { +class LL_R6_DESC_BASE + : MipsR6Arch { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins mem_simm9:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); @@ -604,7 +605,8 @@ class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>; -class SC_R6_DESC_BASE { +class SC_R6_DESC_BASE + : MipsR6Arch { dag OutOperandList = (outs GPROpnd:$dst); dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); @@ -694,7 +696,7 @@ def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6; -def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; +def LL_R6 : R6MMR6Rel, LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6; def LSA_R6 : LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6; def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; @@ -721,7 +723,7 @@ def PREF_R6 : PREF_ENC, PREF_DESC, ISA_MIPS32R6; def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; -def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; +def SC_R6 : R6MMR6Rel, SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6; def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6; def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6; def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32; Index: test/MC/Disassembler/Mips/micromips32r6.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6.txt +++ test/MC/Disassembler/Mips/micromips32r6.txt @@ -41,3 +41,9 @@ # CHECK: selnez $2, $3, $4 0x00 0x83 0x11 0x80 + +# CHECK: ll $2, -153($18) +0x60 0x52 0x3f 0x67 + +# CHECK: sc $15, -40($19) +0x61 0xf3 0xbf 0xd8 Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -15,3 +15,5 @@ lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x83,0x11,0x40] selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x83,0x11,0x80] + ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x60,0x52,0x3f,0x67] + sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x61,0xf3,0xbf,0xd8]