diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -368,12 +368,12 @@ ActiveBlocks.clear(); } - // Set B[i] = C for every live bundle where B[i] was NoCand. + // Set B[I] = C for every live bundle where B[I] was NoCand. unsigned getBundles(SmallVectorImpl &B, unsigned C) { unsigned Count = 0; - for (unsigned i : LiveBundles.set_bits()) - if (B[i] == NoCand) { - B[i] = C; + for (unsigned I : LiveBundles.set_bits()) + if (B[I] == NoCand) { + B[I] = C; Count++; } return Count; @@ -1181,9 +1181,9 @@ // Reset interference dependent info. SplitConstraints.resize(UseBlocks.size()); BlockFrequency StaticCost = 0; - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; + for (unsigned I = 0; I != UseBlocks.size(); ++I) { + const SplitAnalysis::BlockInfo &BI = UseBlocks[I]; + SpillPlacement::BlockConstraint &BC = SplitConstraints[I]; BC.Number = BI.MBB->getNumber(); Intf.moveToBlock(BC.Number); @@ -1254,8 +1254,7 @@ unsigned TBS[GroupSize]; unsigned B = 0, T = 0; - for (unsigned i = 0; i != Blocks.size(); ++i) { - unsigned Number = Blocks[i]; + for (unsigned Number : Blocks) { Intf.moveToBlock(Number); if (!Intf.hasInterference()) { @@ -1312,8 +1311,7 @@ while (true) { ArrayRef NewBundles = SpillPlacer->getRecentPositive(); // Find new through blocks in the periphery of PrefRegBundles. - for (int i = 0, e = NewBundles.size(); i != e; ++i) { - unsigned Bundle = NewBundles[i]; + for (unsigned Bundle : NewBundles) { // Look at all blocks connected to Bundle in the full graph. ArrayRef Blocks = Bundles->getBlocks(Bundle); for (ArrayRef::iterator I = Blocks.begin(), E = Blocks.end(); @@ -1393,8 +1391,8 @@ } LLVM_DEBUG({ - for (int i : Cand.LiveBundles.set_bits()) - dbgs() << " EB#" << i; + for (int I : Cand.LiveBundles.set_bits()) + dbgs() << " EB#" << I; dbgs() << ".\n"; }); return true; @@ -1405,8 +1403,7 @@ BlockFrequency RAGreedy::calcSpillCost() { BlockFrequency Cost = 0; ArrayRef UseBlocks = SA->getUseBlocks(); - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; + for (const SplitAnalysis::BlockInfo &BI : UseBlocks) { unsigned Number = BI.MBB->getNumber(); // We normally only need one spill instruction - a load or a store. Cost += SpillPlacer->getBlockFrequency(Number); @@ -1578,9 +1575,9 @@ const BitVector &LiveBundles = Cand.LiveBundles; unsigned VirtRegToSplit = SA->getParent().reg(); ArrayRef UseBlocks = SA->getUseBlocks(); - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; + for (unsigned I = 0; I != UseBlocks.size(); ++I) { + const SplitAnalysis::BlockInfo &BI = UseBlocks[I]; + SpillPlacement::BlockConstraint &BC = SplitConstraints[I]; bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, false)]; bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, true)]; unsigned Ins = 0; @@ -1618,8 +1615,7 @@ GlobalCost += SpillPlacer->getBlockFrequency(BC.Number); } - for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { - unsigned Number = Cand.ActiveBlocks[i]; + for (unsigned Number : Cand.ActiveBlocks) { bool RegIn = LiveBundles[Bundles->getBundle(Number, false)]; bool RegOut = LiveBundles[Bundles->getBundle(Number, true)]; if (!RegIn && !RegOut) @@ -1682,8 +1678,7 @@ // First handle all the blocks with uses. ArrayRef UseBlocks = SA->getUseBlocks(); - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; + for (const SplitAnalysis::BlockInfo &BI : UseBlocks) { unsigned Number = BI.MBB->getNumber(); unsigned IntvIn = 0, IntvOut = 0; SlotIndex IntfIn, IntfOut; @@ -1728,8 +1723,7 @@ BitVector Todo = SA->getThroughBlocks(); for (unsigned c = 0; c != UsedCands.size(); ++c) { ArrayRef Blocks = GlobalCand[UsedCands[c]].ActiveBlocks; - for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { - unsigned Number = Blocks[i]; + for (unsigned Number : Blocks) { if (!Todo.test(Number)) continue; Todo.reset(Number); @@ -1772,8 +1766,8 @@ // - Candidate intervals can be assigned to Cand.PhysReg. // - Block-local splits are candidates for local splitting. // - DCE leftovers should go back on the queue. - for (unsigned i = 0, e = LREdit.size(); i != e; ++i) { - LiveInterval &Reg = LIS->getInterval(LREdit.get(i)); + for (unsigned I = 0, E = LREdit.size(); I != E; ++I) { + LiveInterval &Reg = LIS->getInterval(LREdit.get(I)); // Ignore old intervals from DCE. if (getStage(Reg) != RS_New) @@ -1781,14 +1775,14 @@ // Remainder interval. Don't try splitting again, spill if it doesn't // allocate. - if (IntvMap[i] == 0) { + if (IntvMap[I] == 0) { setStage(Reg, RS_Spill); continue; } // Global intervals. Allow repeated splitting as long as the number of live // blocks is strictly decreasing. - if (IntvMap[i] < NumGlobalIntvs) { + if (IntvMap[I] < NumGlobalIntvs) { if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { LLVM_DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks << " blocks as original.\n"); @@ -1865,12 +1859,12 @@ if (NumCands == IntfCache.getMaxCursors()) { unsigned WorstCount = ~0u; unsigned Worst = 0; - for (unsigned i = 0; i != NumCands; ++i) { - if (i == BestCand || !GlobalCand[i].PhysReg) + for (unsigned CandIndex = 0; CandIndex != NumCands; ++CandIndex) { + if (CandIndex == BestCand || !GlobalCand[CandIndex].PhysReg) continue; - unsigned Count = GlobalCand[i].LiveBundles.count(); + unsigned Count = GlobalCand[CandIndex].LiveBundles.count(); if (Count < WorstCount) { - Worst = i; + Worst = CandIndex; WorstCount = Count; } } @@ -1921,8 +1915,8 @@ LLVM_DEBUG({ dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost) << " with bundles"; - for (int i : Cand.LiveBundles.set_bits()) - dbgs() << " EB#" << i; + for (int I : Cand.LiveBundles.set_bits()) + dbgs() << " EB#" << I; dbgs() << ".\n"; }); if (Cost < BestCost) { @@ -2004,8 +1998,7 @@ LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats); SE->reset(LREdit, SplitSpillMode); ArrayRef UseBlocks = SA->getUseBlocks(); - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; + for (const SplitAnalysis::BlockInfo &BI : UseBlocks) { if (SA->shouldSplitSingleBlock(BI, SingleInstrs)) SE->splitSingleBlock(BI); } @@ -2024,9 +2017,9 @@ // Sort out the new intervals created by splitting. The remainder interval // goes straight to spilling, the new local ranges get to stay RS_New. - for (unsigned i = 0, e = LREdit.size(); i != e; ++i) { - LiveInterval &LI = LIS->getInterval(LREdit.get(i)); - if (getStage(LI) == RS_New && IntvMap[i] == 0) + for (unsigned I = 0, E = LREdit.size(); I != E; ++I) { + LiveInterval &LI = LIS->getInterval(LREdit.get(I)); + if (getStage(LI) == RS_New && IntvMap[I] == 0) setStage(LI, RS_Spill); } @@ -2089,18 +2082,18 @@ // the constraints on the virtual register. // Otherwise, splitting just inserts uncoalescable copies that do not help // the allocation. - for (unsigned i = 0; i != Uses.size(); ++i) { - if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i])) + for (const auto &Use : Uses) { + if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Use)) if (MI->isFullCopy() || SuperRCNumAllocatableRegs == getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC, TII, TRI, RCI)) { - LLVM_DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI); + LLVM_DEBUG(dbgs() << " skip:\t" << Use << '\t' << *MI); continue; } SE->openIntv(); - SlotIndex SegStart = SE->enterIntvBefore(Uses[i]); - SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]); + SlotIndex SegStart = SE->enterIntvBefore(Use); + SlotIndex SegStop = SE->leaveIntvAfter(Use); SE->useIntv(SegStart, SegStop); } @@ -2126,7 +2119,7 @@ /// calcGapWeights - Compute the maximum spill weight that needs to be evicted /// in order to use PhysReg between two entries in SA->UseSlots. /// -/// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1]. +/// GapWeight[I] represents the gap between UseSlots[I] and UseSlots[I + 1]. /// void RAGreedy::calcGapWeights(unsigned PhysReg, SmallVectorImpl &GapWeight) { @@ -2229,8 +2222,8 @@ LLVM_DEBUG({ dbgs() << "tryLocalSplit: "; - for (unsigned i = 0, e = Uses.size(); i != e; ++i) - dbgs() << ' ' << Uses[i]; + for (const auto &Use : Uses) + dbgs() << ' ' << Use; dbgs() << '\n'; }); @@ -2242,25 +2235,25 @@ ArrayRef RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber()); LLVM_DEBUG(dbgs() << RMS.size() << " regmasks in block:"); // Constrain to VirtReg's live range. - unsigned ri = + unsigned RI = llvm::lower_bound(RMS, Uses.front().getRegSlot()) - RMS.begin(); - unsigned re = RMS.size(); - for (unsigned i = 0; i != NumGaps && ri != re; ++i) { - // Look for Uses[i] <= RMS <= Uses[i+1]. - assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i])); - if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri])) + unsigned RE = RMS.size(); + for (unsigned I = 0; I != NumGaps && RI != RE; ++I) { + // Look for Uses[I] <= RMS <= Uses[I + 1]. + assert(!SlotIndex::isEarlierInstr(RMS[RI], Uses[I])); + if (SlotIndex::isEarlierInstr(Uses[I + 1], RMS[RI])) continue; // Skip a regmask on the same instruction as the last use. It doesn't // overlap the live range. - if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps) + if (SlotIndex::isSameInstr(Uses[I + 1], RMS[RI]) && I + 1 == NumGaps) break; - LLVM_DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' - << Uses[i + 1]); - RegMaskGaps.push_back(i); + LLVM_DEBUG(dbgs() << ' ' << RMS[RI] << ':' << Uses[I] << '-' + << Uses[I + 1]); + RegMaskGaps.push_back(I); // Advance ri to the next gap. A regmask on one of the uses counts in // both gaps. - while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1])) - ++ri; + while (RI != RE && SlotIndex::isEarlierInstr(RMS[RI], Uses[I + 1])) + ++RI; } LLVM_DEBUG(dbgs() << '\n'); } @@ -2298,13 +2291,13 @@ Order.rewind(); while (unsigned PhysReg = Order.next()) { // Keep track of the largest spill weight that would need to be evicted in - // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1]. + // order to make use of PhysReg between UseSlots[I] and UseSlots[I + 1]. calcGapWeights(PhysReg, GapWeight); // Remove any gaps with regmask clobbers. if (Matrix->checkRegMaskInterference(VirtReg, PhysReg)) - for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i) - GapWeight[RegMaskGaps[i]] = huge_valf; + for (unsigned I = 0, E = RegMaskGaps.size(); I != E; ++I) + GapWeight[RegMaskGaps[I]] = huge_valf; // Try to find the best sequence of gaps to close. // The new spill weight must be larger than any gap interference. @@ -2322,7 +2315,7 @@ const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore] - << '-' << Uses[SplitAfter] << " i=" << MaxGap); + << '-' << Uses[SplitAfter] << " I=" << MaxGap); // Stop before the interval gets so big we wouldn't be making progress. if (!LiveBefore && !LiveAfter) { @@ -2371,8 +2364,8 @@ // Recompute the max when necessary. if (GapWeight[SplitBefore - 1] >= MaxGap) { MaxGap = GapWeight[SplitBefore]; - for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i) - MaxGap = std::max(MaxGap, GapWeight[i]); + for (unsigned I = SplitBefore + 1; I != SplitAfter; ++I) + MaxGap = std::max(MaxGap, GapWeight[I]); } continue; } @@ -2418,10 +2411,10 @@ if (NewGaps >= NumGaps) { LLVM_DEBUG(dbgs() << "Tagging non-progress ranges: "); assert(!ProgressRequired && "Didn't make progress when it was required."); - for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) - if (IntvMap[i] == 1) { - setStage(LIS->getInterval(LREdit.get(i)), RS_Split2); - LLVM_DEBUG(dbgs() << printReg(LREdit.get(i))); + for (unsigned I = 0, E = IntvMap.size(); I != E; ++I) + if (IntvMap[I] == 1) { + setStage(LIS->getInterval(LREdit.get(I)), RS_Split2); + LLVM_DEBUG(dbgs() << printReg(LREdit.get(I))); } LLVM_DEBUG(dbgs() << '\n'); }