diff --git a/compiler-rt/lib/xray/xray_mips.cpp b/compiler-rt/lib/xray/xray_mips.cpp --- a/compiler-rt/lib/xray/xray_mips.cpp +++ b/compiler-rt/lib/xray/xray_mips.cpp @@ -93,6 +93,7 @@ // When |Enable|==false, we set back the first instruction in the sled to be // B #44 + uint32_t *Address = reinterpret_cast(Sled.address()); if (Enable) { uint32_t LoTracingHookAddr = reinterpret_cast(TracingHook) & 0xffff; @@ -100,34 +101,34 @@ (reinterpret_cast(TracingHook) >> 16) & 0xffff; uint32_t LoFunctionID = FuncId & 0xffff; uint32_t HiFunctionID = (FuncId >> 16) & 0xffff; - *reinterpret_cast(Sled.Address + 8) = encodeInstruction( - PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_RA, 0x4); - *reinterpret_cast(Sled.Address + 12) = encodeInstruction( - PatchOpcodes::PO_SW, RegNum::RN_SP, RegNum::RN_T9, 0x0); - *reinterpret_cast(Sled.Address + 16) = encodeInstruction( - PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HiTracingHookAddr); - *reinterpret_cast(Sled.Address + 20) = encodeInstruction( - PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr); - *reinterpret_cast(Sled.Address + 24) = encodeInstruction( - PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID); - *reinterpret_cast(Sled.Address + 28) = encodeSpecialInstruction( - PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0); - *reinterpret_cast(Sled.Address + 32) = encodeInstruction( - PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID); - *reinterpret_cast(Sled.Address + 36) = encodeInstruction( - PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_T9, 0x0); - *reinterpret_cast(Sled.Address + 40) = encodeInstruction( - PatchOpcodes::PO_LW, RegNum::RN_SP, RegNum::RN_RA, 0x4); - *reinterpret_cast(Sled.Address + 44) = encodeInstruction( - PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0x8); + Address[2] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, + RegNum::RN_RA, 0x4); + Address[3] = encodeInstruction(PatchOpcodes::PO_SW, RegNum::RN_SP, + RegNum::RN_T9, 0x0); + Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, + HiTracingHookAddr); + Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, + RegNum::RN_T9, LoTracingHookAddr); + Address[6] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, + HiFunctionID); + Address[7] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9, + 0x0, RegNum::RN_RA, 0X0); + Address[8] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T0, + RegNum::RN_T0, LoFunctionID); + Address[9] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP, + RegNum::RN_T9, 0x0); + Address[10] = encodeInstruction(PatchOpcodes::PO_LW, RegNum::RN_SP, + RegNum::RN_RA, 0x4); + Address[11] = encodeInstruction(PatchOpcodes::PO_ADDIU, RegNum::RN_SP, + RegNum::RN_SP, 0x8); uint32_t CreateStackSpaceInstr = encodeInstruction( PatchOpcodes::PO_ADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xFFF8); std::atomic_store_explicit( - reinterpret_cast *>(Sled.Address), + reinterpret_cast *>(Address), uint32_t(CreateStackSpaceInstr), std::memory_order_release); } else { std::atomic_store_explicit( - reinterpret_cast *>(Sled.Address), + reinterpret_cast *>(Address), uint32_t(PatchOpcodes::PO_B44), std::memory_order_release); } return true; diff --git a/compiler-rt/lib/xray/xray_mips64.cpp b/compiler-rt/lib/xray/xray_mips64.cpp --- a/compiler-rt/lib/xray/xray_mips64.cpp +++ b/compiler-rt/lib/xray/xray_mips64.cpp @@ -89,6 +89,7 @@ // When |Enable|==false, we set back the first instruction in the sled to be // B #60 + uint32_t *Address = reinterpret_cast(Sled.address()); if (Enable) { uint32_t LoTracingHookAddr = reinterpret_cast(TracingHook) & 0xffff; @@ -100,43 +101,42 @@ (reinterpret_cast(TracingHook) >> 48) & 0xffff; uint32_t LoFunctionID = FuncId & 0xffff; uint32_t HiFunctionID = (FuncId >> 16) & 0xffff; - *reinterpret_cast(Sled.Address + 8) = encodeInstruction( - PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_RA, 0x8); - *reinterpret_cast(Sled.Address + 12) = encodeInstruction( - PatchOpcodes::PO_SD, RegNum::RN_SP, RegNum::RN_T9, 0x0); - *reinterpret_cast(Sled.Address + 16) = encodeInstruction( - PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, HighestTracingHookAddr); - *reinterpret_cast(Sled.Address + 20) = - encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, - HigherTracingHookAddr); - *reinterpret_cast(Sled.Address + 24) = encodeSpecialInstruction( - PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10); - *reinterpret_cast(Sled.Address + 28) = encodeInstruction( - PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, HiTracingHookAddr); - *reinterpret_cast(Sled.Address + 32) = encodeSpecialInstruction( - PatchOpcodes::PO_DSLL, 0x0, RegNum::RN_T9, RegNum::RN_T9, 0x10); - *reinterpret_cast(Sled.Address + 36) = encodeInstruction( - PatchOpcodes::PO_ORI, RegNum::RN_T9, RegNum::RN_T9, LoTracingHookAddr); - *reinterpret_cast(Sled.Address + 40) = encodeInstruction( - PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, HiFunctionID); - *reinterpret_cast(Sled.Address + 44) = encodeSpecialInstruction( - PatchOpcodes::PO_JALR, RegNum::RN_T9, 0x0, RegNum::RN_RA, 0X0); - *reinterpret_cast(Sled.Address + 48) = encodeInstruction( - PatchOpcodes::PO_ORI, RegNum::RN_T0, RegNum::RN_T0, LoFunctionID); - *reinterpret_cast(Sled.Address + 52) = encodeInstruction( - PatchOpcodes::PO_LD, RegNum::RN_SP, RegNum::RN_T9, 0x0); - *reinterpret_cast(Sled.Address + 56) = encodeInstruction( - PatchOpcodes::PO_LD, RegNum::RN_SP, RegNum::RN_RA, 0x8); - *reinterpret_cast(Sled.Address + 60) = encodeInstruction( - PatchOpcodes::PO_DADDIU, RegNum::RN_SP, RegNum::RN_SP, 0x10); + Address[2] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, + RegNum::RN_RA, 0x8); + Address[3] = encodeInstruction(PatchOpcodes::PO_SD, RegNum::RN_SP, + RegNum::RN_T9, 0x0); + Address[4] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T9, + HighestTracingHookAddr); + Address[5] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, + RegNum::RN_T9, HigherTracingHookAddr); + Address[6] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0, + RegNum::RN_T9, RegNum::RN_T9, 0x10); + Address[7] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, + RegNum::RN_T9, HiTracingHookAddr); + Address[8] = encodeSpecialInstruction(PatchOpcodes::PO_DSLL, 0x0, + RegNum::RN_T9, RegNum::RN_T9, 0x10); + Address[9] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T9, + RegNum::RN_T9, LoTracingHookAddr); + Address[10] = encodeInstruction(PatchOpcodes::PO_LUI, 0x0, RegNum::RN_T0, + HiFunctionID); + Address[11] = encodeSpecialInstruction(PatchOpcodes::PO_JALR, RegNum::RN_T9, + 0x0, RegNum::RN_RA, 0X0); + Address[12] = encodeInstruction(PatchOpcodes::PO_ORI, RegNum::RN_T0, + RegNum::RN_T0, LoFunctionID); + Address[13] = encodeInstruction(PatchOpcodes::PO_LD, RegNum::RN_SP, + RegNum::RN_T9, 0x0); + Address[14] = encodeInstruction(PatchOpcodes::PO_LD, RegNum::RN_SP, + RegNum::RN_RA, 0x8); + Address[15] = encodeInstruction(PatchOpcodes::PO_DADDIU, RegNum::RN_SP, + RegNum::RN_SP, 0x10); uint32_t CreateStackSpace = encodeInstruction( PatchOpcodes::PO_DADDIU, RegNum::RN_SP, RegNum::RN_SP, 0xfff0); std::atomic_store_explicit( - reinterpret_cast *>(Sled.Address), - CreateStackSpace, std::memory_order_release); + reinterpret_cast *>(Address), CreateStackSpace, + std::memory_order_release); } else { std::atomic_store_explicit( - reinterpret_cast *>(Sled.Address), + reinterpret_cast *>(Address), uint32_t(PatchOpcodes::PO_B60), std::memory_order_release); } return true; diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -3253,14 +3253,10 @@ MCSection *InstMap = nullptr; MCSection *FnSledIndex = nullptr; const Triple &TT = TM.getTargetTriple(); - // Use PC-relative addresses on all targets except MIPS (MIPS64 cannot use - // PC-relative addresses because R_MIPS_PC64 does not exist). - bool PCRel = !TT.isMIPS(); + // Use PC-relative addresses on all targets. if (TT.isOSBinFormatELF()) { auto LinkedToSym = cast(CurrentFnSym); auto Flags = ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER; - if (!PCRel) - Flags |= ELF::SHF_WRITE; StringRef GroupName; if (F.hasComdat()) { Flags |= ELF::SHF_GROUP; @@ -3294,25 +3290,20 @@ OutStreamer->SwitchSection(InstMap); OutStreamer->emitLabel(SledsStart); for (const auto &Sled : Sleds) { - if (PCRel) { - MCSymbol *Dot = Ctx.createTempSymbol(); - OutStreamer->emitLabel(Dot); - OutStreamer->emitValueImpl( - MCBinaryExpr::createSub(MCSymbolRefExpr::create(Sled.Sled, Ctx), - MCSymbolRefExpr::create(Dot, Ctx), Ctx), - WordSizeBytes); - OutStreamer->emitValueImpl( - MCBinaryExpr::createSub( - MCSymbolRefExpr::create(CurrentFnBegin, Ctx), - MCBinaryExpr::createAdd( - MCSymbolRefExpr::create(Dot, Ctx), - MCConstantExpr::create(WordSizeBytes, Ctx), Ctx), - Ctx), - WordSizeBytes); - } else { - OutStreamer->emitSymbolValue(Sled.Sled, WordSizeBytes); - OutStreamer->emitSymbolValue(CurrentFnSym, WordSizeBytes); - } + MCSymbol *Dot = Ctx.createTempSymbol(); + OutStreamer->emitLabel(Dot); + OutStreamer->emitValueImpl( + MCBinaryExpr::createSub(MCSymbolRefExpr::create(Sled.Sled, Ctx), + MCSymbolRefExpr::create(Dot, Ctx), Ctx), + WordSizeBytes); + OutStreamer->emitValueImpl( + MCBinaryExpr::createSub( + MCSymbolRefExpr::create(CurrentFnBegin, Ctx), + MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Dot, Ctx), + MCConstantExpr::create(WordSizeBytes, Ctx), + Ctx), + Ctx), + WordSizeBytes); Sled.emit(WordSizeBytes, OutStreamer.get()); } MCSymbol *SledsEnd = OutContext.createTempSymbol("xray_sleds_end", true); diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -1233,7 +1233,7 @@ .addImm(0x34)); } - recordSled(CurSled, MI, Kind); + recordSled(CurSled, MI, Kind, 2); } void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) { diff --git a/llvm/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll b/llvm/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll --- a/llvm/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll +++ b/llvm/test/CodeGen/Mips/xray-mips-attribute-instrumentation.ll @@ -52,20 +52,22 @@ ; CHECK-MIPS32-LABEL: $tmp2: ; CHECK-MIPS32: addiu $25, $25, 52 } -; CHECK: .section xray_instr_map,{{.*}} -; CHECK-MIPS64: .8byte .Lxray_sled_0 -; CHECK-MIPS64: .8byte .Lxray_sled_1 -; CHECK-MIPS32: .4byte ($xray_sled_0) -; CHECK-MIPS32: .4byte ($xray_sled_1) +; CHECK: .section xray_instr_map,"ao",@progbits,foo +; CHECK-MIPS64: .Ltmp3: +; CHECK-MIPS64-NEXT: .8byte .Lxray_sled_0-.Ltmp3 +; CHECK-MIPS64-NEXT: .8byte .Lfunc_begin0-(.Ltmp3+8) +; CHECK-MIPS32: $tmp3: +; CHECK-MIPS32-NEXT: .4byte ($xray_sled_0)-($tmp3) +; CHECK-MIPS32-NEXT: .4byte ($func_begin0)-(($tmp3)+4) ; We test multiple returns in a single function to make sure we're getting all ; of them with XRay instrumentation. define i32 @bar(i32 %i) nounwind noinline uwtable "function-instrument"="xray-always" { ; CHECK: .p2align 2 ; CHECK-MIPS64-LABEL: .Lxray_sled_2: -; CHECK-MIPS64-NEXT: b .Ltmp4 +; CHECK-MIPS64-NEXT: b .Ltmp6 ; CHECK-MIPS32-LABEL: $xray_sled_2: -; CHECK-MIPS32-NEXT: b $tmp4 +; CHECK-MIPS32-NEXT: b $tmp6 ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop @@ -81,8 +83,8 @@ ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop -; CHECK-MIPS64-LABEL: .Ltmp4: -; CHECK-MIPS32-LABEL: $tmp4: +; CHECK-MIPS64-LABEL: .Ltmp6: +; CHECK-MIPS32-LABEL: $tmp6: ; CHECK-MIPS32: addiu $25, $25, 52 Test: %cond = icmp eq i32 %i, 0 @@ -91,9 +93,9 @@ ret i32 0 ; CHECK: .p2align 2 ; CHECK-MIPS64-LABEL: .Lxray_sled_3: -; CHECK-MIPS64-NEXT: b .Ltmp5 +; CHECK-MIPS64-NEXT: b .Ltmp7 ; CHECK-MIPS32-LABEL: $xray_sled_3: -; CHECK-MIPS32-NEXT: b $tmp5 +; CHECK-MIPS32-NEXT: b $tmp7 ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop @@ -109,16 +111,16 @@ ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop -; CHECK-MIPS64-LABEL: .Ltmp5: -; CHECK-MIPS32-LABEL: $tmp5: +; CHECK-MIPS64-LABEL: .Ltmp7: +; CHECK-MIPS32-LABEL: $tmp7: ; CHECK-MIPS32: addiu $25, $25, 52 NotEqual: ret i32 1 ; CHECK: .p2align 2 ; CHECK-MIPS64-LABEL: .Lxray_sled_4: -; CHECK-MIPS64-NEXT: b .Ltmp6 +; CHECK-MIPS64-NEXT: b .Ltmp8 ; CHECK-MIPS32-LABEL: $xray_sled_4: -; CHECK-MIPS32-NEXT: b $tmp6 +; CHECK-MIPS32-NEXT: b $tmp8 ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop @@ -134,14 +136,14 @@ ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop ; CHECK-MIPS64: nop -; CHECK-MIPS64-LABEL: .Ltmp6: -; CHECK-MIPS32-LABEL: $tmp6: +; CHECK-MIPS64-LABEL: .Ltmp8: +; CHECK-MIPS32-LABEL: $tmp8: ; CHECK-MIPS32: addiu $25, $25, 52 } ; CHECK: .section xray_instr_map,{{.*}} ; CHECK-MIPS64: .8byte .Lxray_sled_2 ; CHECK-MIPS64: .8byte .Lxray_sled_3 ; CHECK-MIPS64: .8byte .Lxray_sled_4 -; CHECK-MIPS32: .4byte ($xray_sled_2) -; CHECK-MIPS32: .4byte ($xray_sled_3) -; CHECK-MIPS32: .4byte ($xray_sled_4) +; CHECK-MIPS32: .4byte ($xray_sled_2)-($tmp9) +; CHECK-MIPS32: .4byte ($xray_sled_3)-($tmp10) +; CHECK-MIPS32: .4byte ($xray_sled_4)-($tmp11) diff --git a/llvm/test/CodeGen/Mips/xray-section-group.ll b/llvm/test/CodeGen/Mips/xray-section-group.ll --- a/llvm/test/CodeGen/Mips/xray-section-group.ll +++ b/llvm/test/CodeGen/Mips/xray-section-group.ll @@ -14,7 +14,7 @@ define i32 @foo() nounwind noinline uwtable "function-instrument"="xray-always" { ; CHECK: .section .text.foo,"ax",@progbits ret i32 0 -; CHECK: .section xray_instr_map,"awo",@progbits,foo{{$}} +; CHECK: .section xray_instr_map,"ao",@progbits,foo{{$}} } ; CHECK-OBJ: Section { @@ -24,7 +24,7 @@ define i32 @bar() nounwind noinline uwtable "function-instrument"="xray-always" comdat($bar) { ; CHECK: .section .text.bar,"axG",@progbits,bar,comdat ret i32 1 -; CHECK: .section xray_instr_map,"aGwo",@progbits,bar,comdat,bar{{$}} +; CHECK: .section xray_instr_map,"aGo",@progbits,bar,comdat,bar{{$}} } ; CHECK-OBJ: Section {