diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -234,7 +234,7 @@
   virtual void leaveMBB() {};
 
   /// Notify this strategy that all roots have been released (including those
-  /// that depend on EntrySU or ExitSU).
+  /// that depend on ExitSU).
   virtual void registerRoots() {}
 
   /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -560,7 +560,6 @@
     MachineFunction &MF;                ///< Machine function
     MachineRegisterInfo &MRI;           ///< Virtual/real register map
     std::vector<SUnit> SUnits;          ///< The scheduling units.
-    SUnit EntrySU;                      ///< Special node for the region entry.
     SUnit ExitSU;                       ///< Special node for the region exit.
 
 #ifdef NDEBUG
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -680,7 +680,7 @@
     PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
 
   --PredSU->NumSuccsLeft;
-  if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
+  if (PredSU->NumSuccsLeft == 0)
     SchedImpl->releaseBottomNode(PredSU);
 }
 
@@ -853,7 +853,7 @@
   NextClusterSucc = nullptr;
   NextClusterPred = nullptr;
 
-  // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
+  // Release all DAG roots for scheduling, not including ExitSU.
   //
   // Nodes with unreleased weak edges can still be roots.
   // Release top roots in forward order.
@@ -867,7 +867,6 @@
     SchedImpl->releaseBottomNode(*I);
   }
 
-  releaseSuccessors(&EntrySU);
   releasePredecessors(&ExitSU);
 
   SchedImpl->registerRoots();
@@ -1168,8 +1167,6 @@
 
 void ScheduleDAGMILive::dump() const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  if (EntrySU.getInstr() != nullptr)
-    dumpNodeAll(EntrySU);
   for (const SUnit &SU : SUnits) {
     dumpNodeAll(SU);
     if (ShouldTrackPressure) {
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -109,23 +109,21 @@
 
   // Make the FirstSU also dependent on the dependencies of the SecondSU to
   // prevent them from being scheduled between the FirstSU and the SecondSU.
-  if (&FirstSU != &DAG.EntrySU) {
-    for (const SDep &SI : SecondSU.Preds) {
-      SUnit *SU = SI.getSUnit();
-      if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
-        continue;
-      LLVM_DEBUG(dbgs() << "  Bind "; DAG.dumpNodeName(*SU); dbgs() << " - ";
-                 DAG.dumpNodeName(FirstSU); dbgs() << '\n';);
-      DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
-    }
-    // ExitSU comes last by design, which acts like an implicit dependency
-    // between ExitSU and any bottom root in the graph. We should transfer
-    // this to FirstSU as well.
-    if (&SecondSU == &DAG.ExitSU) {
-      for (SUnit &SU : DAG.SUnits) {
-        if (SU.Succs.empty())
-          DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
-      }
+  for (const SDep &SI : SecondSU.Preds) {
+    SUnit *SU = SI.getSUnit();
+    if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
+      continue;
+    LLVM_DEBUG(dbgs() << "  Bind "; DAG.dumpNodeName(*SU); dbgs() << " - ";
+               DAG.dumpNodeName(FirstSU); dbgs() << '\n';);
+    DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
+  }
+  // ExitSU comes last by design, which acts like an implicit dependency
+  // between ExitSU and any bottom root in the graph. We should transfer
+  // this to FirstSU as well.
+  if (&SecondSU == &DAG.ExitSU) {
+    for (SUnit &SU : DAG.SUnits) {
+      if (SU.Succs.empty())
+        DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
     }
   }
 
diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp
--- a/llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -527,9 +527,6 @@
   // blocks are a single region).
   HazardRec->Reset();
 
-  // Release any successors of the special Entry node.
-  ReleaseSuccessors(&EntrySU);
-
   // Add all leaves to Available queue.
   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     // It is available if it has no predecessors.
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -63,7 +63,6 @@
 
 void ScheduleDAG::clearDAG() {
   SUnits.clear();
-  EntrySU = SUnit();
   ExitSU = SUnit();
 }
 
@@ -352,9 +351,7 @@
 }
 
 LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const {
-  if (&SU == &EntrySU)
-    dbgs() << "EntrySU";
-  else if (&SU == &ExitSU)
+  if (&SU == &ExitSU)
     dbgs() << "ExitSU";
   else
     dbgs() << "SU(" << SU.NodeNum << ")";
@@ -656,7 +653,7 @@
     for (int I = SU->Preds.size()-1; I >= 0; --I) {
       const SUnit *Pred = SU->Preds[I].getSUnit();
       unsigned s = Pred->NodeNum;
-      // Edges to non-SUnits are allowed but ignored (e.g. EntrySU).
+      // Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
       if (Pred->isBoundaryNode())
         continue;
       if (Node2Index[s] == LowerBound) {
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -1167,8 +1167,6 @@
 
 void ScheduleDAGInstrs::dump() const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  if (EntrySU.getInstr() != nullptr)
-    dumpNodeAll(EntrySU);
   for (const SUnit &SU : SUnits)
     dumpNodeAll(SU);
   if (ExitSU.getInstr() != nullptr)
@@ -1179,9 +1177,7 @@
 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
   std::string s;
   raw_string_ostream oss(s);
-  if (SU == &EntrySU)
-    oss << "<entry>";
-  else if (SU == &ExitSU)
+  if (SU == &ExitSU)
     oss << "<exit>";
   else
     SU->getInstr()->print(oss, /*SkipOpers=*/true);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -150,8 +150,8 @@
   --PredSU->NumSuccsLeft;
 
   // If all the node's successors are scheduled, this node is ready
-  // to be scheduled. Ignore the special EntrySU node.
-  if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
+  // to be scheduled.
+  if (PredSU->NumSuccsLeft == 0) {
     PredSU->isAvailable = true;
     AvailableQueue.push(PredSU);
   }
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -415,8 +415,8 @@
   }
 
   // If all the node's successors are scheduled, this node is ready
-  // to be scheduled. Ignore the special EntrySU node.
-  if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
+  // to be scheduled.
+  if (PredSU->NumSuccsLeft == 0) {
     PredSU->isAvailable = true;
 
     unsigned Height = PredSU->getHeight();
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -696,8 +696,6 @@
 
 void ScheduleDAGSDNodes::dump() const {
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
-  if (EntrySU.getNode() != nullptr)
-    dumpNodeAll(EntrySU);
   for (const SUnit &SU : SUnits)
     dumpNodeAll(SU);
   if (ExitSU.getNode() != nullptr)
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp
@@ -166,9 +166,6 @@
 void ScheduleDAGVLIW::listScheduleTopDown() {
   unsigned CurCycle = 0;
 
-  // Release any successors of the special Entry node.
-  releaseSuccessors(&EntrySU);
-
   // All leaves to AvailableQueue.
   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     // It is available if it has no predecessors.
diff --git a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
--- a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
@@ -248,7 +248,6 @@
   for (auto SU : TopRoots) {
     RQ.push_back(*new (Alloc.Allocate()) Candidate(SU, StepNo));
   }
-  releaseSuccessors(&DAG.EntrySU, StepNo);
 
   while (!RQ.empty()) {
     LLVM_DEBUG(dbgs() << "\n=== Picking candidate, Step = " << StepNo
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
@@ -455,7 +455,6 @@
   MachineRegisterInfo *getMRI() { return &MRI; }
   const TargetRegisterInfo *getTRI() { return TRI; }
   ScheduleDAGTopologicalSort *GetTopo() { return &Topo; }
-  SUnit& getEntrySU() { return EntrySU; }
   SUnit& getExitSU() { return ExitSU; }
 
   void restoreSULinksLeft();