diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -224,6 +224,8 @@ SMAXV, UMAXV, + SADDV_PRED, + UADDV_PRED, SMAXV_PRED, UMAXV_PRED, SMINV_PRED, diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -116,6 +116,27 @@ /// Value type used for condition codes. static const MVT MVT_CC = MVT::i32; +static inline EVT getPackedSVEVectorVT(EVT VT) { + switch (VT.getSimpleVT().SimpleTy) { + default: + llvm_unreachable("unexpected element type for vector"); + case MVT::i8: + return MVT::nxv16i8; + case MVT::i16: + return MVT::nxv8i16; + case MVT::i32: + return MVT::nxv4i32; + case MVT::i64: + return MVT::nxv2i64; + case MVT::f16: + return MVT::nxv8f16; + case MVT::f32: + return MVT::nxv4f32; + case MVT::f64: + return MVT::nxv2f64; + } +} + /// Returns true if VT's elements occupy the lowest bit positions of its /// associated register class without any intervening space. /// @@ -1581,6 +1602,8 @@ MAKE_CASE(AArch64ISD::UMINV) MAKE_CASE(AArch64ISD::SMAXV) MAKE_CASE(AArch64ISD::UMAXV) + MAKE_CASE(AArch64ISD::SADDV_PRED) + MAKE_CASE(AArch64ISD::UADDV_PRED) MAKE_CASE(AArch64ISD::SMAXV_PRED) MAKE_CASE(AArch64ISD::UMAXV_PRED) MAKE_CASE(AArch64ISD::SMINV_PRED) @@ -12158,34 +12181,6 @@ DAG.getConstant(0, dl, MVT::i64)); } -static SDValue LowerSVEIntReduction(SDNode *N, unsigned Opc, - SelectionDAG &DAG) { - SDLoc dl(N); - LLVMContext &Ctx = *DAG.getContext(); - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - - EVT VT = N->getValueType(0); - SDValue Pred = N->getOperand(1); - SDValue Data = N->getOperand(2); - EVT DataVT = Data.getValueType(); - - if (DataVT.getVectorElementType().isScalarInteger() && - (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)) { - if (!TLI.isTypeLegal(DataVT)) - return SDValue(); - - EVT OutputVT = EVT::getVectorVT(Ctx, VT, - AArch64::NeonBitsPerVector / VT.getSizeInBits()); - SDValue Reduce = DAG.getNode(Opc, dl, OutputVT, Pred, Data); - SDValue Zero = DAG.getConstant(0, dl, MVT::i64); - SDValue Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Reduce, Zero); - - return Result; - } - - return SDValue(); -} - static SDValue LowerSVEIntrinsicIndex(SDNode *N, SelectionDAG &DAG) { SDLoc DL(N); SDValue Op1 = N->getOperand(1); @@ -12329,6 +12324,25 @@ return DAG.getZExtOrTrunc(Res, DL, VT); } +static SDValue combineSVEReductionInt(SDNode *N, unsigned Opc, + SelectionDAG &DAG) { + SDLoc DL(N); + + SDValue Pred = N->getOperand(1); + SDValue VecToReduce = N->getOperand(2); + + // NOTE: The integer reduction's result type is not always linked to the + // operand's element type so we construct it from the intrinsic's result type. + EVT ReduceVT = getPackedSVEVectorVT(N->getValueType(0)); + SDValue Reduce = DAG.getNode(Opc, DL, ReduceVT, Pred, VecToReduce); + + // SVE reductions set the whole vector register with the first element + // containing the reduction result, which we'll now extract. + SDValue Zero = DAG.getConstant(0, DL, MVT::i64); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, N->getValueType(0), Reduce, + Zero); +} + static SDValue combineSVEReductionFP(SDNode *N, unsigned Opc, SelectionDAG &DAG) { SDLoc DL(N); @@ -12442,20 +12456,28 @@ case Intrinsic::aarch64_crc32h: case Intrinsic::aarch64_crc32ch: return tryCombineCRC32(0xffff, N, DAG); + case Intrinsic::aarch64_sve_saddv: + // There is no i64 version of SADDV because the sign is irrelevant. + if (N->getOperand(2)->getValueType(0).getVectorElementType() == MVT::i64) + return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); + else + return combineSVEReductionInt(N, AArch64ISD::SADDV_PRED, DAG); + case Intrinsic::aarch64_sve_uaddv: + return combineSVEReductionInt(N, AArch64ISD::UADDV_PRED, DAG); case Intrinsic::aarch64_sve_smaxv: - return LowerSVEIntReduction(N, AArch64ISD::SMAXV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::SMAXV_PRED, DAG); case Intrinsic::aarch64_sve_umaxv: - return LowerSVEIntReduction(N, AArch64ISD::UMAXV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::UMAXV_PRED, DAG); case Intrinsic::aarch64_sve_sminv: - return LowerSVEIntReduction(N, AArch64ISD::SMINV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::SMINV_PRED, DAG); case Intrinsic::aarch64_sve_uminv: - return LowerSVEIntReduction(N, AArch64ISD::UMINV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::UMINV_PRED, DAG); case Intrinsic::aarch64_sve_orv: - return LowerSVEIntReduction(N, AArch64ISD::ORV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::ORV_PRED, DAG); case Intrinsic::aarch64_sve_eorv: - return LowerSVEIntReduction(N, AArch64ISD::EORV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::EORV_PRED, DAG); case Intrinsic::aarch64_sve_andv: - return LowerSVEIntReduction(N, AArch64ISD::ANDV_PRED, DAG); + return combineSVEReductionInt(N, AArch64ISD::ANDV_PRED, DAG); case Intrinsic::aarch64_sve_index: return LowerSVEIntrinsicIndex(N, DAG); case Intrinsic::aarch64_sve_dup: diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -152,6 +152,8 @@ def AArch64fmaxnmv_p : SDNode<"AArch64ISD::FMAXNMV_PRED", SDT_AArch64Reduce>; def AArch64fminv_p : SDNode<"AArch64ISD::FMINV_PRED", SDT_AArch64Reduce>; def AArch64fminnmv_p : SDNode<"AArch64ISD::FMINNMV_PRED", SDT_AArch64Reduce>; +def AArch64saddv_p : SDNode<"AArch64ISD::SADDV_PRED", SDT_AArch64Reduce>; +def AArch64uaddv_p : SDNode<"AArch64ISD::UADDV_PRED", SDT_AArch64Reduce>; def AArch64smaxv_p : SDNode<"AArch64ISD::SMAXV_PRED", SDT_AArch64Reduce>; def AArch64umaxv_p : SDNode<"AArch64ISD::UMAXV_PRED", SDT_AArch64Reduce>; def AArch64sminv_p : SDNode<"AArch64ISD::SMINV_PRED", SDT_AArch64Reduce>; @@ -299,8 +301,8 @@ defm MLS_ZPmZZ : sve_int_mlas_vvv_pred<0b1, "mls", int_aarch64_sve_mls, sub, AArch64mul_p_oneuse>; // SVE predicated integer reductions. - defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", int_aarch64_sve_saddv>; - defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv", int_aarch64_sve_uaddv, int_aarch64_sve_saddv>; + defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", AArch64saddv_p>; + defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv", AArch64uaddv_p>; defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv", AArch64smaxv_p>; defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv", AArch64umaxv_p>; defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv", AArch64sminv_p>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -348,11 +348,6 @@ : Pat<(vtd (op (pt (AArch64ptrue 31)), vt1:$Op1, vt2:$Op2)), (inst $Op1, $Op2)>; -class SVE_2_Op_Pat_Reduce_To_Neon -: Pat<(vtd (op vt1:$Op1, vt2:$Op2)), - (INSERT_SUBREG (vtd (IMPLICIT_DEF)), (inst $Op1, $Op2), sub)>; - class SVE_3_Op_Pat : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -4526,7 +4521,6 @@ def : SVE_2_Op_Pat(NAME # _D)>; } - //===----------------------------------------------------------------------===// // SVE Floating Point Accumulating Reduction Group //===----------------------------------------------------------------------===// @@ -7164,8 +7158,8 @@ //===----------------------------------------------------------------------===// class sve_int_reduce sz8_32, bits<2> fmt, bits<3> opc, string asm, - ZPRRegOp zprty, RegisterClass regtype> -: I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), + ZPRRegOp zprty, FPRasZPROperand dstOpType> +: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Vd, $Pg, $Zn", "", []>, Sched<[]> { @@ -7183,51 +7177,54 @@ let Inst{4-0} = Vd; } -multiclass sve_int_reduce_0_saddv opc, string asm, SDPatternOperator op> { - def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; - def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; - def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; - - def : SVE_2_Op_Pat(NAME # _B)>; - def : SVE_2_Op_Pat(NAME # _H)>; - def : SVE_2_Op_Pat(NAME # _S)>; -} - -multiclass sve_int_reduce_0_uaddv opc, string asm, SDPatternOperator op, SDPatternOperator opSaddv> { - def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>; - def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>; - def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>; - def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>; - - def : SVE_2_Op_Pat(NAME # _B)>; - def : SVE_2_Op_Pat(NAME # _H)>; - def : SVE_2_Op_Pat(NAME # _S)>; - def : SVE_2_Op_Pat(NAME # _D)>; - def : SVE_2_Op_Pat(NAME # _D)>; -} - -multiclass sve_int_reduce_1 opc, string asm, SDPatternOperator op> { - def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>; - def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>; - def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>; - def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>; +multiclass sve_int_reduce_0_saddv opc, string asm, + SDPatternOperator op> { + def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64asZPR>; + def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64asZPR>; + def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64asZPR>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _B), bsub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _H), hsub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _S), ssub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _D), dsub>; + def : SVE_2_Op_Pat(NAME # _B)>; + def : SVE_2_Op_Pat(NAME # _H)>; + def : SVE_2_Op_Pat(NAME # _S)>; } -multiclass sve_int_reduce_2 opc, string asm, SDPatternOperator op> { - def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>; - def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>; - def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>; - def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>; - - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _B), bsub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _H), hsub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _S), ssub>; - def : SVE_2_Op_Pat_Reduce_To_Neon(NAME # _D), dsub>; +multiclass sve_int_reduce_0_uaddv opc, string asm, + SDPatternOperator op> { + def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64asZPR>; + def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64asZPR>; + def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64asZPR>; + def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64asZPR>; + + def : SVE_2_Op_Pat(NAME # _B)>; + def : SVE_2_Op_Pat(NAME # _H)>; + def : SVE_2_Op_Pat(NAME # _S)>; + def : SVE_2_Op_Pat(NAME # _D)>; +} + +multiclass sve_int_reduce_1 opc, string asm, + SDPatternOperator op> { + def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8asZPR>; + def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16asZPR>; + def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32asZPR>; + def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64asZPR>; + + def : SVE_2_Op_Pat(NAME # _B)>; + def : SVE_2_Op_Pat(NAME # _H)>; + def : SVE_2_Op_Pat(NAME # _S)>; + def : SVE_2_Op_Pat(NAME # _D)>; +} + +multiclass sve_int_reduce_2 opc, string asm, + SDPatternOperator op> { + def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8asZPR>; + def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16asZPR>; + def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32asZPR>; + def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64asZPR>; + + def : SVE_2_Op_Pat(NAME # _B)>; + def : SVE_2_Op_Pat(NAME # _H)>; + def : SVE_2_Op_Pat(NAME # _S)>; + def : SVE_2_Op_Pat(NAME # _D)>; } class sve_int_movprfx_pred sz8_32, bits<3> opc, string asm,