diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3665,6 +3665,12 @@
   if (TM.getOptLevel() == CodeGenOpt::None || !TM.isPPC64())
     return false;
 
+  // For POWER10, it is more profitable to use the set boolean extension
+  // instructions rather than the integer compare elimination codegen.
+  // Users can override this via the command line option, `--ppc-gpr-icmps`.
+  if (!(CmpInGPR.getNumOccurrences() > 0) && Subtarget->isISA3_1())
+    return false;
+
   switch (N->getOpcode()) {
   default: break;
   case ISD::ZERO_EXTEND:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1080,6 +1080,7 @@
 def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
 def HasFPU : Predicate<"Subtarget->hasFPU()">;
 def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
+def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Multiclass Definitions.
@@ -3902,6 +3903,7 @@
 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
           (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
 
+let Predicates = [IsNotISA3_1] in {
 // Instantiations of CRNotPat for i32.
 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
                 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
@@ -3959,6 +3961,7 @@
                 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
                 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
+}
 
 multiclass FSetCCPat<SDNode SetCC, ValueType Ty, PatLeaf FCmp> {
   defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1355,6 +1355,113 @@
   def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
 }
 
+// Multiclass defining patterns for Set Boolean Extension Reverse Instructions.
+// This is analogous to the CRNotPat multiclass but specifically for Power10
+// and newer subtargets since the extended forms use Set Boolean instructions.
+// The first two anonymous patterns defined are actually a duplicate of those
+// in CRNotPat, but it is preferable to define both multiclasses as complete
+// ones rather than pulling that small common section out.
+multiclass P10ReverseSetBool<dag pattern, dag result> {
+  def : Pat<pattern, (crnot result)>;
+  def : Pat<(not pattern), result>;
+
+  def : Pat<(i32 (zext pattern)),
+            (SETBCR result)>;
+  def : Pat<(i64 (zext pattern)),
+            (SETBCR8 result)>;
+
+  def : Pat<(i32 (sext pattern)),
+            (SETNBCR result)>;
+  def : Pat<(i64 (sext pattern)),
+            (SETNBCR8 result)>;
+
+  def : Pat<(i32 (anyext pattern)),
+            (SETBCR result)>;
+  def : Pat<(i64 (anyext pattern)),
+            (SETBCR8 result)>;
+}
+
+multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, ImmLeaf ZExtTy,
+                               ImmLeaf SExtTy, PatLeaf Cmpi, PatLeaf Cmpli,
+                               PatLeaf Cmp, PatLeaf Cmpl> {
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
+                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
+                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
+                           (EXTRACT_SUBREG (Cmpl $s1, $s2), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
+                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
+                           (EXTRACT_SUBREG (Cmp $s1, $s2), sub_eq)>;
+
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
+                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
+                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
+                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
+                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETNE)),
+                           (EXTRACT_SUBREG (Cmpi $s1, imm:$imm), sub_eq)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETNE)),
+                           (EXTRACT_SUBREG (Cmpli $s1, imm:$imm), sub_eq)>;
+}
+
+multiclass FSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf FCmp> {
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>;
+  defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
+                           (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>;
+}
+
+let Predicates = [IsISA3_1] in {
+  def : Pat<(i32 (zext i1:$in)),
+            (SETBC $in)>;
+  def : Pat<(i64 (zext i1:$in)),
+            (SETBC8 $in)>;
+  def : Pat<(i32 (sext i1:$in)),
+            (SETNBC $in)>;
+  def : Pat<(i64 (sext i1:$in)),
+            (SETNBC8 $in)>;
+  def : Pat<(i32 (anyext i1:$in)),
+            (SETBC $in)>;
+  def : Pat<(i64 (anyext i1:$in)),
+            (SETBC8 $in)>;
+
+  // Instantiation of the set boolean reverse patterns for 32-bit integers.
+  defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
+                             CMPWI, CMPLWI, CMPW, CMPLW>;
+  defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
+                           (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
+                                           (LO16 imm:$imm)), sub_eq)>;
+
+  // Instantiation of the set boolean reverse patterns for 64-bit integers.
+  defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
+                             CMPDI, CMPLDI, CMPD, CMPLD>;
+  defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
+                           (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
+                                           (LO16 imm:$imm)), sub_eq)>;
+}
+
+// Instantiation of the set boolean reverse patterns for f32, f64, f128.
+let Predicates = [IsISA3_1, HasFPU] in {
+  defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
+  defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
+  defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
+}
+
 //---------------------------- Anonymous Patterns ----------------------------//
 let Predicates = [IsISA3_1] in {
   // Exploit the vector multiply high instructions using intrinsics.
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -827,6 +827,16 @@
     SpillsKnownBit = true;
     break;
   default:
+    // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
+    // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
+    // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
+    // register), and SETNBC will set this.
+    if (Subtarget.isISA3_1()) {
+      BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
+          .addReg(SrcReg, RegState::Undef);
+      break;
+    }
+
     // On Power9, we can use SETB to extract the LT bit. This only works for
     // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
     // of the bit we care about (32-bit sign bit) will be set to the value of
diff --git a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
--- a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
+++ b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
@@ -9,6 +9,12 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-P10
 @glob = local_unnamed_addr global i64 0, align 8
 @.str = private unnamed_addr constant [12 x i8] c"Value = %d\0A\00", align 1
 
@@ -42,6 +48,15 @@
 ; CHECK: ld r3, [[OFF]](r1)
 ; CHECK: xori r3, r3, 1
 ; CHECK: blr
+
+; CHECK-P10-LABEL: test
+; CHECK-P10: sub r3,
+; CHECK-P10: extsw r3,
+; CHECK-P10: bl call
+; CHECK-P10: cmpw r29, r30
+; CHECK-P10: #APP
+; CHECK-P10: setbcr r3, gt
+; CHECK-P10: blr
 }
 
 ; Function Attrs: nounwind
diff --git a/llvm/test/CodeGen/PowerPC/crbits.ll b/llvm/test/CodeGen/PowerPC/crbits.ll
--- a/llvm/test/CodeGen/PowerPC/crbits.ll
+++ b/llvm/test/CodeGen/PowerPC/crbits.ll
@@ -1,7 +1,8 @@
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
-target datalayout = "E-m:e-i64:64-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 -ppc-gpr-icmps=none < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-P10
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test1(float %v1, float %v2) #0 {
@@ -27,6 +28,18 @@
 ; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
+
+; CHECK-P10-LABEL: test1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    xxlxor f0, f0, f0
+; CHECK-P10-NEXT:    fcmpu cr1, f2, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    fcmpu cr0, f2, f0
+; CHECK-P10-NEXT:    crnor 4*cr5+gt, 4*cr1+un, gt
+; CHECK-P10-NEXT:    crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -47,6 +60,18 @@
 ; CHECK: creqv [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
 ; CHECK: blr
+
+; CHECK-P10-LABEL: test2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    xxlxor f0, f0, f0
+; CHECK-P10-NEXT:    fcmpu cr1, f2, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    fcmpu cr0, f2, f0
+; CHECK-P10-NEXT:    crnor 4*cr5+gt, 4*cr1+un, gt
+; CHECK-P10-NEXT:    crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -70,6 +95,20 @@
 ; CHECK: creqv [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
 ; CHECK: blr
+
+; CHECK-P10-LABEL: test3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    xxlxor f0, f0, f0
+; CHECK-P10-NEXT:    fcmpu cr1, f2, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    fcmpu cr0, f2, f0
+; CHECK-P10-NEXT:    crnor 4*cr5+gt, 4*cr1+un, gt
+; CHECK-P10-NEXT:    cmpwi r5, -2
+; CHECK-P10-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, eq
+; CHECK-P10-NEXT:    crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -103,6 +142,15 @@
 ; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1
 ; CHECK: or 3, [[TRUNC]], [[NE4]]
 ; CHECK-NEXT: blr
+
+; CHECK-P10-LABEL: test5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    and r3, r3, r4
+; CHECK-P10-NEXT:    cmpwi cr1, r5, -2
+; CHECK-P10-NEXT:    andi. r3, r3, 1
+; CHECK-P10-NEXT:    crorc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -124,6 +172,17 @@
 ; CHECK: or [[OR:[0-9]+]], [[NE4]], [[CLR1]]
 ; CHECK: and 3, [[OR]], [[CLR2]]
 ; CHECK-NEXT: blr
+
+; CHECK-P10-LABEL: test6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 1
+; CHECK-P10-NEXT:    cmpwi cr1, r5, -2
+; CHECK-P10-NEXT:    crmove 4*cr5+lt, gt
+; CHECK-P10-NEXT:    andi. r3, r4, 1
+; CHECK-P10-NEXT:    crorc 4*cr5+gt, gt, 4*cr1+eq
+; CHECK-P10-NEXT:    crand 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 ; Function Attrs: nounwind readnone
@@ -197,6 +256,14 @@
 ; CHECK: xori 3, 3, 1
 ; CHECK: and 3, 3, 4
 ; CHECK-NEXT: blr
+
+; CHECK-P10-LABEL: test10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    cmpwi cr1, r4, 0
+; CHECK-P10-NEXT:    crandc 4*cr5+lt, 4*cr1+eq, eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
 }
 
 attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setbc-ri.ll
@@ -0,0 +1,527 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setbc1(i8 %a) {
+; CHECK-P10-LABEL: setbc1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc2(i32 %a) {
+; CHECK-P10-LABEL: setbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc3(i64 %a) {
+; CHECK-P10-LABEL: setbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc4(i16 %a) {
+; CHECK-P10-LABEL: setbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc5(i8 %a) {
+; CHECK-P10-LABEL: setbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc6(i32 %a) {
+; CHECK-P10-LABEL: setbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc7(i64 %a) {
+; CHECK-P10-LABEL: setbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc8(i16 %a) {
+; CHECK-P10-LABEL: setbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setbc9(i8 %a) {
+; CHECK-P10-LABEL: setbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbc10(i32 %a) {
+; CHECK-P10-LABEL: setbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setbc11(i64 %a) {
+; CHECK-P10-LABEL: setbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setbc12(i16 %a) {
+; CHECK-P10-LABEL: setbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setbc13(i8 %a) {
+; CHECK-P10-LABEL: setbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc14(i32 %a) {
+; CHECK-P10-LABEL: setbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc15(i64 %a) {
+; CHECK-P10-LABEL: setbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc16(i16 %a) {
+; CHECK-P10-LABEL: setbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc17(i8 %a) {
+; CHECK-P10-LABEL: setbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc18(i32 %a) {
+; CHECK-P10-LABEL: setbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc19(i64 %a) {
+; CHECK-P10-LABEL: setbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc20(i16 %a) {
+; CHECK-P10-LABEL: setbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setbc21(i8 %a) {
+; CHECK-P10-LABEL: setbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbc22(i32 %a) {
+; CHECK-P10-LABEL: setbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setbc23(i64 %a) {
+; CHECK-P10-LABEL: setbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setbc24(i16 %a) {
+; CHECK-P10-LABEL: setbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setbc25(i8 %a) {
+; CHECK-P10-LABEL: setbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc26(i32 %a) {
+; CHECK-P10-LABEL: setbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc27(i64 %a) {
+; CHECK-P10-LABEL: setbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc28(i16 %a) {
+; CHECK-P10-LABEL: setbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc29(i8 %a) {
+; CHECK-P10-LABEL: setbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc30(i32 %a) {
+; CHECK-P10-LABEL: setbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc31(i64 %a) {
+; CHECK-P10-LABEL: setbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc32(i16 %a) {
+; CHECK-P10-LABEL: setbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setbc33(i8 %a) {
+; CHECK-P10-LABEL: setbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbc34(i32 %a) {
+; CHECK-P10-LABEL: setbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setbc35(i64 %a) {
+; CHECK-P10-LABEL: setbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setbc36(i16 %a) {
+; CHECK-P10-LABEL: setbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setbc37(i64 %a) {
+; CHECK-P10-LABEL: setbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc38(i64 %a) {
+; CHECK-P10-LABEL: setbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setbc39(i64 %a) {
+; CHECK-P10-LABEL: setbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setbc-rr.ll
@@ -0,0 +1,720 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setbc1(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc2(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc3(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc4(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define void @setbc5(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbc6(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setbc7(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc8(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+
+define void @setbc9(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define signext i32 @setbc10(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc11(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define signext i32 @setbc12(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc13(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define signext i32 @setbc14(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbc15(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define signext i32 @setbc16(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc17(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define signext i32 @setbc18(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc19(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define void @setbc20(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define signext i32 @setbc21(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbc22(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define signext i32 @setbc23(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc24(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define signext i32 @setbc25(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc26(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define void @setbc27(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define signext i32 @setbc28(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define signext i64 @setbc29(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+
+define void @setbc30(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define signext i32 @setbc31(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbc32(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define i64 @setbc33(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+
+define void @setbc34(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define i64 @setbc35(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbc36(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define void @setbc37(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define i64 @setbc38(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+
+define void @setbc39(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define i64 @setbc40(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbc40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+
+define void @setbc41(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbc41:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define i64 @setbc42(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbc42:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbc43(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbc43:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define i64 @setbc44(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc44:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbc45(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc45:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define i64 @setbc46(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbc46:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+
+define void @setbc47(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbc47:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define i64 @setbc48(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc48:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbc49(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc49:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define i64 @setbc50(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbc50:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setnbc51(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc51:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setbcr-ri.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setbcr1(i8 %a) {
+; CHECK-P10-LABEL: setbcr1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbcr2(i32 %a) {
+; CHECK-P10-LABEL: setbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbcr3(i64 %a) {
+; CHECK-P10-LABEL: setbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbcr4(i16 %a) {
+; CHECK-P10-LABEL: setbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbcr5(i8 %a) {
+; CHECK-P10-LABEL: setbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbcr6(i32 %a) {
+; CHECK-P10-LABEL: setbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbcr7(i64 %a) {
+; CHECK-P10-LABEL: setbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbcr8(i16 %a) {
+; CHECK-P10-LABEL: setbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setbcr9(i8 %a) {
+; CHECK-P10-LABEL: setbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv1 = zext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbcr10(i32 %a) {
+; CHECK-P10-LABEL: setbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv1 = zext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setbcr11(i64 %a) {
+; CHECK-P10-LABEL: setbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setbcr12(i16 %a) {
+; CHECK-P10-LABEL: setbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv1 = zext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setbcr-rr.ll
@@ -0,0 +1,822 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+
+define signext i32 @setbcr1(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+
+define signext i32 @setbcr2(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+
+define signext i32 @setbcr3(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+
+define signext i32 @setbcr4(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbcr5(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define void @setbcr6(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define signext i32 @setbcr7(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define signext i64 @setbcr8(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+
+define void @setbcr9(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define signext i32 @setbcr10(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbcr11(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define signext i32 @setbcr12(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbcr13(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+
+define signext i32 @setbcr14(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbcr15(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+
+define signext i32 @setbcr16(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbcr17(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define signext i32 @setbcr18(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbcr19(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+
+define signext i32 @setbcr20(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+
+define void @setbcr21(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define signext i32 @setbcr22(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+
+define void @setbcr23(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define signext i32 @setbcr24(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define void @setbcr25(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setbcr26(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setbcr27(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setbcr28(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setbcr29(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define void @setbcr30(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setbcr31(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbcr31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define void @setbcr32(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setbcr32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setbcr33(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbcr33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setbcr34(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setbcr34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setbcr35(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbcr35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv2 = zext i1 %cmp to i32
+  ret i32 %conv2
+}
+
+define void @setbcr36(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setbcr36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setbcr37(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setbcr38(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setbcr39(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setbcr40(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setbcr41(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr41:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setbcr42(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr42:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setbcr43(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr43:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setbcr44(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr44:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define i64 @setbcr45(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr45:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbcr46(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr46:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define i64 @setbcr47(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr47:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setbcr48(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setbcr48:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = zext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setbcr49(i32 signext %a, i32 signext %b)  {
+; CHECK-P10-LABEL: setbcr49:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setbcr50(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setbcr50:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv = zext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+
+define i64 @setbcr51(i64 %a, i64 %b)  {
+; CHECK-P10-LABEL: setbcr51:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbcr52(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr52:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setbcr53(i16 signext %a, i16 signext %b)  {
+; CHECK-P10-LABEL: setbcr53:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setbcr54(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setbcr54:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = zext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+
+define i64 @setbcr55(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr55:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+
+define void @setbcr56(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr56:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define i64 @setbcr57(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr57:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setbcr58(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr58:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setbcr59(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr59:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setbcr60(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setbcr60:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = zext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/p10-setboolean-ext-fp.ll b/llvm/test/CodeGen/PowerPC/p10-setboolean-ext-fp.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setboolean-ext-fp.ll
@@ -0,0 +1,1464 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc(float %a, float %b) {
+; CHECK-P10-LABEL: setbc:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge float %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc2(float %a, float %b) {
+; CHECK-P10-LABEL: setbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc2(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr2(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge float %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr2(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc3(double %a, double %b) {
+; CHECK-P10-LABEL: setbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc3(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr3(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge double %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr3(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc4(double %a, double %b) {
+; CHECK-P10-LABEL: setbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc4(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp olt double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr4(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge double %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr4(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uge double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc5(float %a, float %b) {
+; CHECK-P10-LABEL: setbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc5(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr5(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule float %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr5(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc6(double %a, double %b) {
+; CHECK-P10-LABEL: setbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc6(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr6(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule double %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr6(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc7(float %a, float %b) {
+; CHECK-P10-LABEL: setbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc7(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr7(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule float %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr7(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc8(double %a, double %b) {
+; CHECK-P10-LABEL: setbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc8(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ogt double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr8(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule double %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr8(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ule double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc9(float %a, float %b) {
+; CHECK-P10-LABEL: setbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc9(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr9(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une float %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr9(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc10(double %a, double %b) {
+; CHECK-P10-LABEL: setbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc10(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr10(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une double %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr10(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc11(float %a, float %b) {
+; CHECK-P10-LABEL: setbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc11(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr11(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une float %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr11(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc12(double %a, double %b) {
+; CHECK-P10-LABEL: setbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc12(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oeq double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr12(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une double %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr12(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp une double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc13(float %a, float %b) {
+; CHECK-P10-LABEL: setbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc13(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr13(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord float %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr13(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord float %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbc14(double %a, double %b) {
+; CHECK-P10-LABEL: setbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbc14(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setbcr14(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord double %a, %b
+  %lnot.ext = zext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i32 @setnbcr14(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord double %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc15(float %a, float %b) {
+; CHECK-P10-LABEL: setbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc15(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr15(float %a, float %b) {
+; CHECK-P10-LABEL: setbcr15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord float %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr15(float %a, float %b) {
+; CHECK-P10-LABEL: setnbcr15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord float %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbc16(double %a, double %b) {
+; CHECK-P10-LABEL: setbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbc16(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbc r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp uno double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setbcr16(double %a, double %b) {
+; CHECK-P10-LABEL: setbcr16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord double %a, %b
+  %lnot.ext = zext i1 %cmp to i64
+  ret i64 %lnot.ext
+}
+
+; Function Attrs: norecurse nounwind readnone
+define signext i64 @setnbcr16(double %a, double %b) {
+; CHECK-P10-LABEL: setnbcr16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    setnbcr r3, un
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ord double %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+define signext i32 @setbc17(float %a, float %b) {
+; CHECK-P10-LABEL: setbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc17(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc18(double %a, double %b) {
+; CHECK-P10-LABEL: setbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc18(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc19(float %a, float %b) {
+; CHECK-P10-LABEL: setbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc19(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc20(double %a, double %b) {
+; CHECK-P10-LABEL: setbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc20(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, lt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ult double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setbc21(float %a, float %b) {
+; CHECK-P10-LABEL: setbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc21(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc22(double %a, double %b) {
+; CHECK-P10-LABEL: setbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc22(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc23(float %a, float %b) {
+; CHECK-P10-LABEL: setbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc23(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc24(double %a, double %b) {
+; CHECK-P10-LABEL: setbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc24(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, lt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp oge double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setbc25(float %a, float %b) {
+; CHECK-P10-LABEL: setbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc25(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc26(double %a, double %b) {
+; CHECK-P10-LABEL: setbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc26(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc27(float %a, float %b) {
+; CHECK-P10-LABEL: setbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc27(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc28(double %a, double %b) {
+; CHECK-P10-LABEL: setbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc28(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, gt
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ole double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setbc29(float %a, float %b) {
+; CHECK-P10-LABEL: setbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc29(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc30(double %a, double %b) {
+; CHECK-P10-LABEL: setbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc30(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc31(float %a, float %b) {
+; CHECK-P10-LABEL: setbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc31(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc32(double %a, double %b) {
+; CHECK-P10-LABEL: setbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc32(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, gt, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ugt double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setbc33(float %a, float %b) {
+; CHECK-P10-LABEL: setbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc33(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc34(double %a, double %b) {
+; CHECK-P10-LABEL: setbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc34(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc35(float %a, float %b) {
+; CHECK-P10-LABEL: setbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc35(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc36(double %a, double %b) {
+; CHECK-P10-LABEL: setbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc36(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    cror 4*cr5+lt, eq, un
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp ueq double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setbc37(float %a, float %b) {
+; CHECK-P10-LABEL: setbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one float %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc37(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one float %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setbc38(double %a, double %b) {
+; CHECK-P10-LABEL: setbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one double %a, %b
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc38(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one double %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setbc39(float %a, float %b) {
+; CHECK-P10-LABEL: setbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one float %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc39(float %a, float %b) {
+; CHECK-P10-LABEL: setnbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one float %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setbc40(double %a, double %b) {
+; CHECK-P10-LABEL: setbc40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one double %a, %b
+  %conv = zext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc40(double %a, double %b) {
+; CHECK-P10-LABEL: setnbc40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    fcmpu cr0, f1, f2
+; CHECK-P10-NEXT:    crnor 4*cr5+lt, un, eq
+; CHECK-P10-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = fcmp one double %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbc-ri.ll
@@ -0,0 +1,904 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setnbc1(i8 %a) {
+; CHECK-P10-LABEL: setnbc1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc2(i32 %a) {
+; CHECK-P10-LABEL: setnbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc3(i64 %a) {
+; CHECK-P10-LABEL: setnbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc4(i16 %a) {
+; CHECK-P10-LABEL: setnbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc5(i8 %a) {
+; CHECK-P10-LABEL: setnbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc6(i32 %a) {
+; CHECK-P10-LABEL: setnbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc7(i64 %a) {
+; CHECK-P10-LABEL: setnbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc8(i16 %a) {
+; CHECK-P10-LABEL: setnbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc9(i8 %a) {
+; CHECK-P10-LABEL: setnbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 1
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc10(i32 %a) {
+; CHECK-P10-LABEL: setnbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 1
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc11(i64 %a) {
+; CHECK-P10-LABEL: setnbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbc12(i16 %a) {
+; CHECK-P10-LABEL: setnbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 1
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc13(i8 %a) {
+; CHECK-P10-LABEL: setnbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc14(i32 %a) {
+; CHECK-P10-LABEL: setnbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc15(i64 %a) {
+; CHECK-P10-LABEL: setnbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc16(i16 %a) {
+; CHECK-P10-LABEL: setnbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc17(i8 %a) {
+; CHECK-P10-LABEL: setnbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc18(i32 %a) {
+; CHECK-P10-LABEL: setnbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc19(i64 %a) {
+; CHECK-P10-LABEL: setnbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc20(i16 %a) {
+; CHECK-P10-LABEL: setnbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc21(i8 %a) {
+; CHECK-P10-LABEL: setnbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 1
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc22(i32 %a) {
+; CHECK-P10-LABEL: setnbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 1
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc23(i64 %a) {
+; CHECK-P10-LABEL: setnbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbc24(i16 %a) {
+; CHECK-P10-LABEL: setnbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh r3, r3
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 1
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc25(i8 %a) {
+; CHECK-P10-LABEL: setnbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc26(i32 %a) {
+; CHECK-P10-LABEL: setnbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc27(i64 %a) {
+; CHECK-P10-LABEL: setnbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc28(i16 %a) {
+; CHECK-P10-LABEL: setnbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc29(i8 %a) {
+; CHECK-P10-LABEL: setnbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc30(i32 %a) {
+; CHECK-P10-LABEL: setnbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc31(i64 %a) {
+; CHECK-P10-LABEL: setnbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc32(i16 %a) {
+; CHECK-P10-LABEL: setnbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc33(i8 %a) {
+; CHECK-P10-LABEL: setnbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 1
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc34(i32 %a) {
+; CHECK-P10-LABEL: setnbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 1
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc35(i64 %a) {
+; CHECK-P10-LABEL: setnbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbc36(i16 %a) {
+; CHECK-P10-LABEL: setnbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 1
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc37(i64 %a) {
+; CHECK-P10-LABEL: setnbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc38(i64 %a) {
+; CHECK-P10-LABEL: setnbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc39(i64 %a) {
+; CHECK-P10-LABEL: setnbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpldi r3, 1
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbc40(i8 %a) {
+; CHECK-P10-LABEL: setnbc40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc41(i32 %a) {
+; CHECK-P10-LABEL: setnbc41:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc42(i16 %a) {
+; CHECK-P10-LABEL: setnbc42:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc43(i8 %a) {
+; CHECK-P10-LABEL: setnbc43:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc44(i32 %a) {
+; CHECK-P10-LABEL: setnbc44:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc45(i16 %a) {
+; CHECK-P10-LABEL: setnbc45:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i32 @setnbc46(i8 %a) {
+; CHECK-P10-LABEL: setnbc46:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc47(i32 %a) {
+; CHECK-P10-LABEL: setnbc47:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc48(i64 %a) {
+; CHECK-P10-LABEL: setnbc48:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc49(i16 %a) {
+; CHECK-P10-LABEL: setnbc49:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc50(i8 %a) {
+; CHECK-P10-LABEL: setnbc50:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc51(i32 %a) {
+; CHECK-P10-LABEL: setnbc51:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc52(i64 %a) {
+; CHECK-P10-LABEL: setnbc52:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc53(i16 %a) {
+; CHECK-P10-LABEL: setnbc53:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc54(i8 %a) {
+; CHECK-P10-LABEL: setnbc54:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsb. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, 0
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc55(i32 %a) {
+; CHECK-P10-LABEL: setnbc55:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, 0
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc56(i64 %a) {
+; CHECK-P10-LABEL: setnbc56:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbc57(i16 %a) {
+; CHECK-P10-LABEL: setnbc57:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    extsh. r3, r3
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, 0
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc58(i8 %a) {
+; CHECK-P10-LABEL: setnbc58:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc59(i32 %a) {
+; CHECK-P10-LABEL: setnbc59:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc60(i64 %a) {
+; CHECK-P10-LABEL: setnbc60:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc61(i16 %a) {
+; CHECK-P10-LABEL: setnbc61:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc62(i8 %a) {
+; CHECK-P10-LABEL: setnbc62:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc63(i32 %a) {
+; CHECK-P10-LABEL: setnbc63:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc64(i64 %a) {
+; CHECK-P10-LABEL: setnbc64:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbc65(i16 %a) {
+; CHECK-P10-LABEL: setnbc65:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc66(i8 %a) {
+; CHECK-P10-LABEL: setnbc66:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, 0
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc67(i32 %a) {
+; CHECK-P10-LABEL: setnbc67:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, 0
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc68(i64 %a) {
+; CHECK-P10-LABEL: setnbc68:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, 0
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbc69(i16 %a) {
+; CHECK-P10-LABEL: setnbc69:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, 0
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbc-rr.ll
@@ -0,0 +1,991 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setnbc1(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc2(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc3(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbc4(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+; function attrs: norecurse nounwind
+define void @setnbc5(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc6(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc7(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbc8(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbc9(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbc10(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setnbc11(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc12(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setnbc13(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setnbc14(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setnbc15(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc16(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setnbc17(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc18(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc19(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc20(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc21(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc22(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbc23(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc24(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc25(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc26(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setnbc27(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc28(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc29(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc30(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc31(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc32(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbc33(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc34(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define signext i64 @setnbc35(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %sub = sext i1 %cmp to i64
+  ret i64 %sub
+}
+
+define void @setnbc36(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbc37(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc38(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbc39(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc40(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setnbc41(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc41:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc42(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc42:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbc43(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc43:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbc44(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc44:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbc45(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc45:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc46(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbc46:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbc47(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc47:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc48(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbc48:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbc49(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc49:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbc50(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc50:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc51(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbc51:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbc52(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc52:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc53(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc53:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbc54(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc54:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc55(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc55:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setnbc56(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc56:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc57(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc57:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbc58(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc58:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc59(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc59:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp eq i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbc60(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc60:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc61(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc61:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbc62(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc62:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc63(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc63:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbc64(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc64:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc65(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc65:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setnbc66(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc66:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc67(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc67:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ugt i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbc68(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc68:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc69(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbc69:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp slt i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbc70(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc70:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc71(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbc71:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbc72(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc72:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbc73(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbc73:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setnbc74(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc74:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbc75(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbc75:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbc r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ult i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll b/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbcr-ri.ll
@@ -0,0 +1,326 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setnbcr1(i8 %a) {
+; CHECK-P10-LABEL: setnbcr1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr2(i32 %a) {
+; CHECK-P10-LABEL: setnbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr3(i64 %a) {
+; CHECK-P10-LABEL: setnbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr4(i16 %a) {
+; CHECK-P10-LABEL: setnbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbcr5(i8 %a) {
+; CHECK-P10-LABEL: setnbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr6(i32 %a) {
+; CHECK-P10-LABEL: setnbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr7(i64 %a) {
+; CHECK-P10-LABEL: setnbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr8(i16 %a) {
+; CHECK-P10-LABEL: setnbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbcr9(i8 %a) {
+; CHECK-P10-LABEL: setnbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 255
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, 1
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbcr10(i32 %a) {
+; CHECK-P10-LABEL: setnbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, 1
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbcr11(i64 %a) {
+; CHECK-P10-LABEL: setnbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 0
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbcr12(i16 %a) {
+; CHECK-P10-LABEL: setnbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    andi. r3, r3, 65535
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, 1
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbcr13(i8 %a) {
+; CHECK-P10-LABEL: setnbcr13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr14(i32 %a) {
+; CHECK-P10-LABEL: setnbcr14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr15(i64 %a) {
+; CHECK-P10-LABEL: setnbcr15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i32 @setnbcr16(i16 %a) {
+; CHECK-P10-LABEL: setnbcr16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbcr17(i8 %a) {
+; CHECK-P10-LABEL: setnbcr17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr18(i32 %a) {
+; CHECK-P10-LABEL: setnbcr18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr19(i64 %a) {
+; CHECK-P10-LABEL: setnbcr19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define signext i64 @setnbcr20(i16 %a) {
+; CHECK-P10-LABEL: setnbcr20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbcr21(i8 %a) {
+; CHECK-P10-LABEL: setnbcr21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 24
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, 1
+  %conv1 = sext i1 %cmp to i8
+  store i8 %conv1, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbcr22(i32 %a) {
+; CHECK-P10-LABEL: setnbcr22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, 1
+  %conv1 = sext i1 %cmp to i32
+  store i32 %conv1, i32* @globalVal2, align 4
+  ret void
+}
+
+define void @setnbcr23(i64 %a) {
+; CHECK-P10-LABEL: setnbcr23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpdi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, 1
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define void @setnbcr24(i16 %a) {
+; CHECK-P10-LABEL: setnbcr24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 16
+; CHECK-P10-NEXT:    cmpwi r3, 1
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, 1
+  %conv1 = sext i1 %cmp to i16
+  store i16 %conv1, i16* @globalVal4, align 2
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll b/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-setnbcr-rr.ll
@@ -0,0 +1,1092 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
+; RUN:     --check-prefix=CHECK-P10
+
+; This file does not contain many test cases involving comparisons and logical
+; comparisons (cmplwi, cmpldi). This is because alternative code is generated
+; when there is a compare (logical or not), followed by a sign or zero extend.
+; This codegen will be re-evaluated at a later time on whether or not it should
+; be emitted on P10.
+
+@globalVal = common local_unnamed_addr global i8 0, align 1
+@globalVal2 = common local_unnamed_addr global i32 0, align 4
+@globalVal3 = common local_unnamed_addr global i64 0, align 8
+@globalVal4 = common local_unnamed_addr global i16 0, align 2
+
+define signext i32 @setnbcr1(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %lnot.ext = sext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+define signext i32 @setnbcr2(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %lnot.ext = sext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+define signext i32 @setnbcr3(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr3:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %lnot.ext = sext i1 %cmp to i32
+  ret i32 %lnot.ext
+}
+
+define signext i32 @setnbcr4(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr4:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define void @setnbcr5(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr5:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbcr6(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr6:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbcr7(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr7:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = sext i1 %cmp to i32
+  ret i32 %conv
+}
+
+define signext i64 @setnbcr8(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr8:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv = sext i1 %cmp to i64
+  ret i64 %conv
+}
+
+define void @setnbcr9(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr9:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbcr10(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr10:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr11(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr11:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbcr12(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr12:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr13(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr13:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal
+  ret void
+}
+
+define signext i32 @setnbcr14(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr14:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr15(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr15:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2
+  ret void
+}
+
+define signext i32 @setnbcr16(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr16:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr17(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr17:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define signext i32 @setnbcr18(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr18:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr19(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr19:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4
+  ret void
+}
+
+define signext i32 @setnbcr20(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr20:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr21(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr21:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setnbcr22(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr22:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr23(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr23:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbcr24(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr24:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr25(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr25:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbcr26(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr26:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr27(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr27:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbcr28(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr28:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr29(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr29:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal
+  ret void
+}
+
+define signext i32 @setnbcr30(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr30:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr31(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr31:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2
+  ret void
+}
+
+define signext i32 @setnbcr32(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr32:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr33(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr33:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define signext i32 @setnbcr34(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr34:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr35(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr35:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4
+  ret void
+}
+
+define signext i32 @setnbcr36(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr36:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr37(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr37:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define void @setnbcr38(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr38:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbcr39(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr39:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr40(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr40:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define signext i32 @setnbcr41(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr41:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr42(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr42:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define signext i32 @setnbcr43(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr43:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @sernbcr44(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: sernbcr44:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define signext i32 @setnbcr45(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr45:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr46(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr46:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i32 %a, %b
+  %conv = sext i1 %cmp to i32
+  store i32 %conv, i32* @globalVal2, align 4
+  ret void
+}
+
+define signext i32 @setnbcr47(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr47:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %sub = sext i1 %cmp to i32
+  ret i32 %sub
+}
+
+define void @setnbcr48(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr48:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbcr49(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr49:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr50(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr50:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbcr51(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr51:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr52(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr52:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setnbcr53(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr53:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr54(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr54:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbcr55(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr55:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr56(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr56:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbcr57(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr57:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr58(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr58:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal
+  ret void
+}
+
+define i64 @setnbcr59(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr59:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr60(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr60:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2
+  ret void
+}
+
+define i64 @setnbcr61(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr61:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr62(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr62:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define i64 @setnbcr63(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr63:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr64(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr64:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, lt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp uge i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4
+  ret void
+}
+
+define i64 @setnbcr65(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr65:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr66(i8 signext %a, i8 signext %b) {
+; CHECK-P10-LABEL: setnbcr66:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal, align 1
+  ret void
+}
+
+define i64 @setnbcr67(i32 signext %a, i32 signext %b)  {
+; CHECK-P10-LABEL: setnbcr67:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr68(i32 signext %a, i32 signext %b) {
+; CHECK-P10-LABEL: setnbcr68:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2, align 4
+  ret void
+}
+
+define i64 @setnbcr69(i64 %a, i64 %b)  {
+; CHECK-P10-LABEL: setnbcr69:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr70(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr70:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
+define i64 @setnbcr71(i16 signext %a, i16 signext %b)  {
+; CHECK-P10-LABEL: setnbcr71:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr72(i16 signext %a, i16 signext %b) {
+; CHECK-P10-LABEL: setnbcr72:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp sle i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4, align 2
+  ret void
+}
+
+define i64 @setnbcr73(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr73:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr74(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr74:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstb r3, globalVal@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i8 %a, %b
+  %conv3 = sext i1 %cmp to i8
+  store i8 %conv3, i8* @globalVal
+  ret void
+}
+
+define i64 @setnbcr75(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr75:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr76(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr76:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstw r3, globalVal2@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i32 %a, %b
+  %sub = sext i1 %cmp to i32
+  store i32 %sub, i32* @globalVal2
+  ret void
+}
+
+define i64 @setnbcr77(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr77:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr78(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr78:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpld r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3
+  ret void
+}
+
+define i64 @setnbcr79(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr79:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i64
+  ret i64 %conv3
+}
+
+define void @setnbcr80(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-P10-LABEL: setnbcr80:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, gt
+; CHECK-P10-NEXT:    psth r3, globalVal4@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ule i16 %a, %b
+  %conv3 = sext i1 %cmp to i16
+  store i16 %conv3, i16* @globalVal4
+  ret void
+}
+
+define i64 @setnbcr81(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr81:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define i64 @setnbcr82(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr82:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  ret i64 %conv1
+}
+
+define void @setnbcr83(i64 %a, i64 %b) {
+; CHECK-P10-LABEL: setnbcr83:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    cmpd r3, r4
+; CHECK-P10-NEXT:    setnbcr r3, eq
+; CHECK-P10-NEXT:    pstd r3, globalVal3@PCREL(0), 1
+; CHECK-P10-NEXT:    blr
+entry:
+  %cmp = icmp ne i64 %a, %b
+  %conv1 = sext i1 %cmp to i64
+  store i64 %conv1, i64* @globalVal3, align 8
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
@@ -0,0 +1,337 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
+; This test case tests spilling the CR EQ bit on Power10. On Power10, this is
+; achieved by setb %reg, %CRREG (eq bit) -> stw %reg, $FI instead of:
+; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
+
+; Without fine-grained control over clobbering individual CR bits,
+; it is difficult to produce a concise test case that will ensure a specific
+; bit of any CR field is spilled. We need to test the spilling of a CR bit
+; other than the LT bit. Hence this test case is rather complex.
+
+%0 = type { i32, %1*, %0*, [1 x i8], i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
+%1 = type { %1*, %0*, i32 }
+%2 = type { [200 x i8], [200 x i8], %3*, %3*, %4*, %4*, %4*, %4*, %4*, i64 }
+%3 = type { i64, i32, %3*, %3*, %3*, %3*, %4*, %4*, %4*, %4*, i64, i32, i32 }
+%4 = type { i32, i64, %3*, %3*, i16, %4*, %4*, i64, i64 }
+
+define dso_local double @P10_Spill_CR_EQ(%2* %arg) local_unnamed_addr #0 {
+; CHECK-LABEL: P10_Spill_CR_EQ:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    mfcr r12
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    ld r4, 0(0)
+; CHECK-NEXT:    ld r5, 56(0)
+; CHECK-NEXT:    cmpdi cr1, r3, 0
+; CHECK-NEXT:    cmpdi cr4, r4, 0
+; CHECK-NEXT:    cmpdi cr6, r5, 0
+; CHECK-NEXT:    cmpldi r3, 0
+; CHECK-NEXT:    beq cr0, .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %bb10
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    bc 12, 4*cr4+eq, .LBB0_4
+; CHECK-NEXT:  .LBB0_2: # %bb14
+; CHECK-NEXT:    lwz r5, 0(r3)
+; CHECK-NEXT:    b .LBB0_5
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    # implicit-def: $r3
+; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    # implicit-def: $r5
+; CHECK-NEXT:  .LBB0_5: # %bb16
+; CHECK-NEXT:    mfocrf r4, 64
+; CHECK-NEXT:    crnot 4*cr2+un, 4*cr1+eq
+; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr6+eq
+; CHECK-NEXT:    rotlwi r4, r4, 4
+; CHECK-NEXT:    stw r4, -4(r1)
+; CHECK-NEXT:    bc 12, 4*cr6+eq, .LBB0_7
+; CHECK-NEXT:  # %bb.6: # %bb18
+; CHECK-NEXT:    lwz r4, 0(r3)
+; CHECK-NEXT:    b .LBB0_8
+; CHECK-NEXT:  .LBB0_7:
+; CHECK-NEXT:    # implicit-def: $r4
+; CHECK-NEXT:  .LBB0_8: # %bb20
+; CHECK-NEXT:    cmpwi r3, -1
+; CHECK-NEXT:    cmpwi cr3, r4, -1
+; CHECK-NEXT:    cmpwi cr7, r3, 0
+; CHECK-NEXT:    cmpwi cr1, r4, 0
+; CHECK-NEXT:    # implicit-def: $x3
+; CHECK-NEXT:    crand 4*cr5+eq, gt, 4*cr2+un
+; CHECK-NEXT:    crand 4*cr5+gt, 4*cr3+gt, 4*cr5+lt
+; CHECK-NEXT:    setnbc r4, 4*cr5+eq
+; CHECK-NEXT:    stw r4, -20(r1)
+; CHECK-NEXT:    bc 4, 4*cr5+eq, .LBB0_10
+; CHECK-NEXT:  # %bb.9: # %bb34
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:  .LBB0_10: # %bb36
+; CHECK-NEXT:    mfocrf r4, 2
+; CHECK-NEXT:    cmpwi cr3, r5, 0
+; CHECK-NEXT:    rotlwi r4, r4, 24
+; CHECK-NEXT:    stw r4, -12(r1)
+; CHECK-NEXT:    # implicit-def: $x4
+; CHECK-NEXT:    bc 4, 4*cr5+gt, .LBB0_12
+; CHECK-NEXT:  # %bb.11: # %bb38
+; CHECK-NEXT:    ld r4, 0(r3)
+; CHECK-NEXT:  .LBB0_12: # %bb40
+; CHECK-NEXT:    mcrf cr6, cr4
+; CHECK-NEXT:    crnot 4*cr4+eq, 4*cr4+eq
+; CHECK-NEXT:    crand 4*cr4+lt, 4*cr7+lt, 4*cr2+un
+; CHECK-NEXT:    # implicit-def: $x6
+; CHECK-NEXT:    crand 4*cr4+gt, 4*cr1+lt, 4*cr5+lt
+; CHECK-NEXT:    bc 4, 4*cr4+gt, .LBB0_14
+; CHECK-NEXT:  # %bb.13: # %bb48
+; CHECK-NEXT:    ld r6, 0(r3)
+; CHECK-NEXT:  .LBB0_14: # %bb50
+; CHECK-NEXT:    cmpwi r5, -1
+; CHECK-NEXT:    crand 4*cr4+un, 4*cr3+lt, 4*cr4+eq
+; CHECK-NEXT:    # implicit-def: $r5
+; CHECK-NEXT:    bc 4, 4*cr4+lt, .LBB0_16
+; CHECK-NEXT:  # %bb.15: # %bb52
+; CHECK-NEXT:    lwz r5, 0(r3)
+; CHECK-NEXT:  .LBB0_16: # %bb54
+; CHECK-NEXT:    setnbc r7, 4*cr5+gt
+; CHECK-NEXT:    stw r7, -16(r1)
+; CHECK-NEXT:    mfocrf r7, 2
+; CHECK-NEXT:    rotlwi r7, r7, 24
+; CHECK-NEXT:    stw r7, -8(r1)
+; CHECK-NEXT:    # implicit-def: $r7
+; CHECK-NEXT:    bc 4, 4*cr4+un, .LBB0_18
+; CHECK-NEXT:  # %bb.17: # %bb56
+; CHECK-NEXT:    lwz r7, 0(r3)
+; CHECK-NEXT:  .LBB0_18: # %bb58
+; CHECK-NEXT:    crand 4*cr5+gt, 4*cr7+eq, 4*cr2+un
+; CHECK-NEXT:    mcrf cr2, cr1
+; CHECK-NEXT:    cmpwi cr1, r5, 1
+; CHECK-NEXT:    crand lt, gt, 4*cr4+eq
+; CHECK-NEXT:    # implicit-def: $x5
+; CHECK-NEXT:    setnbc r8, 4*cr5+gt
+; CHECK-NEXT:    crand 4*cr5+lt, 4*cr2+eq, 4*cr5+lt
+; CHECK-NEXT:    crand 4*cr4+eq, 4*cr3+eq, 4*cr4+eq
+; CHECK-NEXT:    crand gt, 4*cr1+lt, 4*cr4+lt
+; CHECK-NEXT:    stw r8, -24(r1)
+; CHECK-NEXT:    setnbc r8, 4*cr5+lt
+; CHECK-NEXT:    cmpwi cr5, r7, 1
+; CHECK-NEXT:    stw r8, -28(r1)
+; CHECK-NEXT:    lwz r6, 92(r6)
+; CHECK-NEXT:    crand eq, 4*cr5+lt, 4*cr4+un
+; CHECK-NEXT:    cmpwi cr6, r6, 1
+; CHECK-NEXT:    crand un, 4*cr6+lt, 4*cr4+gt
+; CHECK-NEXT:    bc 4, gt, .LBB0_20
+; CHECK-NEXT:  # %bb.19: # %bb68
+; CHECK-NEXT:    ld r5, 0(r3)
+; CHECK-NEXT:  .LBB0_20: # %bb70
+; CHECK-NEXT:    lwz r7, -20(r1)
+; CHECK-NEXT:    # implicit-def: $cr5lt
+; CHECK-NEXT:    mfocrf r6, 4
+; CHECK-NEXT:    xxlxor f2, f2, f2
+; CHECK-NEXT:    rlwimi r6, r7, 12, 20, 20
+; CHECK-NEXT:    mtocrf 4, r6
+; CHECK-NEXT:    ld r6, 0(r3)
+; CHECK-NEXT:    crandc 4*cr5+gt, lt, 4*cr3+eq
+; CHECK-NEXT:    lwz r8, -16(r1)
+; CHECK-NEXT:    # implicit-def: $cr5eq
+; CHECK-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr7+eq
+; CHECK-NEXT:    mfocrf r7, 4
+; CHECK-NEXT:    rlwimi r7, r8, 10, 22, 22
+; CHECK-NEXT:    mtocrf 4, r7
+; CHECK-NEXT:    lwz r7, -24(r1)
+; CHECK-NEXT:    # implicit-def: $cr5un
+; CHECK-NEXT:    lwz r9, -28(r1)
+; CHECK-NEXT:    crandc 4*cr5+eq, 4*cr5+eq, 4*cr2+eq
+; CHECK-NEXT:    isel r3, r3, r5, 4*cr5+lt
+; CHECK-NEXT:    crnor 4*cr5+lt, gt, 4*cr5+lt
+; CHECK-NEXT:    crnor 4*cr5+gt, eq, 4*cr5+gt
+; CHECK-NEXT:    crnor 4*cr5+eq, un, 4*cr5+eq
+; CHECK-NEXT:    mfocrf r5, 4
+; CHECK-NEXT:    rlwimi r5, r7, 9, 23, 23
+; CHECK-NEXT:    setbc r7, 4*cr4+eq
+; CHECK-NEXT:    mtocrf 4, r5
+; CHECK-NEXT:    setbc r5, 4*cr5+un
+; CHECK-NEXT:    # implicit-def: $cr5un
+; CHECK-NEXT:    mfocrf r8, 4
+; CHECK-NEXT:    add r5, r7, r5
+; CHECK-NEXT:    rlwimi r8, r9, 9, 23, 23
+; CHECK-NEXT:    lwz r9, -4(r1)
+; CHECK-NEXT:    mtocrf 4, r8
+; CHECK-NEXT:    mtocrf 128, r9
+; CHECK-NEXT:    lwz r9, -8(r1)
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    setbc r8, 4*cr5+un
+; CHECK-NEXT:    isel r6, 0, r6, 4*cr5+gt
+; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+eq
+; CHECK-NEXT:    add r5, r8, r5
+; CHECK-NEXT:    iseleq r3, 0, r3
+; CHECK-NEXT:    mtfprd f0, r5
+; CHECK-NEXT:    mtocrf 128, r9
+; CHECK-NEXT:    lwz r9, -12(r1)
+; CHECK-NEXT:    lwz r12, 8(r1)
+; CHECK-NEXT:    xscvsxddp f0, f0
+; CHECK-NEXT:    iseleq r6, 0, r6
+; CHECK-NEXT:    mtocrf 128, r9
+; CHECK-NEXT:    add r3, r6, r3
+; CHECK-NEXT:    mtocrf 32, r12
+; CHECK-NEXT:    mtocrf 16, r12
+; CHECK-NEXT:    mtocrf 8, r12
+; CHECK-NEXT:    iseleq r4, 0, r4
+; CHECK-NEXT:    add r3, r4, r3
+; CHECK-NEXT:    xsmuldp f0, f0, f2
+; CHECK-NEXT:    mtfprd f1, r3
+; CHECK-NEXT:    xscvsxddp f1, f1
+; CHECK-NEXT:    xsadddp f1, f0, f1
+; CHECK-NEXT:    blr
+bb:
+  %tmp = getelementptr inbounds %4, %4* null, i64 undef, i32 7
+  %tmp1 = load i64, i64* undef, align 8
+  %tmp2 = load i64, i64* null, align 8
+  %tmp3 = load i64, i64* %tmp, align 8
+  %tmp4 = icmp eq i64 %tmp1, 0
+  %tmp5 = icmp eq i64 %tmp2, 0
+  %tmp6 = icmp eq i64 %tmp3, 0
+  %tmp7 = xor i1 %tmp4, true
+  %tmp8 = xor i1 %tmp5, true
+  %tmp9 = xor i1 %tmp6, true
+  br i1 %tmp4, label %bb12, label %bb10
+
+bb10:                                             ; preds = %bb
+  %tmp11 = load i32, i32* undef, align 8
+  br label %bb12
+
+bb12:                                             ; preds = %bb10, %bb
+  %tmp13 = phi i32 [ undef, %bb ], [ %tmp11, %bb10 ]
+  br i1 %tmp5, label %bb16, label %bb14
+
+bb14:                                             ; preds = %bb12
+  %tmp15 = load i32, i32* undef, align 8
+  br label %bb16
+
+bb16:                                             ; preds = %bb14, %bb12
+  %tmp17 = phi i32 [ undef, %bb12 ], [ %tmp15, %bb14 ]
+  br i1 %tmp6, label %bb20, label %bb18
+
+bb18:                                             ; preds = %bb16
+  %tmp19 = load i32, i32* undef, align 8
+  br label %bb20
+
+bb20:                                             ; preds = %bb18, %bb16
+  %tmp21 = phi i32 [ undef, %bb16 ], [ %tmp19, %bb18 ]
+  %tmp22 = icmp slt i32 %tmp13, 0
+  %tmp23 = icmp slt i32 %tmp17, 0
+  %tmp24 = icmp slt i32 %tmp21, 0
+  %tmp25 = icmp eq i32 %tmp13, 0
+  %tmp26 = icmp eq i32 %tmp17, 0
+  %tmp27 = icmp eq i32 %tmp21, 0
+  %tmp28 = xor i1 %tmp22, true
+  %tmp29 = xor i1 %tmp23, true
+  %tmp30 = xor i1 %tmp24, true
+  %tmp31 = and i1 %tmp28, %tmp7
+  %tmp32 = and i1 %tmp29, %tmp8
+  %tmp33 = and i1 %tmp30, %tmp9
+  br i1 %tmp31, label %bb34, label %bb36
+
+bb34:                                             ; preds = %bb20
+  %tmp35 = load i64, i64* undef, align 8
+  br label %bb36
+
+bb36:                                             ; preds = %bb34, %bb20
+  %tmp37 = phi i64 [ undef, %bb20 ], [ %tmp35, %bb34 ]
+  br i1 %tmp33, label %bb38, label %bb40
+
+bb38:                                             ; preds = %bb36
+  %tmp39 = load i64, i64* undef, align 8
+  br label %bb40
+
+bb40:                                             ; preds = %bb38, %bb36
+  %tmp41 = phi i64 [ undef, %bb36 ], [ %tmp39, %bb38 ]
+  %tmp42 = and i1 %tmp25, %tmp7
+  %tmp43 = and i1 %tmp26, %tmp8
+  %tmp44 = and i1 %tmp27, %tmp9
+  %tmp45 = and i1 %tmp22, %tmp7
+  %tmp46 = and i1 %tmp23, %tmp8
+  %tmp47 = and i1 %tmp24, %tmp9
+  br i1 %tmp47, label %bb48, label %bb50
+
+bb48:                                             ; preds = %bb40
+  %tmp49 = load %3*, %3** undef, align 8
+  br label %bb50
+
+bb50:                                             ; preds = %bb48, %bb40
+  %tmp51 = phi %3* [ undef, %bb40 ], [ %tmp49, %bb48 ]
+  br i1 %tmp45, label %bb52, label %bb54
+
+bb52:                                             ; preds = %bb50
+  %tmp53 = load i32, i32* undef, align 8
+  br label %bb54
+
+bb54:                                             ; preds = %bb52, %bb50
+  %tmp55 = phi i32 [ undef, %bb50 ], [ %tmp53, %bb52 ]
+  br i1 %tmp46, label %bb56, label %bb58
+
+bb56:                                             ; preds = %bb54
+  %tmp57 = load i32, i32* undef, align 8
+  br label %bb58
+
+bb58:                                             ; preds = %bb56, %bb54
+  %tmp59 = phi i32 [ undef, %bb54 ], [ %tmp57, %bb56 ]
+  %tmp60 = getelementptr inbounds %3, %3* %tmp51, i64 0, i32 12
+  %tmp61 = load i32, i32* %tmp60, align 8
+  %tmp62 = icmp slt i32 %tmp55, 1
+  %tmp63 = icmp slt i32 %tmp59, 1
+  %tmp64 = icmp slt i32 %tmp61, 1
+  %tmp65 = and i1 %tmp62, %tmp45
+  %tmp66 = and i1 %tmp63, %tmp46
+  %tmp67 = and i1 %tmp64, %tmp47
+  br i1 %tmp65, label %bb68, label %bb70
+
+bb68:                                             ; preds = %bb58
+  %tmp69 = load i64, i64* undef, align 8
+  br label %bb70
+
+bb70:                                             ; preds = %bb68, %bb58
+  %tmp71 = phi i64 [ undef, %bb58 ], [ %tmp69, %bb68 ]
+  %tmp72 = load i64, i64* undef, align 8
+  %tmp73 = xor i1 %tmp25, true
+  %tmp74 = xor i1 %tmp26, true
+  %tmp75 = xor i1 %tmp27, true
+  %tmp76 = and i1 %tmp31, %tmp73
+  %tmp77 = and i1 %tmp32, %tmp74
+  %tmp78 = and i1 %tmp33, %tmp75
+  %tmp79 = select i1 %tmp76, i64 %tmp37, i64 %tmp71
+  %tmp80 = select i1 %tmp77, i64 undef, i64 %tmp72
+  %tmp81 = select i1 %tmp78, i64 %tmp41, i64 undef
+  %tmp82 = or i1 %tmp65, %tmp76
+  %tmp83 = or i1 %tmp66, %tmp77
+  %tmp84 = or i1 %tmp67, %tmp78
+  %tmp85 = zext i1 %tmp42 to i64
+  %tmp86 = add i64 0, %tmp85
+  %tmp87 = zext i1 %tmp43 to i64
+  %tmp88 = add i64 0, %tmp87
+  %tmp89 = zext i1 %tmp44 to i64
+  %tmp90 = add i64 0, %tmp89
+  %tmp91 = select i1 %tmp82, i64 %tmp79, i64 0
+  %tmp92 = add i64 0, %tmp91
+  %tmp93 = select i1 %tmp83, i64 %tmp80, i64 0
+  %tmp94 = add i64 0, %tmp93
+  %tmp95 = select i1 %tmp84, i64 %tmp81, i64 0
+  %tmp96 = add i64 0, %tmp95
+  %tmp97 = select i1 %tmp42, i64 undef, i64 %tmp92
+  %tmp98 = select i1 %tmp43, i64 undef, i64 %tmp94
+  %tmp99 = select i1 %tmp44, i64 undef, i64 %tmp96
+  %tmp100 = select i1 %tmp4, i64 0, i64 %tmp97
+  %tmp101 = select i1 %tmp5, i64 0, i64 %tmp98
+  %tmp102 = select i1 %tmp6, i64 0, i64 %tmp99
+  %tmp103 = add i64 %tmp88, %tmp86
+  %tmp104 = add i64 %tmp90, %tmp103
+  %tmp105 = add i64 0, %tmp104
+  %tmp106 = add i64 %tmp101, %tmp100
+  %tmp107 = add i64 %tmp102, %tmp106
+  %tmp108 = add i64 0, %tmp107
+  %tmp109 = sitofp i64 %tmp105 to double
+  %tmp110 = sitofp i64 %tmp108 to double
+  %tmp111 = fmul double %tmp109, 0.000000e+00
+  %tmp112 = fadd double %tmp111, %tmp110
+  ret double %tmp112
+}
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
@@ -0,0 +1,432 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
+; This test case tests spilling the CR GT bit on Power10. On Power10, this is
+; achieved by setb %reg, %CRREG (gt bit) -> stw %reg, $FI instead of:
+; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
+
+; Without fine-grained control over clobbering individual CR bits,
+; it is difficult to produce a concise test case that will ensure a specific
+; bit of any CR field is spilled. We need to test the spilling of a CR bit
+; other than the LT bit. Hence this test case is rather complex.
+
+define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
+; CHECK-LABEL: P10_Spill_CR_GT:
+; CHECK:         .localentry P10_Spill_CR_GT, 1
+; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    mfcr r12
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    stdu r1, -80(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r29, -24
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    .cfi_offset cr2, 8
+; CHECK-NEXT:    .cfi_offset cr3, 8
+; CHECK-NEXT:    .cfi_offset cr4, 8
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    paddi r29, 0, .LJTI0_0@PCREL, 1
+; CHECK-NEXT:    srwi r4, r3, 4
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    andi. r4, r4, 1
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    crmove 4*cr4+lt, gt
+; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    setnbc r3, gt
+; CHECK-NEXT:    stw r3, 52(r1)
+; CHECK-NEXT:    cmplwi cr3, r3, 336
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    sldi r30, r3, 2
+; CHECK-NEXT:    b .LBB0_2
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_1: # %bb43
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl call_1@notoc
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    setnbc r3, 4*cr2+eq
+; CHECK-NEXT:    stb r4, 0(r3)
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:  .LBB0_2: # %bb5
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 12, 4*cr4+lt, .LBB0_31
+; CHECK-NEXT:  # %bb.3: # %bb10
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bgt cr3, .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %bb10
+; CHECK-NEXT:    #
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    lwz r5, 0(r3)
+; CHECK-NEXT:    rlwinm r4, r5, 0, 21, 22
+; CHECK-NEXT:    cmpwi cr2, r4, 512
+; CHECK-NEXT:    lwax r4, r30, r29
+; CHECK-NEXT:    add r4, r4, r29
+; CHECK-NEXT:    mtctr r4
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    bctr
+; CHECK-NEXT:  .LBB0_5: # %bb13
+; CHECK-NEXT:    #
+; CHECK-NEXT:    li r4, 16
+; CHECK-NEXT:    b .LBB0_2
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_6: # %bb22
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_6
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_7: # %bb28
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_7
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_8: # %bb52
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_8
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_9: # %bb17
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_9
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_10: # %bb26
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_10
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_11: # %bb42
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_11
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_12: # %bb54
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_12
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_13: # %bb47
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_13
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_14: # %bb58
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_14
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_15: # %bb24
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_15
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_16: # %bb19
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_16
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_17: # %bb23
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_17
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_18: # %bb60
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_18
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_19: # %bb59
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_19
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_20: # %bb46
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_20
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_21: # %bb49
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_21
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_22: # %bb57
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_22
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_23: # %bb56
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_23
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_24: # %bb20
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_24
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_25: # %bb18
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_25
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_26: # %bb61
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_26
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_27: # %bb55
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_27
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_28: # %bb62
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_28
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_29: # %bb50
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_29
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_30: # %bb48
+; CHECK-NEXT:    #
+; CHECK-NEXT:    b .LBB0_30
+; CHECK-NEXT:  .LBB0_31: # %bb9
+; CHECK-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r29, 56(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    addi r1, r1, 80
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    lwz r12, 8(r1)
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    mtocrf 32, r12
+; CHECK-NEXT:    mtocrf 16, r12
+; CHECK-NEXT:    mtocrf 8, r12
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_32: # %bb29
+; CHECK-NEXT:    lwz r4, 52(r1)
+; CHECK-NEXT:    cmpwi cr4, r3, 0
+; CHECK-NEXT:    setnbc r30, 4*cr2+eq
+; CHECK-NEXT:    # implicit-def: $cr2lt
+; CHECK-NEXT:    mfocrf r3, 32
+; CHECK-NEXT:    cmpwi cr3, r5, 366
+; CHECK-NEXT:    li r29, 0
+; CHECK-NEXT:    rlwimi r3, r4, 24, 8, 8
+; CHECK-NEXT:    mtocrf 32, r3
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_33: # %bb32
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 4, 4*cr2+lt, .LBB0_35
+; CHECK-NEXT:  # %bb.34: # %bb33
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stb r29, 0(r30)
+; CHECK-NEXT:  .LBB0_35: # %bb36
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_33
+; CHECK-NEXT:  # %bb.36: # %bb39
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl call_2@notoc
+; CHECK-NEXT:    b .LBB0_33
+bb:
+  %tmp = load i32, i32* undef, align 8
+  %tmp1 = and i32 %tmp, 16
+  %tmp2 = icmp ne i32 %tmp1, 0
+  %tmp3 = and i32 %tmp, 32
+  %tmp4 = icmp ne i32 %tmp3, 0
+  br label %bb5
+
+bb5:                                              ; preds = %bb63, %bb
+  %tmp6 = phi i32 [ 0, %bb ], [ %tmp64, %bb63 ]
+  %tmp7 = phi i1 [ %tmp4, %bb ], [ undef, %bb63 ]
+  %tmp8 = load i32, i32* undef, align 8
+  br i1 %tmp2, label %bb9, label %bb10
+
+bb9:                                              ; preds = %bb5
+  ret void
+
+bb10:                                             ; preds = %bb5
+  %tmp11 = and i32 %tmp8, 1536
+  %tmp12 = icmp eq i32 %tmp11, 512
+  switch i32 undef, label %bb13 [
+    i32 117, label %bb62
+    i32 40, label %bb63
+    i32 302, label %bb63
+    i32 46, label %bb63
+    i32 320, label %bb16
+    i32 64, label %bb16
+    i32 344, label %bb18
+    i32 88, label %bb19
+    i32 376, label %bb63
+    i32 120, label %bb20
+    i32 47, label %bb21
+    i32 65, label %bb21
+    i32 90, label %bb21
+    i32 97, label %bb21
+    i32 66, label %bb63
+    i32 98, label %bb63
+    i32 72, label %bb63
+    i32 104, label %bb63
+    i32 67, label %bb63
+    i32 99, label %bb23
+    i32 87, label %bb24
+    i32 85, label %bb63
+    i32 371, label %bb25
+    i32 115, label %bb25
+    i32 339, label %bb27
+    i32 118, label %bb27
+    i32 110, label %bb27
+    i32 83, label %bb27
+    i32 374, label %bb29
+    i32 366, label %bb29
+    i32 105, label %bb41
+    i32 361, label %bb41
+    i32 73, label %bb43
+    i32 329, label %bb43
+    i32 106, label %bb46
+    i32 74, label %bb47
+    i32 364, label %bb48
+    i32 108, label %bb49
+    i32 332, label %bb50
+    i32 86, label %bb51
+    i32 78, label %bb51
+    i32 76, label %bb51
+    i32 342, label %bb53
+    i32 334, label %bb53
+    i32 112, label %bb55
+    i32 119, label %bb56
+    i32 80, label %bb63
+    i32 113, label %bb57
+    i32 81, label %bb58
+    i32 102, label %bb59
+    i32 100, label %bb60
+    i32 70, label %bb61
+  ]
+
+bb13:                                             ; preds = %bb10
+  %tmp14 = icmp eq i32 0, 0
+  %tmp15 = select i1 %tmp14, i32 16, i32 undef
+  br label %bb63
+
+bb16:                                             ; preds = %bb10, %bb10
+  br label %bb17
+
+bb17:                                             ; preds = %bb17, %bb16
+  br label %bb17
+
+bb18:                                             ; preds = %bb18, %bb10
+  br label %bb18
+
+bb19:                                             ; preds = %bb19, %bb10
+  br label %bb19
+
+bb20:                                             ; preds = %bb20, %bb10
+  br label %bb20
+
+bb21:                                             ; preds = %bb10, %bb10, %bb10, %bb10
+  br label %bb22
+
+bb22:                                             ; preds = %bb22, %bb21
+  br label %bb22
+
+bb23:                                             ; preds = %bb23, %bb10
+  br label %bb23
+
+bb24:                                             ; preds = %bb24, %bb10
+  br label %bb24
+
+bb25:                                             ; preds = %bb10, %bb10
+  br label %bb26
+
+bb26:                                             ; preds = %bb26, %bb25
+  br label %bb26
+
+bb27:                                             ; preds = %bb10, %bb10, %bb10, %bb10
+  br label %bb28
+
+bb28:                                             ; preds = %bb28, %bb27
+  br label %bb28
+
+bb29:                                             ; preds = %bb10, %bb10
+  %tmp30 = icmp eq i32 %tmp8, 366
+  %tmp31 = icmp eq i32 %tmp6, 0
+  br label %bb32
+
+bb32:                                             ; preds = %bb40, %bb29
+  br i1 %tmp7, label %bb33, label %bb36
+
+bb33:                                             ; preds = %bb32
+  %tmp34 = getelementptr inbounds i8, i8* null, i64 -1
+  %tmp35 = select i1 %tmp12, i8* %tmp34, i8* null
+  store i8 0, i8* %tmp35, align 1
+  br label %bb36
+
+bb36:                                             ; preds = %bb33, %bb32
+  br i1 %tmp30, label %bb37, label %bb38
+
+bb37:                                             ; preds = %bb36
+  store i16 undef, i16* null, align 2
+  br label %bb38
+
+bb38:                                             ; preds = %bb37, %bb36
+  br i1 %tmp31, label %bb39, label %bb40
+
+bb39:                                             ; preds = %bb38
+  call void @call_2()
+  br label %bb40
+
+bb40:                                             ; preds = %bb39, %bb38
+  br label %bb32
+
+bb41:                                             ; preds = %bb10, %bb10
+  br label %bb42
+
+bb42:                                             ; preds = %bb42, %bb41
+  br label %bb42
+
+bb43:                                             ; preds = %bb10, %bb10
+  call void @call_1()
+  %tmp44 = getelementptr inbounds i8, i8* null, i64 -1
+  %tmp45 = select i1 %tmp12, i8* %tmp44, i8* null
+  store i8 0, i8* %tmp45, align 1
+  br label %bb63
+
+bb46:                                             ; preds = %bb46, %bb10
+  br label %bb46
+
+bb47:                                             ; preds = %bb47, %bb10
+  br label %bb47
+
+bb48:                                             ; preds = %bb48, %bb10
+  br label %bb48
+
+bb49:                                             ; preds = %bb49, %bb10
+  br label %bb49
+
+bb50:                                             ; preds = %bb50, %bb10
+  br label %bb50
+
+bb51:                                             ; preds = %bb10, %bb10, %bb10
+  br label %bb52
+
+bb52:                                             ; preds = %bb52, %bb51
+  br label %bb52
+
+bb53:                                             ; preds = %bb10, %bb10
+  br label %bb54
+
+bb54:                                             ; preds = %bb54, %bb53
+  br label %bb54
+
+bb55:                                             ; preds = %bb55, %bb10
+  br label %bb55
+
+bb56:                                             ; preds = %bb56, %bb10
+  br label %bb56
+
+bb57:                                             ; preds = %bb57, %bb10
+  br label %bb57
+
+bb58:                                             ; preds = %bb58, %bb10
+  br label %bb58
+
+bb59:                                             ; preds = %bb59, %bb10
+  br label %bb59
+
+bb60:                                             ; preds = %bb60, %bb10
+  br label %bb60
+
+bb61:                                             ; preds = %bb61, %bb10
+  br label %bb61
+
+bb62:                                             ; preds = %bb62, %bb10
+  br label %bb62
+
+bb63:                                             ; preds = %bb43, %bb13, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10, %bb10
+  %tmp64 = phi i32 [ %tmp15, %bb13 ], [ 0, %bb43 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ], [ 0, %bb10 ]
+  br label %bb5
+}
+
+declare void @call_1() local_unnamed_addr
+
+declare void @call_2() local_unnamed_addr
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
@@ -0,0 +1,169 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
+; This test case tests spilling the CR LT bit on Power10. On Power10, this is
+; achieved by setb %reg, %CRREG (lt bit) -> stw %reg, $FI instead of:
+; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
+
+; Without fine-grained control over clobbering individual CR bits,
+; it is difficult to produce a concise test case that will ensure a specific
+; bit of any CR field is spilled. We need to test the spilling of a CR bit
+; other than the LT bit. Hence this test case is rather complex.
+
+%0 = type { %1 }
+%1 = type { %0*, %0*, %0*, i32 }
+
+@call_1 = external dso_local unnamed_addr global i32, align 4
+declare %0* @call_2() local_unnamed_addr
+declare i32 @call_3() local_unnamed_addr
+declare void @call_4() local_unnamed_addr
+
+define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
+; CHECK-LABEL: P10_Spill_CR_LT:
+; CHECK:         .localentry P10_Spill_CR_LT, 1
+; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    mfcr r12
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    stdu r1, -80(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    .cfi_offset cr2, 8
+; CHECK-NEXT:    .cfi_offset cr3, 8
+; CHECK-NEXT:    .cfi_offset cr4, 8
+; CHECK-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    bl call_2@notoc
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
+; CHECK-NEXT:  # %bb.1: # %bb
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-NEXT:  # %bb.2: # %bb4
+; CHECK-NEXT:    cmpdi cr3, r3, 0
+; CHECK-NEXT:    # implicit-def: $r30
+; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr3+eq
+; CHECK-NEXT:    setnbc r3, 4*cr5+lt
+; CHECK-NEXT:    stw r3, 60(r1)
+; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    cmpwi cr4, r3, 0
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB0_3: # %bb12
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl call_3@notoc
+; CHECK-NEXT:    cmpwi r3, 1
+; CHECK-NEXT:    crnand 4*cr5+lt, eq, 4*cr4+gt
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_8
+; CHECK-NEXT:  # %bb.4: # %bb23
+; CHECK-NEXT:    #
+; CHECK-NEXT:    plwz r3, call_1@PCREL(0), 1
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    bne- cr0, .LBB0_10
+; CHECK-NEXT:  # %bb.5: # %bb30
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 12, 4*cr3+eq, .LBB0_9
+; CHECK-NEXT:  # %bb.6: # %bb32
+; CHECK-NEXT:    #
+; CHECK-NEXT:    rlwinm r30, r30, 0, 24, 22
+; CHECK-NEXT:    andi. r3, r30, 2
+; CHECK-NEXT:    mcrf cr2, cr0
+; CHECK-NEXT:    bl call_4@notoc
+; CHECK-NEXT:    beq+ cr2, .LBB0_3
+; CHECK-NEXT:  # %bb.7: # %bb37
+; CHECK-NEXT:  .LBB0_8: # %bb22
+; CHECK-NEXT:  .LBB0_9: # %bb35
+; CHECK-NEXT:  .LBB0_10: # %bb27
+; CHECK-NEXT:    lwz r4, 60(r1)
+; CHECK-NEXT:    # implicit-def: $cr5lt
+; CHECK-NEXT:    mfocrf r3, 4
+; CHECK-NEXT:    rlwimi r3, r4, 12, 20, 20
+; CHECK-NEXT:    mtocrf 4, r3
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-NEXT:  # %bb.11: # %bb28
+; CHECK-NEXT:  .LBB0_12: # %bb29
+; CHECK-NEXT:  .LBB0_13: # %bb3
+; CHECK-NEXT:  .LBB0_14: # %bb2
+bb:
+  %tmp = tail call %0* @call_2()
+  %tmp1 = icmp ne %0* %tmp, null
+  switch i32 undef, label %bb4 [
+    i32 3, label %bb2
+    i32 2, label %bb3
+  ]
+
+bb2:                                              ; preds = %bb
+  unreachable
+
+bb3:                                              ; preds = %bb
+  unreachable
+
+bb4:                                              ; preds = %bb
+  %tmp5 = load i64, i64* undef, align 8
+  %tmp6 = trunc i64 %tmp5 to i32
+  %tmp7 = add i32 0, %tmp6
+  %tmp8 = icmp sgt i32 %tmp7, 0
+  %tmp9 = icmp eq i8 0, 0
+  %tmp10 = zext i1 %tmp9 to i32
+  %tmp11 = icmp eq %0* %tmp, null
+  br label %bb12
+
+bb12:                                             ; preds = %bb38, %bb4
+  %tmp13 = phi i32 [ %tmp10, %bb4 ], [ undef, %bb38 ]
+  %tmp14 = phi i32 [ undef, %bb4 ], [ %tmp17, %bb38 ]
+  %tmp15 = icmp ne i32 %tmp13, 0
+  %tmp16 = and i32 %tmp14, -257
+  %tmp17 = select i1 %tmp15, i32 %tmp16, i32 undef
+  br label %bb18
+
+bb18:                                             ; preds = %bb12
+  %tmp19 = call zeroext i32 @call_3()
+  %tmp20 = icmp eq i32 %tmp19, 1
+  %tmp21 = and i1 %tmp8, %tmp20
+  br i1 %tmp21, label %bb22, label %bb23
+
+bb22:                                             ; preds = %bb18
+  unreachable
+
+bb23:                                             ; preds = %bb18
+  br label %bb24
+
+bb24:                                             ; preds = %bb23
+  %tmp25 = load i32, i32* @call_1, align 4
+  %tmp26 = icmp eq i32 %tmp25, 0
+  br i1 %tmp26, label %bb30, label %bb27
+
+bb27:                                             ; preds = %bb24
+  br i1 %tmp1, label %bb28, label %bb29
+
+bb28:                                             ; preds = %bb27
+  unreachable
+
+bb29:                                             ; preds = %bb27
+  unreachable
+
+bb30:                                             ; preds = %bb24
+  br label %bb31
+
+bb31:                                             ; preds = %bb30
+  br i1 %tmp11, label %bb35, label %bb32
+
+bb32:                                             ; preds = %bb31
+  %tmp33 = and i32 %tmp17, 2
+  %tmp34 = icmp eq i32 %tmp33, 0
+  call void @call_4()
+  br label %bb36
+
+bb35:                                             ; preds = %bb31
+  unreachable
+
+bb36:                                             ; preds = %bb32
+  br i1 %tmp34, label %bb38, label %bb37
+
+bb37:                                             ; preds = %bb36
+  unreachable
+
+bb38:                                             ; preds = %bb36
+  br label %bb12
+}
+
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -0,0 +1,283 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:     FileCheck %s
+
+; This test case tests spilling the CR UN bit on Power10. On Power10, this is
+; achieved by setb %reg, %CRREG (un bit) -> stw %reg, $FI instead of:
+; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
+
+; Without fine-grained control over clobbering individual CR bits,
+; it is difficult to produce a concise test case that will ensure a specific
+; bit of any CR field is spilled. We need to test the spilling of a CR bit
+; other than the LT bit. Hence this test case is rather complex.
+
+%0 = type { i32, [768 x i8], [768 x i8], [1024 x i8], [768 x i8], [768 x i8], [768 x i8], [768 x i8], [768 x i8], [1024 x i8], [1024 x i8], i32, i16, i16, i16, i16, i16, i16, i32, i32, i32, i16, i16, i32, i32, i32, i32, i32, i32, i32, i16, i16, i16, i16, [64 x i8], i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, float, float, i32, i16, i16, float, i16, i16, i16, i16}
+%1 = type opaque
+%2 = type { i8* }
+%3 = type { %3*, %3*, %4* (i8*)*, %2, i32, %2, %2*, i8*, double*, float*, i8*, i8*, %4* }
+%4 = type { %4*, %4*, %4*, i32, i32, i32, i32, i32, i8*, [3 x float], i8, [64 x i8] }
+
+@global_1 = external dso_local unnamed_addr constant [1 x i8], align 1
+@global_2 = external local_unnamed_addr global %0, align 8
+@global_3 = external local_unnamed_addr global i8* (i64, i8*)*, align 8
+@global_4 = external dso_local unnamed_addr constant [14 x i8], align 1
+
+declare i8 @call_1(%1*) local_unnamed_addr
+declare i32 @call_2(%2*, %1*) local_unnamed_addr
+declare i32 @call_3(%2*, %1*) local_unnamed_addr
+declare %3* @call_4(%4*, i32, i32, i32, i32, i32, i16, i16, %2*, %1*, i32, float, float, float, float, i8*) local_unnamed_addr
+declare i32 @call_5(i8*) local_unnamed_addr
+declare i8 @call_6(%1*, i32) local_unnamed_addr
+
+define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unnamed_addr {
+; CHECK-LABEL: P10_Spill_CR_UN:
+; CHECK:         .localentry P10_Spill_CR_UN, 1
+; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    mfcr r12
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    stdu r1, -224(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 224
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r27, -40
+; CHECK-NEXT:    .cfi_offset r28, -32
+; CHECK-NEXT:    .cfi_offset r29, -24
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    .cfi_offset cr2, 8
+; CHECK-NEXT:    .cfi_offset cr3, 8
+; CHECK-NEXT:    .cfi_offset cr4, 8
+; CHECK-NEXT:    std r29, 200(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, 208(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    mr r29, r3
+; CHECK-NEXT:    mr r3, r4
+; CHECK-NEXT:    mr r30, r4
+; CHECK-NEXT:    std r27, 184(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r28, 192(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    mr r28, r5
+; CHECK-NEXT:    bl call_1@notoc
+; CHECK-NEXT:    cmpwi r3, 0
+; CHECK-NEXT:    mr r3, r29
+; CHECK-NEXT:    mr r4, r30
+; CHECK-NEXT:    crnot 4*cr2+eq, eq
+; CHECK-NEXT:    bl call_2@notoc
+; CHECK-NEXT:    mr r27, r3
+; CHECK-NEXT:    srwi r3, r28, 4
+; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    crmove 4*cr2+gt, gt
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %bb9
+; CHECK-NEXT:    mr r3, r29
+; CHECK-NEXT:    mr r4, r30
+; CHECK-NEXT:    bl call_3@notoc
+; CHECK-NEXT:  .LBB0_2: # %bb12
+; CHECK-NEXT:    srwi r3, r28, 7
+; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    crmove 4*cr2+un, gt
+; CHECK-NEXT:    bc 12, 4*cr2+eq, .LBB0_7
+; CHECK-NEXT:  # %bb.3: # %bb37
+; CHECK-NEXT:    lwz r28, 0(r3)
+; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %bb37
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
+; CHECK-NEXT:  .LBB0_5: # %bb42
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    paddi r3, 0, global_1@PCREL, 1
+; CHECK-NEXT:    cmpwi r28, 0
+; CHECK-NEXT:    isel r3, r3, r4, 4*cr2+gt
+; CHECK-NEXT:    crnot 4*cr2+lt, eq
+; CHECK-NEXT:    bl call_5@notoc
+; CHECK-NEXT:    pld r3, global_2@got@pcrel(0), 1
+; CHECK-NEXT:    addi r3, r3, 8682
+; CHECK-NEXT:    lxsihzx v2, 0, r3
+; CHECK-NEXT:    vextsh2d v2, v2
+; CHECK-NEXT:    xscvsxdsp f0, v2
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_12
+; CHECK-NEXT:  # %bb.6: # %bb42
+; CHECK-NEXT:    xxspltidp vs1, 1069547520
+; CHECK-NEXT:    b .LBB0_13
+; CHECK-NEXT:  .LBB0_7: # %bb19
+; CHECK-NEXT:    setnbc r3, 4*cr2+un
+; CHECK-NEXT:    paddi r4, 0, global_4@PCREL, 1
+; CHECK-NEXT:    stw r3, 176(r1)
+; CHECK-NEXT:    pld r3, global_3@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel:
+; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-NEXT:    ld r12, 0(r3)
+; CHECK-NEXT:    mtctr r12
+; CHECK-NEXT:    bctrl
+; CHECK-NEXT:    cmpdi cr4, r3, 0
+; CHECK-NEXT:    andi. r3, r28, 4
+; CHECK-NEXT:    cmpwi cr2, r27, 0
+; CHECK-NEXT:    mcrf cr3, cr0
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_8: # %bb27
+; CHECK-NEXT:    #
+; CHECK-NEXT:    mr r3, r30
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    bl call_6@notoc
+; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_18
+; CHECK-NEXT:  # %bb.9: # %bb31
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 4, 4*cr3+eq, .LBB0_18
+; CHECK-NEXT:  # %bb.10: # %bb33
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 4, 4*cr2+eq, .LBB0_8
+; CHECK-NEXT:  # %bb.11: # %bb36
+; CHECK-NEXT:    stb r3, 181(r1)
+; CHECK-NEXT:    # implicit-def: $cr2un
+; CHECK-NEXT:    mfocrf r3, 32
+; CHECK-NEXT:    lwz r4, 176(r1)
+; CHECK-NEXT:    rlwimi r3, r4, 21, 11, 11
+; CHECK-NEXT:    mtocrf 32, r3
+; CHECK-NEXT:    b .LBB0_16
+; CHECK-NEXT:  .LBB0_12:
+; CHECK-NEXT:    xxspltidp vs1, 1071644672
+; CHECK-NEXT:  .LBB0_13: # %bb42
+; CHECK-NEXT:    xsmulsp f0, f1, f0
+; CHECK-NEXT:    xscvdpsxws f0, f0
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    b .LBB0_15
+; CHECK-NEXT:  .LBB0_14: # %bb41
+; CHECK-NEXT:    # implicit-def: $r3
+; CHECK-NEXT:  .LBB0_15: # %bb50
+; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    xxspltidp vs3, -1082130432
+; CHECK-NEXT:    extsh r9, r3
+; CHECK-NEXT:    extsw r6, r28
+; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    std r30, 104(r1)
+; CHECK-NEXT:    std r29, 96(r1)
+; CHECK-NEXT:    li r7, 0
+; CHECK-NEXT:    li r8, 0
+; CHECK-NEXT:    li r10, 0
+; CHECK-NEXT:    fmr f4, f3
+; CHECK-NEXT:    xxlxor f1, f1, f1
+; CHECK-NEXT:    std r4, 152(r1)
+; CHECK-NEXT:    li r4, -1
+; CHECK-NEXT:    std r4, 112(r1)
+; CHECK-NEXT:    li r4, 1024
+; CHECK-NEXT:    bl call_4@notoc
+; CHECK-NEXT:  .LBB0_16: # %bb54
+; CHECK-NEXT:    bc 12, 4*cr2+un, .LBB0_19
+; CHECK-NEXT:  # %bb.17: # %bb56
+; CHECK-NEXT:    ld r30, 208(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r29, 200(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r28, 192(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r27, 184(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    addi r1, r1, 224
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    lwz r12, 8(r1)
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    mtocrf 32, r12
+; CHECK-NEXT:    mtocrf 16, r12
+; CHECK-NEXT:    mtocrf 8, r12
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_18: # %bb30
+; CHECK-NEXT:    stb r3, 181(r1)
+; CHECK-NEXT:  .LBB0_19: # %bb55
+bb:
+  %tmp = alloca [3 x i8], align 1
+  %tmp3 = tail call zeroext i8 @call_1(%1* %arg1)
+  %tmp4 = icmp ne i8 %tmp3, 0
+  %tmp5 = tail call signext i32 @call_2(%2* %arg, %1* %arg1)
+  %tmp6 = and i32 %arg2, 16
+  %tmp7 = icmp ne i32 %tmp6, 0
+  br label %bb8
+
+bb8:                                              ; preds = %bb
+  br i1 undef, label %bb9, label %bb11
+
+bb9:                                              ; preds = %bb8
+  %tmp10 = call signext i32 @call_3(%2* %arg, %1* %arg1)
+  br label %bb12
+
+bb11:                                             ; preds = %bb8
+  br label %bb12
+
+bb12:                                             ; preds = %bb11, %bb9
+  %tmp13 = and i32 %arg2, 4
+  %tmp14 = and i32 %arg2, 128
+  %tmp15 = icmp ne i32 %tmp14, 0
+  br label %bb16
+
+bb16:                                             ; preds = %bb12
+  %tmp17 = xor i1 %tmp4, true
+  %tmp18 = or i1 false, %tmp17
+  br i1 %tmp18, label %bb37, label %bb19
+
+bb19:                                             ; preds = %bb16
+  %tmp20 = getelementptr inbounds [3 x i8], [3 x i8]* %tmp, i64 0, i64 0
+  %tmp21 = load i8* (i64, i8*)*, i8* (i64, i8*)** @global_3, align 8
+  %tmp22 = call i8* %tmp21(i64 undef, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @global_4, i64 0, i64 0))
+  %tmp23 = bitcast i8* %tmp22 to i32*
+  %tmp24 = icmp eq i32* %tmp23, null
+  %tmp25 = icmp eq i32 %tmp13, 0
+  %tmp26 = zext i32 %tmp5 to i64
+  br label %bb27
+
+bb27:                                             ; preds = %bb34, %bb19
+  %tmp28 = call zeroext i8 @call_6(%1* %arg1, i32 signext undef)
+  store i8 %tmp28, i8* %tmp20, align 1
+  br label %bb29
+
+bb29:                                             ; preds = %bb27
+  br i1 %tmp24, label %bb31, label %bb30
+
+bb30:                                             ; preds = %bb29
+  unreachable
+
+bb31:                                             ; preds = %bb29
+  br i1 %tmp25, label %bb33, label %bb32
+
+bb32:                                             ; preds = %bb31
+  unreachable
+
+bb33:                                             ; preds = %bb31
+  br label %bb34
+
+bb34:                                             ; preds = %bb33
+  %tmp35 = icmp eq i64 0, %tmp26
+  br i1 %tmp35, label %bb36, label %bb27
+
+bb36:                                             ; preds = %bb34
+  br label %bb54
+
+bb37:                                             ; preds = %bb16
+  %tmp38 = load i32, i32* undef, align 8
+  %tmp39 = select i1 %tmp7, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @global_1, i64 0, i64 0), i8* null
+  %tmp40 = icmp ne i32 %tmp38, 0
+  switch i32 undef, label %bb41 [
+    i32 1, label %bb42
+    i32 4, label %bb42
+  ]
+
+bb41:                                             ; preds = %bb37
+  br label %bb50
+
+bb42:                                             ; preds = %bb37, %bb37
+  %tmp43 = call signext i32 @call_5(i8* %tmp39)
+  %tmp44 = load i16, i16* getelementptr inbounds (%0, %0* @global_2, i64 0, i32 81), align 4
+  %tmp45 = sitofp i16 %tmp44 to float
+  %tmp46 = select i1 %tmp40, float 1.750000e+00, float 1.500000e+00
+  %tmp47 = fmul fast float %tmp46, %tmp45
+  %tmp48 = fadd fast float %tmp47, 0.000000e+00
+  %tmp49 = fptosi float %tmp48 to i32
+  br label %bb50
+
+bb50:                                             ; preds = %bb42, %bb41
+  %tmp51 = phi i32 [ %tmp49, %bb42 ], [ undef, %bb41 ]
+  %tmp52 = trunc i32 %tmp51 to i16
+  %tmp53 = call %3* @call_4(%4* nonnull undef, i32 signext 1024, i32 signext 0, i32 signext %tmp38, i32 signext 0, i32 signext 0, i16 signext %tmp52, i16 signext undef, %2* %arg, %1* %arg1, i32 signext -1, float 0.000000e+00, float undef, float -1.000000e+00, float -1.000000e+00, i8* null)
+  br label %bb54
+
+bb54:                                             ; preds = %bb50, %bb36
+  br i1 %tmp15, label %bb55, label %bb56
+
+bb55:                                             ; preds = %bb54
+  unreachable
+
+bb56:                                             ; preds = %bb54
+  ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -7,6 +7,12 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-P10
 
 %struct.tree_common = type { i8, [3 x i8] }
 declare signext i32 @fn2(...) local_unnamed_addr #1
@@ -56,6 +62,14 @@
 ; LE-NEXT:    ld r0, 16(r1)
 ; LE-NEXT:    mtlr r0
 ; LE-NEXT:    blr
+
+; CHECK-P10-LABEL: testCompare1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-DAG:     lbz r3, 0(r3)
+; CHECK-P10-DAG:     clrlwi r3, r3, 31
+; CHECK-P10-DAG:     clrlwi r4, r4, 31
+; CHECK-P10:         cmplw r4, r3
+; CHECK-P10-NEXT:    setbc r3, gt
 entry:
   %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
   %bf.clear = and i8 %bf.load, 1
@@ -79,6 +93,14 @@
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
+
+; CHECK-P10-LABEL: testCompare2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 31
+; CHECK-P10-NEXT:    clrlwi r4, r4, 31
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setbc r3, gt
+; CHECK-P10-NEXT:    blr
 entry:
   %and = and i32 %a, 1
   %and1 = and i32 %b, 1
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -5,6 +5,14 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-P10 --implicit-check-not cmpw \
+; RUN:   --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-P10 --implicit-check-not cmpw \
+; RUN:   --implicit-check-not cmpd --implicit-check-not cmpl
 
 define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: test:
@@ -17,6 +25,14 @@
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
+;
+; CHECK-P10-LABEL: test:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 31
+; CHECK-P10-NEXT:    clrlwi r4, r4, 31
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setbcr r3, gt
+; CHECK-P10-NEXT:    blr
 entry:
   %0 = and i8 %a, 1
   %1 = and i8 %b, 1
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -7,6 +7,12 @@
 ; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
 ; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
 ; RUN:  --check-prefixes=CHECK,LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-P10
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
+; RUN:     -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
+; RUN:     FileCheck %s --check-prefix=CHECK-P10
 
 %struct.tree_common = type { i8, [3 x i8] }
 declare signext i32 @fn2(...) local_unnamed_addr #1
@@ -56,6 +62,14 @@
 ; LE-NEXT:    ld r0, 16(r1)
 ; LE-NEXT:    mtlr r0
 ; LE-NEXT:    blr
+
+; CHECK-P10-LABEL: testCompare1:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-DAG:     lbz r3, 0(r3)
+; CHECK-P10-DAG:     clrlwi r3, r3, 31
+; CHECK-P10-DAG:     clrlwi r4, r4, 31
+; CHECK-P10:         cmplw r4, r3
+; CHECK-P10-NEXT:    setbc r3, lt
 entry:
   %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
   %bf.clear = and i8 %bf.load, 1
@@ -79,6 +93,14 @@
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    rldicl r3, r3, 1, 63
 ; CHECK-NEXT:    blr
+
+; CHECK-P10-LABEL: testCompare2:
+; CHECK-P10:       # %bb.0: # %entry
+; CHECK-P10-NEXT:    clrlwi r3, r3, 31
+; CHECK-P10-NEXT:    clrlwi r4, r4, 31
+; CHECK-P10-NEXT:    cmplw r3, r4
+; CHECK-P10-NEXT:    setbc r3, lt
+; CHECK-P10-NEXT:    blr
 entry:
   %and = and i32 %a, 1
   %and1 = and i32 %b, 1