diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2255,6 +2255,15 @@
                          return isa<Instruction>(U) &&
                                 cast<Instruction>(U)->getParent() == BB;
                        }) > 2;
+
+      // FIXME: How to obtain number of available registers ?
+      // Hardcoded for now.
+      unsigned nRegs = 7;
+
+      // Check that there is at least one register available for holding
+      // function's address
+      if (PreferIndirect && Subtarget->isThumb1Only())
+        PreferIndirect = MF.getFunction().arg_size() + Outs.size() < nRegs - 1;
     }
   }
   if (isTailCall) {
diff --git a/llvm/test/CodeGen/ARM/minsize-call-cse-2.ll b/llvm/test/CodeGen/ARM/minsize-call-cse-2.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/minsize-call-cse-2.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv6m-arm-none-eabi"
+
+; CHECK-LABEL: f:
+; CHECK: bl g
+; CHECK: bl g
+; CHECK: bl g
+; CHECK: bl g
+define void @f(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a) optsize minsize  {
+entry:
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  ret void
+}
+
+declare void @g(i32*,i32,i32,i32,i32)