Index: mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
===================================================================
--- mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
+++ mlir/include/mlir/Dialect/SPIRV/SPIRVCastOps.td
@@ -186,6 +186,8 @@
     %3 = spv.ConvertSToF %2 : vector<3xi32> to vector<3xf32>
     ```
   }];
+
+  let verifier = [{ return verifyCastOp(this->getOperation(), false, true); }];
 }
 
 // -----
Index: mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
===================================================================
--- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
+++ mlir/lib/Dialect/SPIRV/SPIRVOps.cpp
@@ -305,7 +305,8 @@
 }
 
 static LogicalResult verifyCastOp(Operation *op,
-                                  bool requireSameBitWidth = true) {
+                                  bool requireSameBitWidth = true,
+                                  bool skipBitCheck = false) {
   Type operandType = op->getOperand(0).getType();
   Type resultType = op->getResult(0).getType();
 
@@ -326,7 +327,7 @@
   auto resultTypeBitWidth = resultType.getIntOrFloatBitWidth();
   auto isSameBitWidth = operandTypeBitWidth == resultTypeBitWidth;
 
-  if (requireSameBitWidth) {
+  if (requireSameBitWidth && !skipBitCheck) {
     if (!isSameBitWidth) {
       return op->emitOpError(
                  "expected the same bit widths for operand type and result "
@@ -336,7 +337,7 @@
     return success();
   }
 
-  if (isSameBitWidth) {
+  if (isSameBitWidth && !skipBitCheck) {
     return op->emitOpError(
                "expected the different bit widths for operand type and result "
                "type, but provided ")