Index: llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1266,7 +1266,11 @@
       } else
         GepOffsetReg = IdxReg;
 
-      BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
+      if (isa<ConstantPointerNull>(Op0))
+        BaseReg = MIRBuilder.buildIntToPtr(PtrTy, GepOffsetReg).getReg(0);
+      else
+        BaseReg =
+            MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
     }
   }
 
Index: llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
+++ llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
@@ -9,8 +9,8 @@
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
   ; CHECK:   [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
-  ; CHECK:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[C]], [[COPY]](s64)
-  ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
+  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
   ; CHECK:   $x0 = COPY [[COPY1]](p0)
   ; CHECK:   RET_ReallyLR implicit $x0
   %tmp = getelementptr i8, i8* null, i64 %arg
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-add-nullptr.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-add-nullptr.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -march=amdgcn -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+
+define amdgpu_cs i32 @_amdgpu_cs_main(i32 inreg %arg) {
+  ; CHECK-LABEL: name: _amdgpu_cs_main
+  ; CHECK: bb.1..entry:
+  ; CHECK:   liveins: $sgpr0
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+  ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[C]]
+  ; CHECK:   [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[MUL]](s32)
+  ; CHECK:   [[COPY1:%[0-9]+]]:_(p6) = COPY [[INTTOPTR]](p6)
+  ; CHECK:   [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p6)
+  ; CHECK:   [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)
+  ; CHECK:   $sgpr0 = COPY [[INT]](s32)
+  ; CHECK:   SI_RETURN_TO_EPILOG implicit $sgpr0
+.entry:
+  %ptr = getelementptr {i32, i32}, {i32, i32} addrspace(6)* null, i32 %arg, i32 0
+  %iptr = ptrtoint i32 addrspace(6)* %ptr to i32
+  ret i32 %iptr
+}