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Differential D86794

[PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and xvcvbf16spn
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Authored by amyk on Aug 28 2020, 10:08 AM.

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Reviewers
nemanjai
lei
bsaleil
power-llvm-team
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rGca2227c1b3f5: [PowerPC] Implement instruction definitions/MC Tests for xvcvspbf16 and…
Summary

This patch adds the td instruction definitions of the xvcvspbf16 and xvcvbf16spn instructions,
along with their respective MC tests.

Diff Detail

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
5 lines
test/
MC/
Disassembler/
PowerPC/
6 lines
PowerPC/
6 lines

Diff 289191

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Show First 20 Lines • Show All 1,294 Lines • ▼ Show 20 Lineslet Predicates = [IsISA3_1] in {
def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>; def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>; def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>; def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>; def XSCVSQQP : X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
} }
let Predicates = [IsISA3_1, HasVSX] in {
def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>;
def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>;
}
//---------------------------- Anonymous Patterns ----------------------------// //---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in { let Predicates = [IsISA3_1] in {
// Exploit the vector multiply high instructions using intrinsics. // Exploit the vector multiply high instructions using intrinsics.
def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)), def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
(v4i32 (VMULHSW $vA, $vB))>; (v4i32 (VMULHSW $vA, $vB))>;
def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)), def : Pat<(v4i32 (int_ppc_altivec_vmulhuw v4i32:$vA, v4i32:$vB)),
(v4i32 (VMULHUW $vA, $vB))>; (v4i32 (VMULHUW $vA, $vB))>;
def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)), def : Pat<(v2i64 (int_ppc_altivec_vmulhsd v2i64:$vA, v2i64:$vB)),
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

Show First 20 Lines • Show All 536 Lines • ▼ Show 20 Lines
# CHECK: vstribl. 2, 2 # CHECK: vstribl. 2, 2
0x10 0x40 0x14 0x0d 0x10 0x40 0x14 0x0d
# CHECK: vstrihr. 2, 2 # CHECK: vstrihr. 2, 2
0x10 0x43 0x14 0x0d 0x10 0x43 0x14 0x0d
# CHECK: vstrihl. 2, 2 # CHECK: vstrihl. 2, 2
0x10 0x42 0x14 0x0d 0x10 0x42 0x14 0x0d
# CHECK: xvcvspbf16 33, 34
0xf0 0x31 0x17 0x6f
# CHECK: xvcvbf16spn 33, 34
0xf0 0x30 0x17 0x6f

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
# CHECK-LE: vstribl. 2, 2 # encoding: [0x0d,0x14,0x40,0x10] # CHECK-LE: vstribl. 2, 2 # encoding: [0x0d,0x14,0x40,0x10]
vstribl. 2, 2 vstribl. 2, 2
# CHECK-BE: vstrihr. 2, 2 # encoding: [0x10,0x43,0x14,0x0d] # CHECK-BE: vstrihr. 2, 2 # encoding: [0x10,0x43,0x14,0x0d]
# CHECK-LE: vstrihr. 2, 2 # encoding: [0x0d,0x14,0x43,0x10] # CHECK-LE: vstrihr. 2, 2 # encoding: [0x0d,0x14,0x43,0x10]
vstrihr. 2, 2 vstrihr. 2, 2
# CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d] # CHECK-BE: vstrihl. 2, 2 # encoding: [0x10,0x42,0x14,0x0d]
# CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10] # CHECK-LE: vstrihl. 2, 2 # encoding: [0x0d,0x14,0x42,0x10]
vstrihl. 2, 2 vstrihl. 2, 2
# CHECK-BE: xvcvspbf16 33, 34 # encoding: [0xf0,0x31,0x17,0x6f]
# CHECK-LE: xvcvspbf16 33, 34 # encoding: [0x6f,0x17,0x31,0xf0]
xvcvspbf16 33, 34
# CHECK-BE: xvcvbf16spn 33, 34 # encoding: [0xf0,0x30,0x17,0x6f]
# CHECK-LE: xvcvbf16spn 33, 34 # encoding: [0x6f,0x17,0x30,0xf0]
xvcvbf16spn 33, 34