diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10536,13 +10536,16 @@
                                     N0.getValueType());
     }
 
-    // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
+    // zext(setcc x,y,cc) -> zext(select x, y, true, false, cc)
     SDLoc DL(N);
+    EVT N0VT = N0.getValueType();
+    EVT N00VT = N0.getOperand(0).getValueType();
     if (SDValue SCC = SimplifySelectCC(
-            DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
-            DAG.getConstant(0, DL, VT),
+            DL, N0.getOperand(0), N0.getOperand(1),
+            DAG.getBoolConstant(true, DL, N0VT, N00VT),
+            DAG.getBoolConstant(false, DL, N0VT, N00VT),
             cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
-      return SCC;
+      return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, SCC);
   }
 
   // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -310,18 +310,10 @@
   ret i1 %res
 }
 
-;------------------------------------------------------------------------------;
-; A few negative tests
-;------------------------------------------------------------------------------;
-
-define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #24
-; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    lsr w8, w8, w1
-; CHECK-NEXT:    tst w8, w0
-; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -316,20 +316,14 @@
   ret i1 %res
 }
 
-;------------------------------------------------------------------------------;
-; A few negative tests
-;------------------------------------------------------------------------------;
-
-define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; CHECK-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
+; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #24
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    lsl w8, w8, w1
 ; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    sxtb w8, w8
-; CHECK-NEXT:    cmp w8, #0 // =0
-; CHECK-NEXT:    cset w0, lt
+; CHECK-NEXT:    ubfx w0, w8, #7, #1
 ; CHECK-NEXT:    ret
   %t0 = shl i8 24, %y
   %t1 = and i8 %t0, %x
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
@@ -1489,7 +1489,7 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -1510,7 +1510,7 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -1619,8 +1619,8 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -1644,8 +1644,8 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -1796,7 +1796,7 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -1817,7 +1817,7 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -1922,8 +1922,8 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -1943,8 +1943,8 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -2093,7 +2093,7 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -2114,7 +2114,7 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -2223,8 +2223,8 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -2248,8 +2248,8 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -2400,7 +2400,7 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __gekf2
 ; P8-NEXT:    nop
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -2421,7 +2421,7 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __gekf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
@@ -2526,8 +2526,8 @@
 ; P8-NEXT:    stdu r1, -112(r1)
 ; P8-NEXT:    bl __ltkf2
 ; P8-NEXT:    nop
-; P8-NEXT:    not r3, r3
-; P8-NEXT:    srwi r3, r3, 31
+; P8-NEXT:    rlwinm r3, r3, 1, 31, 31
+; P8-NEXT:    xori r3, r3, 1
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -2547,8 +2547,8 @@
 ; NOVSX-NEXT:    stdu r1, -32(r1)
 ; NOVSX-NEXT:    bl __ltkf2
 ; NOVSX-NEXT:    nop
-; NOVSX-NEXT:    not r3, r3
-; NOVSX-NEXT:    srwi r3, r3, 31
+; NOVSX-NEXT:    rlwinm r3, r3, 1, 31, 31
+; NOVSX-NEXT:    xori r3, r3, 1
 ; NOVSX-NEXT:    addi r1, r1, 32
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    mtlr r0
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -18,8 +18,8 @@
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
@@ -46,7 +46,7 @@
 ; CHECK-LABEL: all_sign_bits_set:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
@@ -72,7 +72,7 @@
 ; CHECK-LABEL: any_sign_bits_set:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp slt i32 %P, 0
   %b = icmp slt i32 %Q, 0
@@ -100,8 +100,8 @@
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
--- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -6,8 +6,8 @@
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
@@ -45,10 +45,9 @@
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 3, -1
-; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
@@ -97,10 +96,9 @@
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 3, -1
-; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    iselgt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    xori 3, 3, 1
+; CHECK-NEXT:    subfic 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
@@ -112,7 +110,7 @@
 define i32 @zext_ifneg(i32 %x) {
 ; CHECK-LABEL: zext_ifneg:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    srwi 3, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = zext i1 %c to i32
@@ -134,10 +132,8 @@
 define i32 @sel_ifneg_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_tval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 41
-; CHECK-NEXT:    cmpwi 3, 0
-; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isellt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    addi 3, 3, 41
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 42, i32 41
@@ -169,10 +165,8 @@
 define i32 @sel_ifneg_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_fval_bigger:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 42
-; CHECK-NEXT:    cmpwi 3, 0
-; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isellt 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 1, 31, 31
+; CHECK-NEXT:    subfic 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 41, i32 42