diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14094,8 +14094,7 @@
   EVT Op1VT = N->getOperand(1).getValueType();
   EVT ResVT = Val.getValueType();
 
-  // Floating point types smaller than 32 bits are not legal on Power.
-  if (ResVT.getScalarSizeInBits() < 32)
+  if (!isTypeLegal(ResVT))
     return SDValue();
 
   // Only perform combine for conversion to i64/i32 or power9 i16/i8.
diff --git a/llvm/test/CodeGen/PowerPC/store_fptoi.ll b/llvm/test/CodeGen/PowerPC/store_fptoi.ll
--- a/llvm/test/CodeGen/PowerPC/store_fptoi.ll
+++ b/llvm/test/CodeGen/PowerPC/store_fptoi.ll
@@ -7,6 +7,82 @@
 ; Tests for store of fp_to_sint converstions
 ; ==========================================
 
+; Function Attrs: norecurse nounwind
+define void @qpConv2sdw(fp128* nocapture readonly %a, i64* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i64
+  store i64 %conv, i64* %b, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2sdw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpsdz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsd [[CONV]], 0(4)
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2sdw
+; CHECK-PWR8: bl __fixkfdi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sw(fp128* nocapture readonly %a, i32* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptosi fp128 %0 to i32
+  store i32 %conv, i32* %b, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2sw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpswz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2sw
+; CHECK-PWR8: bl __fixkfsi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2udw(fp128* nocapture readonly %a, i64* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i64
+  store i64 %conv, i64* %b, align 8
+  ret void
+
+; CHECK-LABEL: qpConv2udw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpudz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsd [[CONV]], 0(4)
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2udw
+; CHECK-PWR8: bl __fixunskfdi
+; CHECK-PWR8: blr
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2uw(fp128* nocapture readonly %a, i32* nocapture %b) {
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptoui fp128 %0 to i32
+  store i32 %conv, i32* %b, align 4
+  ret void
+
+; CHECK-LABEL: qpConv2uw
+; CHECK: lxv [[LD:[0-9]+]], 0(3)
+; CHECK-NEXT: xscvqpuwz [[CONV:[0-9]+]], [[LD]]
+; CHECK-NEXT: stxsiwx [[CONV]], 0, 4
+; CHECK-NEXT: blr
+
+; CHECK-PWR8-LABEL: qpConv2uw
+; CHECK-PWR8: bl __fixunskfsi
+; CHECK-PWR8: blr
+}
+
 ; Function Attrs: norecurse nounwind
 define void @dpConv2sdw(double* nocapture readonly %a, i64* nocapture %b) {
 entry: