Index: llvm/lib/Target/AMDGPU/AMDGPUGISel.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -309,8 +309,10 @@ def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, GISDNodeXFormEquiv; -def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, +def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastFPImm32">, GISDNodeXFormEquiv; +def gi_bitcast_fpimm_to_i64 : GICustomOperandRenderer<"renderBitcastFPImm64">, + GISDNodeXFormEquiv; def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">, GISDNodeXFormEquiv; Index: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -283,8 +283,17 @@ void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; - void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI, - int OpIdx) const; + void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const; + + void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderBitcastFPImm(MIB, MI, OpIdx); + } + void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx) const { + renderBitcastFPImm(MIB, MI, OpIdx); + } void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const; Index: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -2070,10 +2070,18 @@ } bool AMDGPUInstructionSelector::selectG_CONSTANT(MachineInstr &I) const { + if (selectImpl(I, *CoverageInfo)) + return true; + + // FIXME: Relying on manual selection for 64-bit case, and pointer typed + // constants. MachineBasicBlock *BB = I.getParent(); MachineOperand &ImmOp = I.getOperand(1); Register DstReg = I.getOperand(0).getReg(); - unsigned Size = MRI->getType(DstReg).getSizeInBits(); + LLT Ty = MRI->getType(DstReg); + unsigned Size = Ty.getSizeInBits(); + assert((Size == 64 || Ty.isPointer()) && + "patterns should have selected this"); // The AMDGPU backend only supports Imm operands and not CImm or FPImm. if (ImmOp.isFPImm()) { @@ -2087,19 +2095,7 @@ const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); const bool IsSgpr = DstRB->getID() == AMDGPU::SGPRRegBankID; - - unsigned Opcode; - if (DstRB->getID() == AMDGPU::VCCRegBankID) { - Opcode = STI.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; - } else { - Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; - - // We should never produce s1 values on banks other than VCC. If the user of - // this already constrained the register, we may incorrectly think it's VCC - // if it wasn't originally. - if (Size == 1) - return false; - } + unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; if (Size != 64) { I.setDesc(TII.get(Opcode)); @@ -2108,7 +2104,6 @@ } const DebugLoc &DL = I.getDebugLoc(); - APInt Imm(Size, I.getOperand(1).getImm()); MachineInstr *ResInst; @@ -3994,18 +3989,12 @@ MIB.addImm(-MI.getOperand(1).getCImm()->getSExtValue()); } -void AMDGPUInstructionSelector::renderBitcastImm(MachineInstrBuilder &MIB, - const MachineInstr &MI, - int OpIdx) const { - assert(OpIdx == -1); - +void AMDGPUInstructionSelector::renderBitcastFPImm(MachineInstrBuilder &MIB, + const MachineInstr &MI, + int OpIdx) const { const MachineOperand &Op = MI.getOperand(1); - if (MI.getOpcode() == TargetOpcode::G_FCONSTANT) - MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); - else { - assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); - MIB.addImm(Op.getCImm()->getSExtValue()); - } + assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1); + MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue()); } void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB, Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -756,7 +756,9 @@ class VGPRImm : PatLeaf; +}]> { + let GISelPredicateCode = [{return true;}]; +} def NegateImm : SDNodeXFormgetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32); Index: llvm/lib/Target/AMDGPU/SIInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/SIInstructions.td +++ llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1431,6 +1431,12 @@ /********** Immediate Patterns **********/ /********** ================== **********/ +def : GCNPat < + (i32 imm:$imm), + (S_MOV_B32 imm:$imm) +>; + +// FIXME: Remove VGPRImm def : GCNPat < (VGPRImm<(i32 imm)>:$imm), (V_MOV_B32_e32 imm:$imm) @@ -1441,11 +1447,6 @@ (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) >; -def : GCNPat < - (i32 imm:$imm), - (S_MOV_B32 imm:$imm) ->; - def : GCNPat < (VGPRImm<(SIlds tglobaladdr:$ga)>), (V_MOV_B32_e32 $ga) @@ -1464,16 +1465,31 @@ (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm))) >; +def : GCNPat < + (VGPRImm<(i16 imm)>:$imm), + (V_MOV_B32_e32 imm:$imm) +>; + def : GCNPat < (f32 fpimm:$imm), (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) >; +def : GCNPat < + (f32 fpimm:$imm), + (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) +>; + def : GCNPat < (f16 fpimm:$imm), (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm))) >; +def : GCNPat < + (f16 fpimm:$imm), + (V_MOV_B32_e32 (i32 (bitcast_fpimm_to_i32 $imm))) +>; + def : GCNPat < (p5 frameindex:$fi), (V_MOV_B32_e32 (p5 (frameindex_to_targetframeindex $fi))) @@ -1489,28 +1505,22 @@ (S_MOV_B64 InlineImm64:$imm) >; -// XXX - Should this use a s_cmp to set SCC? +def : GCNPat < + (f64 InlineImmFP64:$imm), + (S_MOV_B64 (i64 (bitcast_fpimm_to_i64 $imm))) +>; // Set to sign-extended 64-bit value (true = -1, false = 0) -def : GCNPat < - (i1 imm:$imm), - (S_MOV_B64 (i64 (as_i64imm $imm))) -> { +def : GCNPat <(i1 imm:$imm), + (S_MOV_B64 imm:$imm)> { let WaveSizePredicate = isWave64; } -def : GCNPat < - (i1 imm:$imm), - (S_MOV_B32 (i32 (as_i32imm $imm))) -> { +def : GCNPat <(i1 imm:$imm), + (S_MOV_B32 imm:$imm)> { let WaveSizePredicate = isWave32; } -def : GCNPat < - (f64 InlineImmFP64:$imm), - (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineImmFP64:$imm))) ->; - /********** ================== **********/ /********** Intrinsic Patterns **********/ /********** ================== **********/ Index: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir @@ -341,6 +341,195 @@ S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 ... +--- +name: constant_s_p2 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + + ; WAVE64-LABEL: name: constant_s_p2 + ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE64: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE64: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE64: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE64: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE64: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + ; WAVE32-LABEL: name: constant_s_p2 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE32: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE32: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE32: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE32: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE32: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + %0:sgpr(p2) = G_CONSTANT i32 0 + %1:sgpr(p2) = G_CONSTANT i32 1 + %2:sgpr(p2) = G_CONSTANT i32 -1 + %3:sgpr(p2) = G_CONSTANT i32 -54 + %4:sgpr(p2) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + +--- +name: constant_v_p2 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; WAVE64-LABEL: name: constant_v_p2 + ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + ; WAVE32-LABEL: name: constant_v_p2 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + %0:vgpr(p2) = G_CONSTANT i32 0 + %1:vgpr(p2) = G_CONSTANT i32 1 + %2:vgpr(p2) = G_CONSTANT i32 -1 + %3:vgpr(p2) = G_CONSTANT i32 -54 + %4:vgpr(p2) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + +--- +name: constant_s_p5 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + + ; WAVE64-LABEL: name: constant_s_p5 + ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE64: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE64: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE64: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE64: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE64: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + ; WAVE32-LABEL: name: constant_s_p5 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE32: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE32: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE32: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE32: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE32: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + %0:sgpr(p5) = G_CONSTANT i32 0 + %1:sgpr(p5) = G_CONSTANT i32 1 + %2:sgpr(p5) = G_CONSTANT i32 -1 + %3:sgpr(p5) = G_CONSTANT i32 -54 + %4:sgpr(p5) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + +--- +name: constant_v_p5 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; WAVE64-LABEL: name: constant_v_p5 + ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + ; WAVE32-LABEL: name: constant_v_p5 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + %0:vgpr(p5) = G_CONSTANT i32 0 + %1:vgpr(p5) = G_CONSTANT i32 1 + %2:vgpr(p5) = G_CONSTANT i32 -1 + %3:vgpr(p5) = G_CONSTANT i32 -54 + %4:vgpr(p5) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + +--- +name: constant_s_p6 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + + ; WAVE64-LABEL: name: constant_s_p6 + ; WAVE64: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE64: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE64: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE64: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE64: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE64: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + ; WAVE32-LABEL: name: constant_s_p6 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; WAVE32: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; WAVE32: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; WAVE32: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 -54 + ; WAVE32: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 27 + ; WAVE32: S_ENDPGM 0, implicit [[S_MOV_B32_]], implicit [[S_MOV_B32_1]], implicit [[S_MOV_B32_2]], implicit [[S_MOV_B32_3]], implicit [[S_MOV_B32_4]] + %0:sgpr(p6) = G_CONSTANT i32 0 + %1:sgpr(p6) = G_CONSTANT i32 1 + %2:sgpr(p6) = G_CONSTANT i32 -1 + %3:sgpr(p6) = G_CONSTANT i32 -54 + %4:sgpr(p6) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + +--- +name: constant_v_p6 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + ; WAVE64-LABEL: name: constant_v_p6 + ; WAVE64: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE64: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE64: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + ; WAVE32-LABEL: name: constant_v_p6 + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -54, implicit $exec + ; WAVE32: [[V_MOV_B32_e32_4:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec + ; WAVE32: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]], implicit [[V_MOV_B32_e32_1]], implicit [[V_MOV_B32_e32_2]], implicit [[V_MOV_B32_e32_3]], implicit [[V_MOV_B32_e32_4]] + %0:vgpr(p6) = G_CONSTANT i32 0 + %1:vgpr(p6) = G_CONSTANT i32 1 + %2:vgpr(p6) = G_CONSTANT i32 -1 + %3:vgpr(p6) = G_CONSTANT i32 -54 + %4:vgpr(p6) = G_CONSTANT i32 27 + S_ENDPGM 0, implicit %0 , implicit %1 , implicit %2, implicit %3, implicit %4 +... + --- name: constant_s_p1 legalized: true