Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3132,6 +3132,8 @@ SDValue HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { + if (DCI.isBeforeLegalize()) + return SDValue(); if (isHvxOperation(N)) { if (SDValue V = PerformHvxDAGCombine(N, DCI)) return V; Index: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1809,8 +1809,9 @@ auto IsHvxTy = [this] (EVT Ty) { return Ty.isSimple() && Subtarget.isHVXVectorType(Ty.getSimpleVT(), true); }; - auto IsHvxOp = [this] (SDValue Op) { - return Subtarget.isHVXVectorType(ty(Op), true); + auto IsHvxOp = [this](SDValue Op) { + return Op.getValueType().isSimple() && + Subtarget.isHVXVectorType(ty(Op), true); }; return llvm::any_of(N->values(), IsHvxTy) || llvm::any_of(N->ops(), IsHvxOp); } Index: llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/Hexagon/hvx-isel-vselect-v256i16.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=hexagon -mattr=+hvxv65,+hvx-length128b < %s | FileCheck %s +; This used to crash with +; "llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && +; Expected a SimpleValueType!' failed." + +; CHECK: vmax +define <256 x i16> @f0(<128 x i16> %v0, <128 x i16> %v1) { + %v01 = shufflevector <128 x i16> %v0, <128 x i16> %v1, <256 x i32> + %v10 = shufflevector <128 x i16> %v1, <128 x i16> %v0, <256 x i32> + %p0 = icmp sgt <256 x i16> %v01, %v10 + %res = select <256 x i1> %p0, <256 x i16> %v01, <256 x i16> %v10 + ret <256 x i16> %res +}