diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp --- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp @@ -160,6 +160,19 @@ switch (Opc) { default: break; + case TargetOpcode::COPY: { + assert(DstOps.size() == 1); + const DstOp &Dst = DstOps[0]; + assert(SrcOps.size() == 1); + const SrcOp &Src = SrcOps[0]; + if (Dst.getDstOpKind() == DstOp::DstType::Ty_LLT && + Dst.getLLTTy(*getMRI()) == Src.getLLTTy(*getMRI())) { + Register SrcReg = Src.getReg(); + assert(SrcReg.isVirtual()); + return MachineInstrBuilder(getMF(), getMRI()->getVRegDef(SrcReg)); + } + break; + } case TargetOpcode::G_ADD: case TargetOpcode::G_AND: case TargetOpcode::G_ASHR: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir @@ -17,13 +17,11 @@ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; CHECK: $x0 = COPY [[COPY1]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 - ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) - ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] ; CHECK: $x0 = COPY [[AND]](s64) - ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) - ; CHECK: $x0 = COPY [[COPY3]](s64) - ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY4]], 32 + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) + ; CHECK: $x0 = COPY [[COPY2]](s64) + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 ; CHECK: $x0 = COPY [[SEXT_INREG]](s64) ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1 @@ -53,8 +51,8 @@ ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32) ; CHECK: $x0 = COPY [[FPEXT]](s64) ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32) - ; CHECK: $w0 = COPY [[COPY5]](s32) + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32) + ; CHECK: $w0 = COPY [[COPY3]](s32) ; CHECK: $w0 = COPY [[C3]](s32) ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF ; CHECK: $w0 = COPY [[DEF]](s32) @@ -134,8 +132,7 @@ ; CHECK-LABEL: name: test_anyext_sext ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1 + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1 ; CHECK: $w0 = COPY [[SEXT_INREG]](s32) %0:_(s32) = COPY $w0 %1:_(s1) = G_TRUNC %0(s32) @@ -153,8 +150,7 @@ ; CHECK-LABEL: name: test_anyext_zext ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: $w0 = COPY [[AND]](s32) %0:_(s32) = COPY $w0 %1:_(s1) = G_TRUNC %0(s32) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir @@ -151,8 +151,7 @@ liveins: $w0 ; CHECK-LABEL: name: test_sitofp_s32_s1 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1 + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32) ; CHECK: $w0 = COPY [[SITOFP]](s32) %0:_(s32) = COPY $w0 @@ -169,8 +168,7 @@ ; CHECK-LABEL: name: test_uitofp_s32_s1 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) ; CHECK: $w0 = COPY [[UITOFP]](s32) %0:_(s32) = COPY $w0 @@ -186,8 +184,7 @@ liveins: $w0 ; CHECK-LABEL: name: test_sitofp_s64_s8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8 + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8 ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32) ; CHECK: $x0 = COPY [[SITOFP]](s64) %0:_(s32) = COPY $w0 @@ -204,8 +201,7 @@ ; CHECK-LABEL: name: test_uitofp_s64_s8 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32) ; CHECK: $x0 = COPY [[UITOFP]](s64) %0:_(s32) = COPY $w0 @@ -281,8 +277,7 @@ liveins: $w0 ; CHECK-LABEL: name: test_sitofp_s32_s16 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16 + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16 ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32) ; CHECK: $w0 = COPY [[SITOFP]](s32) %0:_(s32) = COPY $w0 @@ -299,8 +294,7 @@ ; CHECK-LABEL: name: test_uitofp_s32_s16 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32) ; CHECK: $w0 = COPY [[UITOFP]](s32) %0:_(s32) = COPY $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -305,16 +305,14 @@ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]] ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32) ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1 ; CHECK: bb.2: ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]] ; CHECK: $w0 = COPY [[AND1]](s32) ; CHECK: RET_ReallyLR implicit $w0 bb.0: @@ -610,7 +608,6 @@ selected: false tracksRegLiveness: true body: | - ; Check that the G_MERGE here gets inserted after all the PHIs. ; CHECK-LABEL: name: legalize_phi_check_insertpt ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x80000000) @@ -627,6 +624,7 @@ ; CHECK: G_STORE [[MV]](s128), [[COPY1]](p0) :: (store 16) ; CHECK: G_STORE [[PHI2]](s64), [[COPY1]](p0) :: (store 8) ; CHECK: RET_ReallyLR + ; Check that the G_MERGE here gets inserted after all the PHIs. bb.0: successors: %bb.1(0x40000000) liveins: $x0, $x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir @@ -7,8 +7,7 @@ ; CHECK-LABEL: name: test_ptr_add_small ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 - ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) - ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 8 + ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s64) ; CHECK: $x0 = COPY [[PTR_ADD]](p0) %0:_(p0) = COPY $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir @@ -28,13 +28,12 @@ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND1]](s32) ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[C3]] - ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26 ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]] - ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR]](s32) - ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]] + ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) + ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) + ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]] ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32) ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2 ; CHECK: bb.2: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir --- a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir @@ -9,11 +9,10 @@ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]] ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]] - ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND1]](s32) - ; CHECK: $w0 = COPY [[COPY3]](s32) + ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND1]](s32) + ; CHECK: $w0 = COPY [[COPY2]](s32) %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir @@ -51,9 +51,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -83,8 +82,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -140,9 +138,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -172,8 +169,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -232,8 +228,7 @@ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]] ; MIPS32: $v0 = COPY [[ADD2]](s32) ; MIPS32: $v1 = COPY [[ADD]](s32) @@ -282,18 +277,15 @@ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND2]] ; MIPS32: $v0 = COPY [[ADD]](s32) ; MIPS32: $v1 = COPY [[ADD2]](s32) @@ -340,8 +332,7 @@ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag) ; MIPS32: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store 4 into %ir.padd) ; MIPS32: RetRA diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir @@ -613,11 +613,9 @@ ; MIPS32: liveins: $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; MIPS32: $v0 = COPY [[COPY3]](s32) ; MIPS32: RetRA implicit $v0 @@ -642,16 +640,13 @@ ; MIPS32: liveins: $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32) - ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s32) - ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32) - ; MIPS32: $v0 = COPY [[COPY3]](s32) + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) + ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) + ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32) + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32) + ; MIPS32: $v0 = COPY [[COPY2]](s32) ; MIPS32: RetRA implicit $v0 %1:_(s32) = COPY $a0 %0:_(s8) = G_TRUNC %1(s32) @@ -676,12 +671,10 @@ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] - ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) - ; MIPS32: $v0 = COPY [[COPY3]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] + ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32) + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) + ; MIPS32: $v0 = COPY [[COPY2]](s32) ; MIPS32: RetRA implicit $v0 %1:_(s32) = COPY $a0 %0:_(s16) = G_TRUNC %1(s32) @@ -718,14 +711,11 @@ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]] ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32) ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C1]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]] ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[COPY1]], [[SELECT1]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: $v1 = COPY [[SELECT2]](s32) @@ -771,14 +761,11 @@ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32) ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32) ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]] ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]] ; MIPS32: $v0 = COPY [[SELECT1]](s32) ; MIPS32: $v1 = COPY [[SELECT2]](s32) @@ -822,14 +809,11 @@ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]] ; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32) ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]] ; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]] ; MIPS32: $v0 = COPY [[SELECT1]](s32) ; MIPS32: $v1 = COPY [[SELECT2]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir @@ -68,8 +68,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.if.then: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir @@ -55,10 +55,7 @@ ; MIPS32-LABEL: name: signed_i16 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) - ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; MIPS32: $v0 = COPY [[ASHR]](s32) + ; MIPS32: $v0 = COPY [[COPY]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s16) = G_CONSTANT i16 -32768 %1:_(s32) = G_SEXT %0(s16) @@ -75,10 +72,7 @@ ; MIPS32-LABEL: name: signed_i8 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32) - ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; MIPS32: $v0 = COPY [[ASHR]](s32) + ; MIPS32: $v0 = COPY [[COPY]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s8) = G_CONSTANT i8 -128 %1:_(s32) = G_SEXT %0(s8) @@ -94,10 +88,8 @@ bb.1.entry: ; MIPS32-LABEL: name: unsigned_i16 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] - ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768 + ; MIPS32: $v0 = COPY [[C1]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s16) = G_CONSTANT i16 -32768 %1:_(s32) = G_ZEXT %0(s16) @@ -113,10 +105,8 @@ bb.1.entry: ; MIPS32-LABEL: name: unsigned_i8 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128 - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] - ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 + ; MIPS32: $v0 = COPY [[C1]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s8) = G_CONSTANT i8 -128 %1:_(s32) = G_ZEXT %0(s8) @@ -133,8 +123,7 @@ ; MIPS32-LABEL: name: i1_true ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] - ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: $v0 = COPY [[COPY]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s1) = G_CONSTANT i1 true %1:_(s32) = G_ZEXT %0(s1) @@ -150,10 +139,8 @@ bb.1.entry: ; MIPS32-LABEL: name: i1_false ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] - ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: $v0 = COPY [[COPY]](s32) ; MIPS32: RetRA implicit $v0 %0:_(s1) = G_CONSTANT i1 false %1:_(s32) = G_ZEXT %0(s1) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir @@ -39,8 +39,7 @@ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: $v1 = COPY [[C]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir @@ -54,8 +54,7 @@ ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32) ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]] ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: $v1 = COPY [[C]](s32) @@ -92,8 +91,7 @@ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]] - ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[C1]], [[ADD1]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: RetRA implicit $v0 @@ -137,22 +135,19 @@ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]] ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32) ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]] - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]] ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32) ; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]] ; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]] ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) - ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]] ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64) ; MIPS32: $v0 = COPY [[UV]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir @@ -99,9 +99,8 @@ ; FP32: liveins: $f12 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: $v0 = COPY [[ASHR]](s32) ; FP32: RetRA implicit $v0 @@ -109,9 +108,8 @@ ; FP64: liveins: $f12 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: $v0 = COPY [[ASHR]](s32) ; FP64: RetRA implicit $v0 @@ -134,9 +132,8 @@ ; FP32: liveins: $f12 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: $v0 = COPY [[ASHR]](s32) ; FP32: RetRA implicit $v0 @@ -144,9 +141,8 @@ ; FP64: liveins: $f12 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: $v0 = COPY [[ASHR]](s32) ; FP64: RetRA implicit $v0 @@ -235,9 +231,8 @@ ; FP32: liveins: $d6 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: $v0 = COPY [[ASHR]](s32) ; FP32: RetRA implicit $v0 @@ -245,9 +240,8 @@ ; FP64: liveins: $d6 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: $v0 = COPY [[ASHR]](s32) ; FP64: RetRA implicit $v0 @@ -270,9 +264,8 @@ ; FP32: liveins: $d6 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: $v0 = COPY [[ASHR]](s32) ; FP32: RetRA implicit $v0 @@ -280,9 +273,8 @@ ; FP64: liveins: $d6 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: $v0 = COPY [[ASHR]](s32) ; FP64: RetRA implicit $v0 @@ -352,8 +344,7 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: $v0 = COPY [[SELECT]](s32) ; FP32: RetRA implicit $v0 @@ -368,8 +359,7 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: $v0 = COPY [[SELECT]](s32) ; FP64: RetRA implicit $v0 @@ -398,12 +388,10 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP32: $v0 = COPY [[AND1]](s32) ; FP32: RetRA implicit $v0 ; FP64-LABEL: name: f32tou16 @@ -417,12 +405,10 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP64: $v0 = COPY [[AND1]](s32) ; FP64: RetRA implicit $v0 %0:_(s32) = COPY $f12 @@ -451,12 +437,10 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP32: $v0 = COPY [[AND1]](s32) ; FP32: RetRA implicit $v0 ; FP64-LABEL: name: f32tou8 @@ -470,12 +454,10 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP64: $v0 = COPY [[AND1]](s32) ; FP64: RetRA implicit $v0 %0:_(s32) = COPY $f12 @@ -544,8 +526,7 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: $v0 = COPY [[SELECT]](s32) ; FP32: RetRA implicit $v0 @@ -560,8 +541,7 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: $v0 = COPY [[SELECT]](s32) ; FP64: RetRA implicit $v0 @@ -590,12 +570,10 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP32: $v0 = COPY [[AND1]](s32) ; FP32: RetRA implicit $v0 ; FP64-LABEL: name: f64tou16 @@ -609,12 +587,10 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP64: $v0 = COPY [[AND1]](s32) ; FP64: RetRA implicit $v0 %0:_(s64) = COPY $d6 @@ -643,12 +619,10 @@ ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP32: $v0 = COPY [[AND1]](s32) ; FP32: RetRA implicit $v0 ; FP64-LABEL: name: f64tou8 @@ -662,12 +636,10 @@ ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]] ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] + ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]] ; FP64: $v0 = COPY [[AND1]](s32) ; FP64: RetRA implicit $v0 %0:_(s64) = COPY $d6 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir @@ -79,13 +79,11 @@ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: $v0 = COPY [[COPY2]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %0:_(s8) = G_TRUNC %2(s32) @@ -109,16 +107,14 @@ ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: $v0 = COPY [[COPY2]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %0:_(s16) = G_TRUNC %2(s32) @@ -218,11 +214,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -256,11 +251,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -294,11 +288,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -332,11 +325,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -370,11 +362,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -408,11 +399,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -446,11 +436,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 @@ -484,11 +473,10 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY7]](s32) + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 %3:_(s32) = COPY $a1 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir @@ -84,8 +84,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.6 ; MIPS32: bb.1.entry: ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) @@ -109,17 +108,16 @@ ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000) ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C7]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32) - ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY4]](s32), [[COPY5]] + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32) + ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY3]](s32), [[COPY4]] ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C8]] ; MIPS32: G_BRCOND [[AND1]](s32), %bb.13 ; MIPS32: bb.8.sw.epilog: ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000) ; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.1 - ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32) + ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY3]](s32) ; MIPS32: bb.9.sw.bb4: ; MIPS32: $v0 = COPY [[C4]](s32) ; MIPS32: RetRA implicit $v0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir @@ -52,9 +52,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -84,8 +83,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -141,9 +139,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -173,8 +170,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -285,12 +281,10 @@ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]] ; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]] @@ -299,27 +293,22 @@ ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) - ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]] + ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]] - ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) - ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]] + ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]] ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]] ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]] ; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]] - ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32) - ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]] + ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C]] ; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]] ; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]] ; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]] - ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32) - ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]] + ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C]] ; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]] ; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]] ; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]] @@ -383,29 +372,24 @@ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]] ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]] ; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]] ; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]] - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) - ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]] + ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]] ; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]] - ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) - ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]] + ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]] ; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]] ; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]] ; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]] @@ -444,8 +428,7 @@ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]] ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]] ; MIPS32: G_STORE [[AND]](s32), [[COPY3]](p0) :: (store 1 into %ir.pcarry_flag) ; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store 4 into %ir.pmul) ; MIPS32: RetRA diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir @@ -157,21 +157,20 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: G_BR %bb.3 ; MIPS32: bb.2.cond.false: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; MIPS32: bb.3.cond.end: - ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) - ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY3]](s32), %bb.1, [[COPY4]](s32), %bb.2 + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) + ; MIPS32: $v0 = COPY [[COPY5]](s32) ; MIPS32: RetRA implicit $v0 bb.1.entry: liveins: $a0, $a1, $a2 @@ -210,21 +209,20 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: G_BR %bb.3 ; MIPS32: bb.2.cond.false: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; MIPS32: bb.3.cond.end: - ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) - ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY3]](s32), %bb.1, [[COPY4]](s32), %bb.2 + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) + ; MIPS32: $v0 = COPY [[COPY5]](s32) ; MIPS32: RetRA implicit $v0 bb.1.entry: liveins: $a0, $a1, $a2 @@ -263,21 +261,20 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: G_BR %bb.3 ; MIPS32: bb.2.cond.false: ; MIPS32: successors: %bb.3(0x80000000) - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; MIPS32: bb.3.cond.end: - ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2 - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) - ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY3]](s32), %bb.1, [[COPY4]](s32), %bb.2 + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[PHI]](s32) + ; MIPS32: $v0 = COPY [[COPY5]](s32) ; MIPS32: RetRA implicit $v0 bb.1.entry: liveins: $a0, $a1, $a2 @@ -316,8 +313,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: @@ -372,8 +368,7 @@ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1) ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: @@ -432,8 +427,7 @@ ; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load 8 from %ir.i64_ptr_a) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 8 from %ir.i64_ptr_b) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: @@ -482,8 +476,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: @@ -532,8 +525,7 @@ ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 4 from %ir.f32_ptr_a) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.f32_ptr_b) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: @@ -585,8 +577,7 @@ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; MIPS32: G_BRCOND [[AND]](s32), %bb.1 ; MIPS32: G_BR %bb.2 ; MIPS32: bb.1.cond.true: diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir @@ -32,16 +32,13 @@ ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) - ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32) ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: RetRA implicit $v0 @@ -67,16 +64,13 @@ ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32) - ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32) ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: RetRA implicit $v0 @@ -163,16 +157,13 @@ ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) - ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32) ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: RetRA implicit $v0 @@ -198,16 +189,13 @@ ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32) + ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32) ; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32) - ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32) ; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR2]](s32) ; MIPS32: RetRA implicit $v0 @@ -295,14 +283,11 @@ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32) ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -329,14 +314,11 @@ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32) ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -424,14 +406,11 @@ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32) ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -458,14 +437,11 @@ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32) ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir @@ -28,11 +28,10 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY5]](s32) ; MIPS32: RetRA implicit $v0 %3:_(s32) = COPY $a0 %0:_(s1) = G_TRUNC %3(s32) @@ -62,11 +61,10 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY5]](s32) ; MIPS32: RetRA implicit $v0 %3:_(s32) = COPY $a0 %0:_(s1) = G_TRUNC %3(s32) @@ -94,8 +92,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: RetRA implicit $v0 @@ -122,8 +119,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] ; MIPS32: $v0 = COPY [[SELECT]](p0) ; MIPS32: RetRA implicit $v0 @@ -155,8 +151,7 @@ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32) ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]] - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[XOR]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]] ; MIPS32: $v0 = COPY [[SELECT]](s32) ; MIPS32: RetRA implicit $v0 @@ -195,8 +190,7 @@ ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load 4 from %fixed-stack.1) ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]] ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64) ; MIPS32: $v0 = COPY [[UV]](s32) @@ -233,8 +227,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] ; MIPS32: $f0 = COPY [[SELECT]](s32) ; MIPS32: RetRA implicit $f0 @@ -264,8 +257,7 @@ ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load 4 from %fixed-stack.0, align 8) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]] ; MIPS32: $d0 = COPY [[SELECT]](s64) ; MIPS32: RetRA implicit $d0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir @@ -98,9 +98,8 @@ ; FP32-LABEL: name: i16tof32 ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; FP32: $f0 = COPY [[SITOFP]](s32) @@ -108,9 +107,8 @@ ; FP64-LABEL: name: i16tof32 ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; FP64: $f0 = COPY [[SITOFP]](s32) @@ -133,9 +131,8 @@ ; FP32-LABEL: name: i8tof32 ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; FP32: $f0 = COPY [[SITOFP]](s32) @@ -143,9 +140,8 @@ ; FP64-LABEL: name: i8tof32 ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; FP64: $f0 = COPY [[SITOFP]](s32) @@ -234,9 +230,8 @@ ; FP32-LABEL: name: i16tof64 ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; FP32: $d0 = COPY [[SITOFP]](s64) @@ -244,9 +239,8 @@ ; FP64-LABEL: name: i16tof64 ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; FP64: $d0 = COPY [[SITOFP]](s64) @@ -269,9 +263,8 @@ ; FP32-LABEL: name: i8tof64 ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; FP32: $d0 = COPY [[SITOFP]](s64) @@ -279,9 +272,8 @@ ; FP64-LABEL: name: i8tof64 ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) + ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; FP64: $d0 = COPY [[SITOFP]](s64) @@ -379,8 +371,7 @@ ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -392,8 +383,7 @@ ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -420,8 +410,7 @@ ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -433,8 +422,7 @@ ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -533,8 +521,7 @@ ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -545,8 +532,7 @@ ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -572,8 +558,7 @@ ; FP32: liveins: $a0 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 @@ -584,8 +569,7 @@ ; FP64: liveins: $a0 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200 ; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32) ; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir @@ -50,9 +50,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -82,8 +81,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -139,9 +137,8 @@ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32) + ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32) ; MIPS32: $v0 = COPY [[ASHR]](s32) ; MIPS32: RetRA implicit $v0 @@ -171,8 +168,7 @@ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]] ; MIPS32: $v0 = COPY [[AND]](s32) ; MIPS32: RetRA implicit $v0 %2:_(s32) = COPY $a0 @@ -231,8 +227,7 @@ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]] ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] ; MIPS32: $v0 = COPY [[SUB2]](s32) ; MIPS32: $v1 = COPY [[SUB]](s32) @@ -281,30 +276,25 @@ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]] ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]] ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]] ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]] - ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) - ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) - ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) - ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]] - ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY4]], [[COPY5]] ; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]] - ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]] + ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]] ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]] ; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]] ; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]] - ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) - ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) - ; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32) - ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]] - ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]] + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32) + ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]] + ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY6]], [[COPY7]] ; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]] - ; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32) - ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]] + ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]] ; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]] ; MIPS32: $v0 = COPY [[SUB]](s32) ; MIPS32: $v1 = COPY [[SUB2]](s32) diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir --- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir +++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir @@ -64,8 +64,7 @@ ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load 1 from %ir.py) ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]] ; MIPS32: G_STORE [[AND]](s32), [[COPY]](p0) :: (store 1 into %ir.px) ; MIPS32: RetRA %0:_(p0) = COPY $a0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll @@ -307,7 +307,6 @@ ; MIPS32-LABEL: shl_i16: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: andi $1, $1, 65535 ; MIPS32-NEXT: sllv $2, $4, $1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop @@ -320,7 +319,6 @@ ; MIPS32-LABEL: ashr_i8: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: andi $1, $1, 255 ; MIPS32-NEXT: sll $2, $4, 24 ; MIPS32-NEXT: sra $2, $2, 24 ; MIPS32-NEXT: srav $2, $2, $1 @@ -335,7 +333,6 @@ ; MIPS32-LABEL: lshr_i16: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: ori $1, $zero, 2 -; MIPS32-NEXT: andi $1, $1, 65535 ; MIPS32-NEXT: andi $2, $4, 65535 ; MIPS32-NEXT: srlv $2, $2, $1 ; MIPS32-NEXT: jr $ra diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll @@ -25,9 +25,7 @@ define signext i16 @signed_i16() { ; MIPS32-LABEL: signed_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $1, $zero, 32768 -; MIPS32-NEXT: sll $1, $1, 16 -; MIPS32-NEXT: sra $2, $1, 16 +; MIPS32-NEXT: addiu $2, $zero, 32768 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -37,9 +35,7 @@ define signext i8 @signed_i8() { ; MIPS32-LABEL: signed_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $1, $zero, 65408 -; MIPS32-NEXT: sll $1, $1, 24 -; MIPS32-NEXT: sra $2, $1, 24 +; MIPS32-NEXT: addiu $2, $zero, 65408 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -49,8 +45,7 @@ define zeroext i16 @unsigned_i16() { ; MIPS32-LABEL: unsigned_i16: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $1, $zero, 32768 -; MIPS32-NEXT: andi $2, $1, 65535 +; MIPS32-NEXT: ori $2, $zero, 32768 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -60,8 +55,7 @@ define zeroext i8 @unsigned_i8() { ; MIPS32-LABEL: unsigned_i8: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: addiu $1, $zero, 65408 -; MIPS32-NEXT: andi $2, $1, 255 +; MIPS32-NEXT: ori $2, $zero, 128 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -71,8 +65,7 @@ define zeroext i1 @i1_true() { ; MIPS32-LABEL: i1_true: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 1 -; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: ori $2, $zero, 1 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: @@ -82,8 +75,7 @@ define zeroext i1 @i1_false() { ; MIPS32-LABEL: i1_false: ; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: ori $1, $zero, 0 -; MIPS32-NEXT: andi $2, $1, 1 +; MIPS32-NEXT: ori $2, $zero, 0 ; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: nop entry: diff --git a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll --- a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll @@ -165,11 +165,9 @@ ; X64-LABEL: test_ashr_i1_imm1: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: movb $1, %cl ; X64-NEXT: shlb $7, %al ; X64-NEXT: sarb $7, %al -; X64-NEXT: andb $1, %cl -; X64-NEXT: sarb %cl, %al +; X64-NEXT: sarb %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %a = trunc i32 %arg1 to i1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir @@ -16,8 +16,7 @@ ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4) ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4) ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 - ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8) - ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]] + ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]] ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1) ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1) ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2) @@ -49,11 +48,11 @@ ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8) ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; X32: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32) - ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4 + 4) + ; X32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32) + ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 + 4) ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8) - ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32) - ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4 + 4) + ; X32: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[DEF]], [[C]](s32) + ; X32: G_STORE [[LOAD1]](s32), [[PTR_ADD1]](p0) :: (store 4 + 4) %0:_(p0) = IMPLICIT_DEF %1:_(s64) = G_LOAD %0 :: (load 8) diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir @@ -16,8 +16,7 @@ ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4) ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4) ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 - ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8) - ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]] + ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]] ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1) ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1) ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2) diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -39,8 +39,7 @@ ; CHECK: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]] ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[MUL]](s8) - ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]] ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1) ; CHECK: RET 0 %0(s32) = COPY $edx diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir @@ -47,8 +47,7 @@ ; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]] ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[OR]](s8) - ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[OR]], [[C]] ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1) ; CHECK: RET 0 %0(s32) = COPY $edx diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir @@ -30,8 +30,7 @@ ; CHECK: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]] ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[SUB]](s8) - ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[SUB]], [[C]] ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1) ; CHECK: RET 0 %0(s32) = COPY $edx diff --git a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll --- a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll @@ -164,10 +164,8 @@ ; X64-LABEL: test_lshr_i1_imm1: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: movb $1, %cl ; X64-NEXT: andb $1, %al -; X64-NEXT: andb $1, %cl -; X64-NEXT: shrb %cl, %al +; X64-NEXT: shrb %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %a = trunc i32 %arg1 to i1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll --- a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll @@ -161,10 +161,8 @@ define i1 @test_shl_i1_imm1(i32 %arg1) { ; X64-LABEL: test_shl_i1_imm1: ; X64: # %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: movb $1, %cl -; X64-NEXT: andb $1, %cl -; X64-NEXT: shlb %cl, %al +; X64-NEXT: # kill: def $edi killed $edi def $rdi +; X64-NEXT: leal (%rdi,%rdi), %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq %a = trunc i32 %arg1 to i1 diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir @@ -88,11 +88,10 @@ ; CHECK-LABEL: name: int8_to_float ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24 - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8) - ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8) - ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8) + ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8) + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8) ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) @@ -121,11 +120,10 @@ ; CHECK-LABEL: name: int16_to_float ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16 - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8) - ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8) - ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8) + ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8) + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8) ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32) ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) @@ -206,11 +204,10 @@ ; CHECK-LABEL: name: int8_to_double ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24 - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8) - ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8) - ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8) + ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8) + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8) ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) @@ -239,11 +236,10 @@ ; CHECK-LABEL: name: int16_to_double ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16 - ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8) - ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8) - ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8) + ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8) + ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8) + ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8) ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64) ; CHECK: $xmm0 = COPY [[ANYEXT]](s128) diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir @@ -124,8 +124,7 @@ ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: $eax = COPY [[AND]](s32) ; CHECK: RET 0, implicit $eax %1:_(s32) = COPY $edi @@ -205,8 +204,7 @@ ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: $eax = COPY [[AND]](s32) ; CHECK: RET 0, implicit $eax %1:_(s32) = COPY $edi @@ -259,8 +257,7 @@ ; CHECK: liveins: $edi ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] + ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]] ; CHECK: $eax = COPY [[AND]](s32) ; CHECK: RET 0, implicit $eax %1:_(s32) = COPY $edi