Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3304,6 +3304,18 @@
   unsigned Opcode = N->getOpcode();
   unsigned InVTNumElts = InVT.getVectorNumElements();
   const SDNodeFlags Flags = N->getFlags();
+
+  if (N->getOpcode() == ISD::ZERO_EXTEND &&
+      getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
+    InOp = ZExtPromotedInteger(InOp);
+    InVT = InOp.getValueType();
+    InEltVT = InVT.getVectorElementType();
+    InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
+    InVTNumElts = InVT.getVectorNumElements();
+    if (WidenVT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
+      Opcode = ISD::TRUNCATE;
+  }
+
   if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
     InOp = GetWidenedVector(N->getOperand(0));
     InVT = InOp.getValueType();
Index: llvm/test/CodeGen/SystemZ/vec-zext.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/vec-zext.ll
+++ llvm/test/CodeGen/SystemZ/vec-zext.ll
@@ -92,3 +92,19 @@
   ret <8 x i16> %z
 }
 
+define <2 x i32> @fun11(<2 x i64> %Arg1, <2 x i64> %Arg2) {
+; CHECK-LABEL: fun11:
+; CHECK:      vgbm    %v0, 0
+; CHECK-NEXT: vceqg   %v1, %v24, %v0
+; CHECK-NEXT: vceqg   %v0, %v26, %v0
+; CHECK-NEXT: vo      %v0, %v1, %v0
+; CHECK-NEXT: vrepig  %v1, 1
+; CHECK-NEXT: vn      %v0, %v0, %v1
+; CHECK-NEXT: vpkg    %v24, %v0, %v0
+; CHECK-NEXT: br      %r14
+  %i3 = icmp eq <2 x i64> %Arg1, zeroinitializer
+  %i5 = icmp eq <2 x i64> %Arg2, zeroinitializer
+  %i6 = or <2 x i1> %i3, %i5
+  %i7 = zext <2 x i1> %i6 to <2 x i32>
+  ret <2 x i32> %i7
+}