Index: llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -486,7 +486,7 @@ MachineRegisterInfo &MRI, MachineIRBuilder &Builder, SmallVectorImpl &UpdatedDefs, - GISelObserverWrapper &Observer) { + GISelChangeObserver &Observer) { if (!llvm::canReplaceReg(DstReg, SrcReg, MRI)) { Builder.buildCopy(DstReg, SrcReg); UpdatedDefs.push_back(DstReg); @@ -521,7 +521,7 @@ bool tryCombineUnmergeValues(MachineInstr &MI, SmallVectorImpl &DeadInsts, SmallVectorImpl &UpdatedDefs, - GISelObserverWrapper &Observer) { + GISelChangeObserver &Observer) { assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); unsigned NumDefs = MI.getNumOperands() - 1; Index: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h =================================================================== --- llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -252,6 +252,11 @@ setDebugLoc(MI.getDebugLoc()); } + MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) : + MachineIRBuilder(MI) { + setChangeObserver(Observer); + } + virtual ~MachineIRBuilder() = default; MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {} Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -91,17 +91,14 @@ MachineIRBuilder &Builder) : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()), - TLI(*MF.getSubtarget().getTargetLowering()) { - MIRBuilder.setChangeObserver(Observer); -} + TLI(*MF.getSubtarget().getTargetLowering()) { } LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, GISelChangeObserver &Observer, MachineIRBuilder &B) : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), - TLI(*MF.getSubtarget().getTargetLowering()) { - MIRBuilder.setChangeObserver(Observer); -} + TLI(*MF.getSubtarget().getTargetLowering()) { } + LegalizerHelper::LegalizeResult LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { LLVM_DEBUG(dbgs() << "Legalizing: " << MI); Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -187,7 +187,12 @@ } void changingInstr(MachineInstr &MI) override {} - void changedInstr(MachineInstr &MI) override {} + void changedInstr(MachineInstr &MI) override { + // FIXME: In principle we should probably add the instruction to NewInsts, + // but the way the LegalizerHelper uses the observer, we will always see the + // registers we need to set the regbank on also referenced in a new + // instruction. + } }; } @@ -1171,10 +1176,8 @@ // 96-bit loads are only available for vector loads. We need to split this // into a 64-bit part, and 32 (unless we can widen to a 128-bit load). - MachineIRBuilder B(MI); ApplyRegBankMapping O(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&O); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, O); if (MMO->getAlign() < Align(16)) { LLT Part64, Part32; @@ -1213,13 +1216,10 @@ LLT PtrTy = MRI.getType(MI.getOperand(1).getReg()); MRI.setType(BasePtrReg, PtrTy); - MachineIRBuilder B(MI); - unsigned NumSplitParts = LoadTy.getSizeInBits() / MaxNonSmrdLoadSize; const LLT LoadSplitTy = LoadTy.divide(NumSplitParts); - ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); - GISelObserverWrapper Observer(&O); - B.setChangeObserver(Observer); + ApplyRegBankMapping Observer(*this, MRI, &AMDGPU::VGPRRegBank); + MachineIRBuilder B(MI, Observer); LegalizerHelper Helper(B.getMF(), Observer, B); if (LoadTy.isVector()) { @@ -1263,10 +1263,7 @@ const SIMachineFunctionInfo *Info = MF.getInfo(); Register SPReg = Info->getStackPtrOffsetReg(); ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplyBank); - - MachineIRBuilder B(MI); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, ApplyBank); auto WaveSize = B.buildConstant(LLT::scalar(32), ST.getWavefrontSizeLog2()); auto ScaledSize = B.buildShl(IntPtrTy, AllocSize, WaveSize); @@ -1556,9 +1553,7 @@ // The scalar form packs the offset and width in a single operand. ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - B.setChangeObserver(Observer); + MachineIRBuilder B(MI, ApplyBank); // Ensure the high bits are clear to insert the offset. auto OffsetMask = B.buildConstant(S32, maskTrailingOnes(6)); @@ -2150,9 +2145,8 @@ // Promote SGPR/VGPR booleans to s32 MachineFunction *MF = MI.getParent()->getParent(); ApplyRegBankMapping ApplyBank(*this, MRI, DstBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - LegalizerHelper Helper(*MF, Observer, B); + MachineIRBuilder B(MI, ApplyBank); + LegalizerHelper Helper(*MF, ApplyBank, B); if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); @@ -2295,9 +2289,8 @@ MachineFunction *MF = MI.getParent()->getParent(); ApplyRegBankMapping ApplyBank(*this, MRI, DstBank); - GISelObserverWrapper Observer(&ApplyBank); - MachineIRBuilder B(MI); - LegalizerHelper Helper(*MF, Observer, B); + MachineIRBuilder B(MI, ApplyBank); + LegalizerHelper Helper(*MF, ApplyBank, B); if (Helper.widenScalar(MI, 0, LLT::scalar(32)) != LegalizerHelper::Legalized) @@ -2369,13 +2362,10 @@ const LLT S32 = LLT::scalar(32); MachineBasicBlock *MBB = MI.getParent(); MachineFunction *MF = MBB->getParent(); - MachineIRBuilder B(MI); ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); + MachineIRBuilder B(MI, ApplySALU); if (DstTy.isVector()) { - B.setChangeObserver(Observer); - Register WideSrc0Lo, WideSrc0Hi; Register WideSrc1Lo, WideSrc1Hi; @@ -2388,7 +2378,7 @@ B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)}); MI.eraseFromParent(); } else { - LegalizerHelper Helper(*MF, Observer, B); + LegalizerHelper Helper(*MF, ApplySALU, B); if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); @@ -2425,8 +2415,7 @@ if (Ty == V2S16) { ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); - B.setChangeObserver(Observer); + B.setChangeObserver(ApplySALU); // Need to widen to s32, and expand as cmp + select, and avoid producing // illegal vector extends or unmerges that would need further @@ -2458,8 +2447,8 @@ MI.eraseFromParent(); } else if (Ty == S16) { ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); - GISelObserverWrapper Observer(&ApplySALU); - LegalizerHelper Helper(*MF, Observer, B); + B.setChangeObserver(ApplySALU); + LegalizerHelper Helper(*MF, ApplySALU, B); // Need to widen to s32, and expand as cmp + select. if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) @@ -2513,9 +2502,6 @@ case AMDGPU::G_CTPOP: case AMDGPU::G_CTLZ_ZERO_UNDEF: case AMDGPU::G_CTTZ_ZERO_UNDEF: { - MachineIRBuilder B(MI); - MachineFunction &MF = B.getMF(); - const RegisterBank *DstBank = OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank; if (DstBank == &AMDGPU::SGPRRegBank) @@ -2528,8 +2514,10 @@ break; ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); - GISelObserverWrapper Observer(&ApplyVALU); - LegalizerHelper Helper(MF, Observer, B); + MachineIRBuilder B(MI, ApplyVALU); + + MachineFunction &MF = B.getMF(); + LegalizerHelper Helper(MF, ApplyVALU, B); if (Helper.narrowScalar(MI, 1, S32) != LegalizerHelper::Legalized) llvm_unreachable("narrowScalar should have succeeded"); Index: llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -716,7 +716,7 @@ static void combineAwayG_UNMERGE_VALUES(LegalizationArtifactCombiner &ArtCombiner, - MachineInstr &MI, GISelObserverWrapper &Observer) { + MachineInstr &MI, GISelChangeObserver &Observer) { SmallVector UpdatedDefs; SmallVector DeadInstrs; ArtCombiner.tryCombineUnmergeValues(MI, DeadInstrs, UpdatedDefs, Observer); @@ -728,14 +728,13 @@ const OperandsMapper &OpdMapper) const { MachineInstr &MI = OpdMapper.getMI(); InstListTy NewInstrs; - MachineIRBuilder B(MI); MachineFunction *MF = MI.getMF(); MachineRegisterInfo &MRI = OpdMapper.getMRI(); const LegalizerInfo &LegInfo = *MF->getSubtarget().getLegalizerInfo(); InstManager NewInstrObserver(NewInstrs); - GISelObserverWrapper WrapperObserver(&NewInstrObserver); - LegalizerHelper Helper(*MF, WrapperObserver, B); + MachineIRBuilder B(MI, NewInstrObserver); + LegalizerHelper Helper(*MF, NewInstrObserver, B); LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), LegInfo); switch (MI.getOpcode()) { @@ -752,7 +751,7 @@ // not be considered for regbank selection. RegBankSelect for mips // visits/makes corresponding G_MERGE first. Combine them here. if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) - combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI, WrapperObserver); + combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI, NewInstrObserver); // This G_MERGE will be combined away when its corresponding G_UNMERGE // gets regBankSelected. else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) @@ -764,7 +763,7 @@ return; } case TargetOpcode::G_UNMERGE_VALUES: - combineAwayG_UNMERGE_VALUES(ArtCombiner, MI, WrapperObserver); + combineAwayG_UNMERGE_VALUES(ArtCombiner, MI, NewInstrObserver); return; default: break; Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir =================================================================== --- llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir +++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir @@ -11,11 +11,8 @@ ; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s8) = G_TRUNC ; CHECK: CSEInfo::Add MI: %{{[0-9]+}}:_(s32) = G_ZEXT ; CHECK: CSEInfo::Recording new MI G_CONSTANT - ; CHECK: CSEInfo::Recording new MI G_CONSTANT - ; CHECK: CSEInfo::Recording new MI G_TRUNC ; CHECK: CSEInfo::Recording new MI G_TRUNC ; CHECK: CSEInfo::Recording new MI G_AND - ; CHECK: CSEInfo::Recording new MI G_AND ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_CONSTANT ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_TRUNC ; CHECK: CSEInfo::Found Instr %{{[0-9]+}}:_(s32) = G_AND