diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -895,6 +895,7 @@
SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -375,6 +375,13 @@
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
+ // These are equivalent to FP_TO_[SU]INT if the saturation width matches
+ // the result width, otherwise they require expansion.
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
+
// Variable arguments.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAARG, MVT::Other, Custom);
@@ -814,6 +821,8 @@
setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
+ setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v1i64, Expand);
+ setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v1i64, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
@@ -1099,6 +1108,8 @@
setOperationAction(ISD::FP_TO_SINT, VT, Custom);
setOperationAction(ISD::FP_TO_UINT, VT, Custom);
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
+ setOperationAction(ISD::FP_TO_UINT_SAT, VT, Custom);
if (!VT.isFloatingPoint())
setOperationAction(ISD::ABS, VT, Legal);
@@ -2865,22 +2876,36 @@
EVT InVT = Op.getOperand(0).getValueType();
EVT VT = Op.getValueType();
unsigned NumElts = InVT.getVectorNumElements();
+ bool IsSat = Op.getOpcode() == ISD::FP_TO_SINT_SAT ||
+ Op.getOpcode() == ISD::FP_TO_UINT_SAT;
// f16 conversions are promoted to f32 when full fp16 is not supported.
if (InVT.getVectorElementType() == MVT::f16 &&
!Subtarget->hasFullFP16()) {
MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
SDLoc dl(Op);
- return DAG.getNode(
- Op.getOpcode(), dl, Op.getValueType(),
- DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
+ if (IsSat)
+ return DAG.getNode(
+ Op.getOpcode(), dl, Op.getValueType(),
+ DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)),
+ Op.getOperand(1));
+ else
+ return DAG.getNode(
+ Op.getOpcode(), dl, Op.getValueType(),
+ DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
}
if (VT.getSizeInBits() < InVT.getSizeInBits()) {
SDLoc dl(Op);
- SDValue Cv =
- DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
- Op.getOperand(0));
+ SDValue Cv;
+ if (IsSat)
+ Cv = DAG.getNode(Op.getOpcode(), dl,
+ InVT.changeVectorElementTypeToInteger(),
+ Op.getOperand(0), Op.getOperand(1));
+ else
+ Cv = DAG.getNode(Op.getOpcode(), dl,
+ InVT.changeVectorElementTypeToInteger(),
+ Op.getOperand(0));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
}
@@ -2890,7 +2915,10 @@
MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
VT.getVectorNumElements());
SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
- return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
+ if (IsSat)
+ return DAG.getNode(Op.getOpcode(), dl, VT, Ext, Op.getOperand(1));
+ else
+ return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
}
// Type changing conversions are illegal.
@@ -2957,6 +2985,108 @@
return Op;
}
+SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDValue Src = Op.getOperand(0);
+ EVT SrcVT = Src.getValueType();
+ EVT DstVT = Op.getValueType();
+ unsigned SatWidth = Op.getConstantOperandVal(1);
+ unsigned DstWidth = DstVT.getScalarSizeInBits().getFixedSize();
+ SDLoc dl(Op);
+
+ if (SrcVT.isVector()) {
+ SDValue Vec = LowerVectorFP_TO_INT(Op, DAG);
+ if (Vec != Op)
+ return Vec;
+ }
+
+ // f16 conversions are promoted to f32 when full fp16 is not supported.
+ if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16()) {
+ SDValue Extend = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Src);
+ return DAG.getNode(Op.getOpcode(), dl, DstVT, Extend, Op.getOperand(1));
+ }
+
+ // f128 conversions are not native, so we can't trust that they saturate.
+ // Use the default expansion.
+ if (SrcVT == MVT::f128)
+ return SDValue();
+
+ // The below expansion is mostly lifted from expandFP_TO_INT_SAT with
+ // modifications to take advantage of AArch64's natively saturating conversion
+ // instructions.
+ if (DstWidth == SatWidth)
+ return Op;
+
+ bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
+ APInt MinInt, MaxInt;
+ if (IsSigned) {
+ MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth);
+ MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth);
+ } else {
+ MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth);
+ MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth);
+ }
+
+ SDValue MinIntNode = DAG.getConstant(MinInt, dl, DstVT);
+ SDValue MaxIntNode = DAG.getConstant(MaxInt, dl, DstVT);
+
+ APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+ APFloat MaxFloat(DAG.EVTToAPFloatSemantics(SrcVT));
+
+ APFloat::opStatus MinStatus =
+ MinFloat.convertFromAPInt(MinInt, IsSigned, APFloat::rmTowardZero);
+ APFloat::opStatus MaxStatus =
+ MaxFloat.convertFromAPInt(MaxInt, IsSigned, APFloat::rmTowardZero);
+ bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) &&
+ !(MaxStatus & APFloat::opStatus::opInexact);
+
+ SDValue MinFloatNode = DAG.getConstantFP(MinFloat, dl, SrcVT);
+ SDValue MaxFloatNode = DAG.getConstantFP(MaxFloat, dl, SrcVT);
+
+ // If the integer bounds are exactly representable as floats and min/max are
+ // legal, emit a min+max+fptoi sequence. Otherwise we have to use a sequence
+ // of comparisons and selects.
+ bool MinMaxLegal = isOperationLegal(ISD::FMINNUM, SrcVT) &&
+ isOperationLegal(ISD::FMAXNUM, SrcVT);
+
+ // We want the fmin/fmax pattern for vectors since those operations have
+ // vector support and the min/max integer pattern does not.
+ if (DstWidth != SatWidth && SrcVT.isVector() && AreExactFloatBounds &&
+ MinMaxLegal) {
+ SDValue Clamped = Src;
+ // Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
+ Clamped = DAG.getNode(ISD::FMAXNUM, dl, SrcVT, Clamped, MinFloatNode);
+ // Clamp by MaxFloat from above. NaN cannot occur.
+ Clamped = DAG.getNode(ISD::FMINNUM, dl, SrcVT, Clamped, MaxFloatNode);
+ // Convert clamped value to integer.
+ SDValue FpToInt =
+ DAG.getNode(IsSigned ? ISD::FP_TO_SINT_SAT : ISD::FP_TO_UINT_SAT, dl,
+ DstVT, Clamped, DAG.getConstant(DstWidth, dl, MVT::i32));
+ return FpToInt;
+ }
+
+ // The native fp to int conversions are already saturating, lower to them.
+ SDValue Select =
+ DAG.getNode(IsSigned ? ISD::FP_TO_SINT_SAT : ISD::FP_TO_UINT_SAT, dl,
+ DstVT, Src, DAG.getConstant(DstWidth, dl, MVT::i32));
+
+ // If the saturation width is the same as the destination width, we don't
+ // need to emit explicit saturation. However, the vector ops only saturate
+ // when the scalar size of the type is the same (e.g. f32 -> i32).
+ if (DstWidth == SatWidth &&
+ (!SrcVT.isVector() ||
+ SrcVT.getScalarSizeInBits() == DstVT.getScalarSizeInBits()))
+ return Select;
+
+ if (IsSigned)
+ Select = DAG.getSelectCC(dl, Select, MinIntNode, MinIntNode, Select,
+ ISD::CondCode::SETLT);
+ Select =
+ DAG.getSelectCC(dl, Select, MaxIntNode, MaxIntNode, Select,
+ IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT);
+ return Select;
+}
+
SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
if (Op.getValueType().isVector())
@@ -3764,6 +3894,9 @@
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
return LowerFP_TO_INT(Op, DAG);
+ case ISD::FP_TO_SINT_SAT:
+ case ISD::FP_TO_UINT_SAT:
+ return LowerFP_TO_INT_SAT(Op, DAG);
case ISD::FSINCOS:
return LowerFSINCOS(Op, DAG);
case ISD::FLT_ROUNDS_:
@@ -8713,6 +8846,8 @@
// Try to build a simple constant vector.
Op = NormalizeBuildVector(Op, DAG);
+ if (!isa<BuildVectorSDNode>(Op.getNode()))
+ return Op;
if (VT.isInteger()) {
// Certain vector constants, used to express things like logical NOT and
// arithmetic NEG, are passed through unmodified. This allows special
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3545,6 +3545,24 @@
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
+multiclass FPToIntegerSatPats<SDNode to_int, string INST> {
+ def : Pat<(i32 (to_int f16:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # UWHr) $Rn)>;
+ def : Pat<(i64 (to_int f16:$Rn, (i32 64))),
+ (!cast<Instruction>(INST # UXHr) $Rn)>;
+ def : Pat<(i32 (to_int f32:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # UWSr) $Rn)>;
+ def : Pat<(i64 (to_int f32:$Rn, (i32 64))),
+ (!cast<Instruction>(INST # UXSr) $Rn)>;
+ def : Pat<(i32 (to_int f64:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # UWDr) $Rn)>;
+ def : Pat<(i64 (to_int f64:$Rn, (i32 64))),
+ (!cast<Instruction>(INST # UXDr) $Rn)>;
+}
+
+defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
+
let Predicates = [HasFullFP16] in {
def : Pat<(i32 (lround f16:$Rn)),
(!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
@@ -3891,6 +3909,22 @@
defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
+multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int, string INST> {
+ def : Pat<(v4i16 (to_int v4f16:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # v4f16) $Rn)>;
+ def : Pat<(v8i16 (to_int v8f16:$Rn, (i32 64))),
+ (!cast<Instruction>(INST # v8f16) $Rn)>;
+ def : Pat<(v2i32 (to_int v2f32:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # v2f32) $Rn)>;
+ def : Pat<(v4i32 (to_int v4f32:$Rn, (i32 32))),
+ (!cast<Instruction>(INST # v4f32) $Rn)>;
+ def : Pat<(v2i64 (to_int v2f64:$Rn, (i32 64))),
+ (!cast<Instruction>(INST # v2f64) $Rn)>;
+}
+
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : SIMDTwoVectorFPToIntSatPats<fp_to_uint_sat, "FCVTZU">;
+
def : Pat<(v4i16 (int_aarch64_neon_fcvtzs v4f16:$Rn)), (FCVTZSv4f16 $Rn)>;
def : Pat<(v8i16 (int_aarch64_neon_fcvtzs v8f16:$Rn)), (FCVTZSv8f16 $Rn)>;
def : Pat<(v2i32 (int_aarch64_neon_fcvtzs v2f32:$Rn)), (FCVTZSv2f32 $Rn)>;
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
@@ -19,13 +19,11 @@
define i1 @test_signed_i1_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i1_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s1, #-1.00000000
-; CHECK-NEXT: fmov s2, wzr
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: cmn w8, #1 // =1
+; CHECK-NEXT: csinv w8, w8, wzr, ge
+; CHECK-NEXT: cmp w8, #0 // =0
+; CHECK-NEXT: csel w8, wzr, w8, gt
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptosi.sat.i1.f32(float %f)
@@ -35,15 +33,13 @@
define i8 @test_signed_i8_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i8_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-1023410176
-; CHECK-NEXT: mov w9, #1123942400
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #-128
+; CHECK-NEXT: cmn w8, #128 // =128
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #127 // =127
+; CHECK-NEXT: mov w9, #127
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i8 @llvm.fptosi.sat.i8.f32(float %f)
ret i8 %x
@@ -52,16 +48,13 @@
define i13 @test_signed_i13_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i13_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-981467136
-; CHECK-NEXT: mov w9, #61440
-; CHECK-NEXT: movk w9, #17791, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #-4096
+; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #4095 // =4095
+; CHECK-NEXT: mov w9, #4095
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i13 @llvm.fptosi.sat.i13.f32(float %f)
ret i13 %x
@@ -70,16 +63,13 @@
define i16 @test_signed_i16_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i16_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312
-; CHECK-NEXT: mov w9, #65024
-; CHECK-NEXT: movk w9, #18175, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #-32768
+; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT: mov w9, #32767
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i16 @llvm.fptosi.sat.i16.f32(float %f)
ret i16 %x
@@ -88,16 +78,13 @@
define i19 @test_signed_i19_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i19_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-931135488
-; CHECK-NEXT: mov w9, #65472
-; CHECK-NEXT: movk w9, #18559, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: mov w9, #-262144
+; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT: mov w9, #262143
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
ret i19 %x
@@ -106,19 +93,7 @@
define i32 @test_signed_i32_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i32_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-822083584
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: mov w10, #-2147483648
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w11
-; CHECK-NEXT: mov w12, #2147483647
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w0, s0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
ret i32 %x
@@ -127,19 +102,13 @@
define i50 @test_signed_i50_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i50_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-671088640
-; CHECK-NEXT: mov w11, #1476395007
-; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: mov x10, #-562949953421312
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w11
-; CHECK-NEXT: mov x12, #562949953421311
-; CHECK-NEXT: csel x8, x10, x8, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel x8, x12, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: mov x9, #-562949953421312
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x8, x9, x8, lt
+; CHECK-NEXT: mov x9, #562949953421311
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
ret i50 %x
@@ -148,19 +117,7 @@
define i64 @test_signed_i64_f32(float %f) nounwind {
; CHECK-LABEL: test_signed_i64_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-553648128
-; CHECK-NEXT: mov w11, #1593835519
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: mov x10, #-9223372036854775808
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w11
-; CHECK-NEXT: mov x12, #9223372036854775807
-; CHECK-NEXT: csel x8, x10, x8, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel x8, x12, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: fcvtzs x0, s0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
ret i64 %x
@@ -242,13 +199,11 @@
define i1 @test_signed_i1_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i1_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d1, #-1.00000000
-; CHECK-NEXT: fmov d2, xzr
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w8, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: cmn w8, #1 // =1
+; CHECK-NEXT: csinv w8, w8, wzr, ge
+; CHECK-NEXT: cmp w8, #0 // =0
+; CHECK-NEXT: csel w8, wzr, w8, gt
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptosi.sat.i1.f64(double %f)
@@ -258,16 +213,13 @@
define i8 @test_signed_i8_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i8_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4584664420663164928
-; CHECK-NEXT: mov x9, #211106232532992
-; CHECK-NEXT: movk x9, #16479, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #-128
+; CHECK-NEXT: cmn w8, #128 // =128
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #127 // =127
+; CHECK-NEXT: mov w9, #127
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i8 @llvm.fptosi.sat.i8.f64(double %f)
ret i8 %x
@@ -276,16 +228,13 @@
define i13 @test_signed_i13_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i13_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4562146422526312448
-; CHECK-NEXT: mov x9, #279275953455104
-; CHECK-NEXT: movk x9, #16559, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #-4096
+; CHECK-NEXT: cmn w8, #1, lsl #12 // =4096
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #4095 // =4095
+; CHECK-NEXT: mov w9, #4095
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i13 @llvm.fptosi.sat.i13.f64(double %f)
ret i13 %x
@@ -294,16 +243,13 @@
define i16 @test_signed_i16_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i16_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4548635623644200960
-; CHECK-NEXT: mov x9, #281200098803712
-; CHECK-NEXT: movk x9, #16607, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #-32768
+; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT: mov w9, #32767
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i16 @llvm.fptosi.sat.i16.f64(double %f)
ret i16 %x
@@ -312,16 +258,13 @@
define i19 @test_signed_i19_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i19_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4535124824762089472
-; CHECK-NEXT: mov x9, #281440616972288
-; CHECK-NEXT: movk x9, #16655, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
+; CHECK-NEXT: mov w9, #-262144
+; CHECK-NEXT: cmn w8, #64, lsl #12 // =262144
+; CHECK-NEXT: csel w8, w9, w8, lt
+; CHECK-NEXT: cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT: mov w9, #262143
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
ret i19 %x
@@ -330,16 +273,7 @@
define i32 @test_signed_i32_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i32_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024
-; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w0, d0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
ret i32 %x
@@ -348,16 +282,13 @@
define i50 @test_signed_i50_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i50_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4395513236313604096
-; CHECK-NEXT: mov x9, #-16
-; CHECK-NEXT: movk x9, #17151, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs x8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: mov x9, #-562949953421312
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x8, x9, x8, lt
+; CHECK-NEXT: mov x9, #562949953421311
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
ret i50 %x
@@ -366,19 +297,7 @@
define i64 @test_signed_i64_f64(double %f) nounwind {
; CHECK-LABEL: test_signed_i64_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x9, #-4332462841530417152
-; CHECK-NEXT: mov x11, #4890909195324358655
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: mov x10, #-9223372036854775808
-; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: fmov d1, x11
-; CHECK-NEXT: mov x12, #9223372036854775807
-; CHECK-NEXT: csel x8, x10, x8, lt
-; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: csel x8, x12, x8, gt
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: fcvtzs x0, d0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
ret i64 %x
@@ -461,13 +380,11 @@
; CHECK-LABEL: test_signed_i1_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, #-1.00000000
-; CHECK-NEXT: fmov s2, wzr
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, s0
+; CHECK-NEXT: cmn w8, #1 // =1
+; CHECK-NEXT: csinv w8, w8, wzr, ge
+; CHECK-NEXT: cmp w8, #0 // =0
+; CHECK-NEXT: csel w8, wzr, w8, gt
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptosi.sat.i1.f16(half %f)
@@ -477,16 +394,14 @@
define i8 @test_signed_i8_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i8_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-1023410176
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov w9, #1123942400
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-128
+; CHECK-NEXT: cmn w9, #128 // =128
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmp w8, #127 // =127
+; CHECK-NEXT: mov w9, #127
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i8 @llvm.fptosi.sat.i8.f16(half %f)
ret i8 %x
@@ -495,17 +410,14 @@
define i13 @test_signed_i13_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i13_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-981467136
-; CHECK-NEXT: mov w9, #61440
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movk w9, #17791, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-4096
+; CHECK-NEXT: cmn w9, #1, lsl #12 // =4096
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmp w8, #4095 // =4095
+; CHECK-NEXT: mov w9, #4095
+; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: ret
%x = call i13 @llvm.fptosi.sat.i13.f16(half %f)
ret i13 %x
@@ -514,17 +426,14 @@
define i16 @test_signed_i16_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i16_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312
-; CHECK-NEXT: mov w9, #65024
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movk w9, #18175, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-32768
+; CHECK-NEXT: cmn w9, #8, lsl #12 // =32768
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmp w8, #8, lsl #12 // =32768
+; CHECK-NEXT: mov w9, #32767
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i16 @llvm.fptosi.sat.i16.f16(half %f)
ret i16 %x
@@ -533,17 +442,14 @@
define i19 @test_signed_i19_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i19_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-931135488
-; CHECK-NEXT: mov w9, #65472
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: movk w9, #18559, lsl #16
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fmaxnm s1, s0, s1
-; CHECK-NEXT: fmov s2, w9
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w9, s0
+; CHECK-NEXT: mov w8, #-262144
+; CHECK-NEXT: cmn w9, #64, lsl #12 // =262144
+; CHECK-NEXT: csel w8, w8, w9, lt
+; CHECK-NEXT: cmp w8, #64, lsl #12 // =262144
+; CHECK-NEXT: mov w9, #262143
+; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: ret
%x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
ret i19 %x
@@ -552,20 +458,8 @@
define i32 @test_signed_i32_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i32_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: mov w8, #1325400063
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel w8, w9, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w0, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w0, s0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
ret i32 %x
@@ -574,20 +468,14 @@
define i50 @test_signed_i50_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i50_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-671088640
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: mov w8, #1476395007
-; CHECK-NEXT: mov x9, #-562949953421312
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: csel x8, x9, x8, lt
+; CHECK-NEXT: mov x8, #-562949953421312
+; CHECK-NEXT: fcvtzs x9, s0
+; CHECK-NEXT: cmp x9, x8
+; CHECK-NEXT: csel x8, x8, x9, lt
; CHECK-NEXT: mov x9, #562949953421311
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel x8, x9, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, gt
; CHECK-NEXT: ret
%x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
ret i50 %x
@@ -596,20 +484,8 @@
define i64 @test_signed_i64_f16(half %f) nounwind {
; CHECK-LABEL: test_signed_i64_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: mov w8, #1593835519
-; CHECK-NEXT: mov x9, #-9223372036854775808
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: csel x8, x9, x8, lt
-; CHECK-NEXT: mov x9, #9223372036854775807
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel x8, x9, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x0, xzr, x8, vs
+; CHECK-NEXT: fcvtzs x0, s0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
ret i64 %x
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -17,31 +17,7 @@
define <1 x i32> @test_signed_v1f32_v1i32(<1 x float> %f) {
; CHECK-LABEL: test_signed_v1f32_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f32.v1i32(<1 x float> %f)
ret <1 x i32> %x
@@ -50,31 +26,7 @@
define <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x
@@ -83,47 +35,7 @@
define <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
; CHECK-LABEL: test_signed_v3f32_v3i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: mov s3, v0.s[2]
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov s1, v0.s[3]
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
ret <3 x i32> %x
@@ -132,47 +44,7 @@
define <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: mov s3, v0.s[2]
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov s1, v0.s[3]
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x
@@ -181,47 +53,21 @@
define <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
; CHECK-LABEL: test_signed_v5f32_v5i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-822083584
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s5, w9
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: mov w10, #-2147483648
-; CHECK-NEXT: fmov s6, w11
-; CHECK-NEXT: fcmp s0, s5
-; CHECK-NEXT: mov w12, #2147483647
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s0, s6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: fcvtzs w13, s1
-; CHECK-NEXT: csel w0, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s5
-; CHECK-NEXT: csel w8, w10, w13, lt
-; CHECK-NEXT: fcmp s1, s6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w14, s2
-; CHECK-NEXT: csel w1, wzr, w8, vs
-; CHECK-NEXT: fcmp s2, s5
-; CHECK-NEXT: csel w8, w10, w14, lt
-; CHECK-NEXT: fcmp s2, s6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fcvtzs w9, s3
-; CHECK-NEXT: csel w2, wzr, w8, vs
-; CHECK-NEXT: fcmp s3, s5
-; CHECK-NEXT: csel w8, w10, w9, lt
-; CHECK-NEXT: fcmp s3, s6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: fcvtzs w11, s4
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: fcmp s4, s5
-; CHECK-NEXT: csel w8, w10, w11, lt
-; CHECK-NEXT: fcmp s4, s6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: csel w4, wzr, w8, vs
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzs v4.4s, v4.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x
@@ -230,57 +76,24 @@
define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_signed_v6f32_v6i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-822083584
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s6, w9
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov w10, #-2147483648
-; CHECK-NEXT: fcmp s5, s6
-; CHECK-NEXT: fmov s7, w11
-; CHECK-NEXT: mov w12, #2147483647
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s5, s7
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: fcvtzs w13, s4
-; CHECK-NEXT: csel w5, wzr, w8, vs
-; CHECK-NEXT: fcmp s4, s6
-; CHECK-NEXT: csel w8, w10, w13, lt
-; CHECK-NEXT: fcmp s4, s7
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvtzs w14, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s6
-; CHECK-NEXT: csel w13, w10, w14, lt
-; CHECK-NEXT: fcmp s0, s7
-; CHECK-NEXT: csel w13, w12, w13, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w0, wzr, w13, vs
-; CHECK-NEXT: fcmp s1, s6
-; CHECK-NEXT: csel w9, w10, w9, lt
-; CHECK-NEXT: fcmp s1, s7
-; CHECK-NEXT: csel w9, w12, w9, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w11, s2
-; CHECK-NEXT: csel w1, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s6
-; CHECK-NEXT: csel w9, w10, w11, lt
-; CHECK-NEXT: fcmp s2, s7
-; CHECK-NEXT: csel w9, w12, w9, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmov s4, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: csel w2, wzr, w9, vs
-; CHECK-NEXT: fcmp s3, s6
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s3, s7
-; CHECK-NEXT: mov v4.s[1], w5
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: fmov w4, s4
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v4.s[1], v5.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzs v1.4s, v4.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x
@@ -289,66 +102,27 @@
define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_signed_v7f32_v7i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #-822083584
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s7, w9
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov w10, #-2147483648
-; CHECK-NEXT: fcmp s5, s7
-; CHECK-NEXT: fmov s16, w11
-; CHECK-NEXT: mov w12, #2147483647
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s5, s16
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: fcvtzs w13, s4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s4, s7
-; CHECK-NEXT: csel w11, w10, w13, lt
-; CHECK-NEXT: fcmp s4, s16
-; CHECK-NEXT: csel w11, w12, w11, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvtzs w14, s6
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s6, s7
-; CHECK-NEXT: csel w14, w10, w14, lt
-; CHECK-NEXT: fcmp s6, s16
-; CHECK-NEXT: csel w14, w12, w14, gt
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: csel w6, wzr, w14, vs
-; CHECK-NEXT: fcmp s0, s7
-; CHECK-NEXT: csel w9, w10, w9, lt
-; CHECK-NEXT: fcmp s0, s16
-; CHECK-NEXT: csel w9, w12, w9, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: fcvtzs w13, s1
-; CHECK-NEXT: csel w0, wzr, w9, vs
-; CHECK-NEXT: fcmp s1, s7
-; CHECK-NEXT: csel w9, w10, w13, lt
-; CHECK-NEXT: fcmp s1, s16
-; CHECK-NEXT: csel w9, w12, w9, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmov s4, w11
-; CHECK-NEXT: fcvtzs w11, s2
-; CHECK-NEXT: csel w1, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s7
-; CHECK-NEXT: csel w9, w10, w11, lt
-; CHECK-NEXT: fcmp s2, s16
-; CHECK-NEXT: csel w9, w12, w9, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov v4.s[1], w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: csel w2, wzr, w9, vs
-; CHECK-NEXT: fcmp s3, s7
-; CHECK-NEXT: csel w8, w10, w8, lt
-; CHECK-NEXT: fcmp s3, s16
-; CHECK-NEXT: mov v4.s[2], w6
-; CHECK-NEXT: csel w8, w12, w8, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: mov w5, v4.s[1]
-; CHECK-NEXT: fmov w4, s4
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v4.s[1], v5.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v4.s[2], v6.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzs v1.4s, v4.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: mov w6, v1.s[2]
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x
@@ -357,82 +131,8 @@
define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w10, #-822083584
-; CHECK-NEXT: mov s3, v0.s[1]
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s2, w10
-; CHECK-NEXT: mov w8, #-2147483648
-; CHECK-NEXT: fmov s5, w11
-; CHECK-NEXT: fcvtzs w11, s3
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s3, s5
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: fcvtzs w10, s0
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s0, s5
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: mov s4, v0.s[2]
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: mov s3, v0.s[3]
-; CHECK-NEXT: fmov s0, w10
-; CHECK-NEXT: fcvtzs w10, s4
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s4, s5
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: mov v0.s[1], w11
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: mov v0.s[2], w10
-; CHECK-NEXT: fcvtzs w10, s3
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s3, s5
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: mov s4, v1.s[1]
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: mov v0.s[3], w10
-; CHECK-NEXT: fcvtzs w10, s4
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s4, s5
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvtzs w11, s1
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s1, s5
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov s3, v1.s[2]
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: mov s4, v1.s[3]
-; CHECK-NEXT: fmov s1, w11
-; CHECK-NEXT: fcvtzs w11, s3
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s3, s5
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: mov v1.s[1], w10
-; CHECK-NEXT: fcvtzs w10, s4
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: csel w8, w8, w10, lt
-; CHECK-NEXT: fcmp s4, s5
-; CHECK-NEXT: csel w8, w9, w8, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: mov v1.s[2], w11
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v1.s[3], w8
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NEXT: ret
%x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
ret <8 x i32> %x
@@ -452,16 +152,7 @@
define <1 x i32> @test_signed_v1f64_v1i32(<1 x double> %f) {
; CHECK-LABEL: test_signed_v1f64_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4476578029606273024
-; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmaxnm d1, d0, d1
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w8, wzr, w8, vs
+; CHECK-NEXT: fcvtzs w8, d0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f64.v1i32(<1 x double> %f)
@@ -473,23 +164,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4476578029606273024
; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x
@@ -499,34 +180,22 @@
; CHECK-LABEL: test_signed_v3f64_v3i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4476578029606273024
-; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d1, d3
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fmaxnm d5, d0, d3
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d1
-; CHECK-NEXT: fminnm d5, d5, d4
-; CHECK-NEXT: fcvtzs w9, d5
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: fmaxnm d1, d2, d3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmaxnm d3, d3, d0
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fminnm d3, d3, d4
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcmp d2, d2
-; CHECK-NEXT: fcvtzs w8, d3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: dup v3.2d, x8
+; CHECK-NEXT: mov x8, #281474972516352
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: movk x8, #16863, lsl #48
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fminnm v1.2d, v2.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f)
ret <3 x i32> %x
@@ -537,35 +206,17 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4476578029606273024
; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: mov d2, v0.d[1]
; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fmaxnm d5, d2, d4
-; CHECK-NEXT: fcmp d2, d2
-; CHECK-NEXT: fmov d2, x9
-; CHECK-NEXT: fminnm d5, d5, d2
-; CHECK-NEXT: fcvtzs w8, d5
-; CHECK-NEXT: fmaxnm d5, d0, d4
-; CHECK-NEXT: fminnm d5, d5, d2
-; CHECK-NEXT: mov d3, v1.d[1]
-; CHECK-NEXT: fcvtzs w9, d5
-; CHECK-NEXT: fmaxnm d5, d1, d4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: fmaxnm d4, d3, d4
-; CHECK-NEXT: fminnm d5, d5, d2
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fminnm d2, d4, d2
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzs w9, d5
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp d3, d3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: dup v2.2d, x8
+; CHECK-NEXT: dup v3.2d, x9
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: fmaxnm v1.2d, v1.2d, v2.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f)
ret <4 x i32> %x
@@ -574,36 +225,35 @@
define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
; CHECK-LABEL: test_signed_v5f64_v5i32:
; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov x8, #-4476578029606273024
; CHECK-NEXT: mov x9, #281474972516352
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d5, x8
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: fmaxnm d0, d0, d5
-; CHECK-NEXT: fmov d6, x9
-; CHECK-NEXT: fmaxnm d7, d1, d5
-; CHECK-NEXT: fminnm d0, d0, d6
-; CHECK-NEXT: fmaxnm d16, d2, d5
-; CHECK-NEXT: fminnm d7, d7, d6
-; CHECK-NEXT: fcvtzs w8, d0
-; CHECK-NEXT: fmaxnm d17, d3, d5
-; CHECK-NEXT: fminnm d16, d16, d6
-; CHECK-NEXT: fcvtzs w9, d7
-; CHECK-NEXT: csel w0, wzr, w8, vs
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d5, d4, d5
-; CHECK-NEXT: fminnm d17, d17, d6
-; CHECK-NEXT: fcvtzs w10, d16
-; CHECK-NEXT: csel w1, wzr, w9, vs
-; CHECK-NEXT: fcmp d2, d2
-; CHECK-NEXT: fminnm d5, d5, d6
-; CHECK-NEXT: fcvtzs w11, d17
-; CHECK-NEXT: csel w2, wzr, w10, vs
-; CHECK-NEXT: fcmp d3, d3
-; CHECK-NEXT: fcvtzs w12, d5
-; CHECK-NEXT: csel w3, wzr, w11, vs
-; CHECK-NEXT: fcmp d4, d4
-; CHECK-NEXT: csel w4, wzr, w12, vs
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: dup v3.2d, x9
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fmaxnm v1.2d, v4.2d, v1.2d
+; CHECK-NEXT: fminnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-NEXT: xtn v2.2s, v2.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: xtn v1.2s, v1.2d
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w3, v2.s[1]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w2, s2
+; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptosi.sat.v5f64.v5i32(<5 x double> %f)
ret <5 x i32> %x
@@ -612,41 +262,38 @@
define <6 x i32> @test_signed_v6f64_v6i32(<6 x double> %f) {
; CHECK-LABEL: test_signed_v6f64_v6i32:
; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov x8, #-4476578029606273024
; CHECK-NEXT: mov x9, #281474972516352
+; CHECK-NEXT: // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d6, x8
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: fmaxnm d0, d0, d6
-; CHECK-NEXT: fmov d7, x9
-; CHECK-NEXT: fmaxnm d16, d1, d6
-; CHECK-NEXT: fminnm d0, d0, d7
-; CHECK-NEXT: fmaxnm d17, d2, d6
-; CHECK-NEXT: fminnm d16, d16, d7
-; CHECK-NEXT: fcvtzs w8, d0
-; CHECK-NEXT: fmaxnm d18, d3, d6
-; CHECK-NEXT: fminnm d17, d17, d7
-; CHECK-NEXT: fcvtzs w9, d16
-; CHECK-NEXT: csel w0, wzr, w8, vs
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d19, d4, d6
-; CHECK-NEXT: fminnm d18, d18, d7
-; CHECK-NEXT: fcvtzs w10, d17
-; CHECK-NEXT: csel w1, wzr, w9, vs
-; CHECK-NEXT: fcmp d2, d2
-; CHECK-NEXT: fmaxnm d6, d5, d6
-; CHECK-NEXT: fminnm d19, d19, d7
-; CHECK-NEXT: fcvtzs w11, d18
-; CHECK-NEXT: csel w2, wzr, w10, vs
-; CHECK-NEXT: fcmp d3, d3
-; CHECK-NEXT: fminnm d6, d6, d7
-; CHECK-NEXT: fcvtzs w12, d19
-; CHECK-NEXT: csel w3, wzr, w11, vs
-; CHECK-NEXT: fcmp d4, d4
-; CHECK-NEXT: fcvtzs w13, d6
-; CHECK-NEXT: csel w4, wzr, w12, vs
-; CHECK-NEXT: fcmp d5, d5
-; CHECK-NEXT: csel w5, wzr, w13, vs
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: dup v3.2d, x9
+; CHECK-NEXT: fmaxnm v4.2d, v4.2d, v1.2d
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fminnm v1.2d, v4.2d, v3.2d
+; CHECK-NEXT: fminnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v1.2s, v1.2d
+; CHECK-NEXT: xtn v2.2s, v2.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w3, v2.s[1]
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w2, s2
+; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptosi.sat.v6f64.v6i32(<6 x double> %f)
ret <6 x i32> %x
@@ -984,20 +631,8 @@
define <1 x i32> @test_signed_v1f16_v1i32(<1 x half> %f) {
; CHECK-LABEL: test_signed_v1f16_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: mov w8, #1325400063
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: fmov s1, w8
; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csel w8, w9, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
@@ -1007,32 +642,8 @@
define <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w10
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f16.v2i32(<2 x half> %f)
@@ -1042,52 +653,8 @@
define <3 x i32> @test_signed_v3f16_v3i32(<3 x half> %f) {
; CHECK-LABEL: test_signed_v3f16_v3i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w10, s2
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov v0.s[2], w10
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptosi.sat.v3f16.v3i32(<3 x half> %f)
ret <3 x i32> %x
@@ -1096,52 +663,8 @@
define <4 x i32> @test_signed_v4f16_v4i32(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w10, s2
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov v0.s[2], w10
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
ret <4 x i32> %x
@@ -1150,56 +673,15 @@
define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
; CHECK-LABEL: test_signed_v5f16_v5i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fcvtzs w12, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w8, w9, w12, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w0, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w1, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w2, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w12, s0
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w12, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w4, wzr, w8, vs
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
ret <5 x i32> %x
@@ -1208,68 +690,16 @@
define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
; CHECK-LABEL: test_signed_v6f16_v6i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov h2, v1.h[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w5, wzr, w8, vs
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w8, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w10, s2
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs w12, s1
-; CHECK-NEXT: csel w0, wzr, w10, vs
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h2, v0.h[2]
-; CHECK-NEXT: csel w10, w9, w12, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w13, s2
-; CHECK-NEXT: csel w1, wzr, w10, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: csel w10, w9, w13, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w2, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s4
-; CHECK-NEXT: mov v1.s[1], w5
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v0.s[1]
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
ret <6 x i32> %x
@@ -1278,79 +708,17 @@
define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
; CHECK-LABEL: test_signed_v7f16_v7i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov w10, #-822083584
-; CHECK-NEXT: mov h4, v3.h[1]
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fmov s2, w10
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: mov w8, #-2147483648
-; CHECK-NEXT: fmov s1, w11
-; CHECK-NEXT: fcvtzs w10, s4
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s4, s1
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvt s4, h3
-; CHECK-NEXT: fcvtzs w11, s4
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s4, s1
-; CHECK-NEXT: mov h3, v3.h[2]
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvtzs w12, s3
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: csel w12, w8, w12, lt
-; CHECK-NEXT: fcmp s3, s1
-; CHECK-NEXT: fcvt s4, h0
-; CHECK-NEXT: csel w12, w9, w12, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: fcvtzs w13, s4
-; CHECK-NEXT: csel w6, wzr, w12, vs
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: csel w12, w8, w13, lt
-; CHECK-NEXT: fcmp s4, s1
-; CHECK-NEXT: csel w12, w9, w12, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvtzs w13, s3
-; CHECK-NEXT: csel w0, wzr, w12, vs
-; CHECK-NEXT: fcmp s3, s2
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: csel w12, w8, w13, lt
-; CHECK-NEXT: fcmp s3, s1
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: csel w12, w9, w12, gt
-; CHECK-NEXT: fcmp s3, s3
-; CHECK-NEXT: fmov s3, w11
-; CHECK-NEXT: fcvtzs w11, s4
-; CHECK-NEXT: csel w1, wzr, w12, vs
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s4, s1
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: mov v3.s[1], w10
-; CHECK-NEXT: fcvtzs w10, s0
-; CHECK-NEXT: csel w2, wzr, w11, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w8, w10, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: mov v3.s[2], w6
-; CHECK-NEXT: csel w8, w9, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w3, wzr, w8, vs
-; CHECK-NEXT: mov w5, v3.s[1]
-; CHECK-NEXT: fmov w4, s3
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v0.s[1]
+; CHECK-NEXT: mov w6, v0.s[2]
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
ret <7 x i32> %x
@@ -1359,91 +727,10 @@
define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w10, #-822083584
-; CHECK-NEXT: mov w11, #1325400063
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: mov w8, #-2147483648
-; CHECK-NEXT: fmov s2, w11
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov w9, #2147483647
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvt s4, h0
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w11, s4
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s4, s3
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: ext v6.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: fmov s0, w11
-; CHECK-NEXT: fcvtzs w11, s5
-; CHECK-NEXT: fcmp s5, s3
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s5, s2
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h4, v6.h[1]
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: mov v0.s[2], w11
-; CHECK-NEXT: fcvtzs w11, s4
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s4, s3
-; CHECK-NEXT: csel w11, w8, w11, lt
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: fcvt s1, h6
-; CHECK-NEXT: csel w11, w9, w11, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: mov v0.s[3], w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: csel w11, wzr, w11, vs
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov h4, v6.h[2]
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fmov s1, w10
-; CHECK-NEXT: fcvtzs w10, s4
-; CHECK-NEXT: fcmp s4, s3
-; CHECK-NEXT: mov h5, v6.h[3]
-; CHECK-NEXT: csel w10, w8, w10, lt
-; CHECK-NEXT: fcmp s4, s2
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: csel w10, w9, w10, gt
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: mov v1.s[1], w11
-; CHECK-NEXT: fcvtzs w11, s5
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s5, s3
-; CHECK-NEXT: csel w8, w8, w11, lt
-; CHECK-NEXT: fcmp s5, s2
-; CHECK-NEXT: csel w8, w9, w8, gt
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v1.s[2], w10
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v1.s[3], w8
+; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
ret <8 x i32> %x
@@ -1466,23 +753,11 @@
define <2 x i1> @test_signed_v2f32_v2i1(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: fmov s2, #-1.00000000
-; CHECK-NEXT: fmov s3, wzr
-; CHECK-NEXT: fmaxnm s4, s1, s2
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmaxnm s1, s0, s2
-; CHECK-NEXT: fminnm s2, s4, s3
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmov v1.2s, #-1.00000000
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptosi.sat.v2f32.v2i1(<2 x float> %f)
ret <2 x i1> %x
@@ -1491,25 +766,12 @@
define <2 x i8> @test_signed_v2f32_v2i8(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-1023410176
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w9, #1123942400
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fmaxnm s3, s1, s2
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmaxnm s1, s0, s2
-; CHECK-NEXT: fminnm s2, s3, s4
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: movi v1.2s, #195, lsl #24
+; CHECK-NEXT: mov w8, #1123942400
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptosi.sat.v2f32.v2i8(<2 x float> %f)
ret <2 x i8> %x
@@ -1520,24 +782,12 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-981467136
; CHECK-NEXT: mov w9, #61440
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
; CHECK-NEXT: movk w9, #17791, lsl #16
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fmaxnm s3, s1, s2
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmaxnm s1, s0, s2
-; CHECK-NEXT: fminnm s2, s3, s4
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w9
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptosi.sat.v2f32.v2i13(<2 x float> %f)
ret <2 x i13> %x
@@ -1546,26 +796,13 @@
define <2 x i16> @test_signed_v2f32_v2i16(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312
-; CHECK-NEXT: mov w9, #65024
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: movk w9, #18175, lsl #16
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fmaxnm s3, s1, s2
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmaxnm s1, s0, s2
-; CHECK-NEXT: fminnm s2, s3, s4
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov w8, #65024
+; CHECK-NEXT: movi v1.2s, #199, lsl #24
+; CHECK-NEXT: movk w8, #18175, lsl #16
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptosi.sat.v2f32.v2i16(<2 x float> %f)
ret <2 x i16> %x
@@ -1576,24 +813,12 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-931135488
; CHECK-NEXT: mov w9, #65472
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
; CHECK-NEXT: movk w9, #18559, lsl #16
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fmaxnm s3, s1, s2
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmaxnm s1, s0, s2
-; CHECK-NEXT: fminnm s2, s3, s4
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w9
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f)
ret <2 x i19> %x
@@ -1602,31 +827,7 @@
define <2 x i32> @test_signed_v2f32_v2i32_duplicate(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i32_duplicate:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w8, s0
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w10
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzs v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x
@@ -1635,30 +836,15 @@
define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i50:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-671088640
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1476395007
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov x9, #-562949953421312
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov x11, #562949953421311
-; CHECK-NEXT: csel x10, x9, x10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel x10, x11, x10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: csel x10, xzr, x10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel x8, x9, x8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x8, xzr, x8, vs
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: mov v0.d[1], x10
+; CHECK-NEXT: mov x8, #-4395513236313604096
+; CHECK-NEXT: mov x9, #-16
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: movk x9, #17151, lsl #48
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i50> @llvm.fptosi.sat.v2f32.v2i50(<2 x float> %f)
ret <2 x i50> %x
@@ -1667,30 +853,8 @@
define <2 x i64> @test_signed_v2f32_v2i64(<2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-553648128
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w10, #1593835519
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov x9, #-9223372036854775808
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov x11, #9223372036854775807
-; CHECK-NEXT: csel x10, x9, x10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel x10, x11, x10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs x8, s0
-; CHECK-NEXT: csel x10, xzr, x10, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel x8, x9, x8, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x8, xzr, x8, vs
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: mov v0.d[1], x10
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f32.v2i64(<2 x float> %f)
ret <2 x i64> %x
@@ -1847,22 +1011,12 @@
define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fmov d2, #-1.00000000
-; CHECK-NEXT: fmov d3, xzr
-; CHECK-NEXT: fmaxnm d4, d1, d2
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d4, d3
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmov v1.2d, #-1.00000000
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptosi.sat.v2f64.v2i1(<2 x double> %f)
ret <2 x i1> %x
@@ -1873,23 +1027,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4584664420663164928
; CHECK-NEXT: mov x9, #211106232532992
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16479, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptosi.sat.v2f64.v2i8(<2 x double> %f)
ret <2 x i8> %x
@@ -1900,23 +1044,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4562146422526312448
; CHECK-NEXT: mov x9, #279275953455104
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16559, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptosi.sat.v2f64.v2i13(<2 x double> %f)
ret <2 x i13> %x
@@ -1927,23 +1061,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4548635623644200960
; CHECK-NEXT: mov x9, #281200098803712
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16607, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptosi.sat.v2f64.v2i16(<2 x double> %f)
ret <2 x i16> %x
@@ -1954,23 +1078,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4535124824762089472
; CHECK-NEXT: mov x9, #281440616972288
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16655, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f)
ret <2 x i19> %x
@@ -1981,23 +1095,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4476578029606273024
; CHECK-NEXT: mov x9, #281474972516352
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #16863, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs w8, d2
-; CHECK-NEXT: fcvtzs w9, d1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x
@@ -2008,22 +1112,12 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-4395513236313604096
; CHECK-NEXT: mov x9, #-16
-; CHECK-NEXT: mov d1, v0.d[1]
; CHECK-NEXT: movk x9, #17151, lsl #48
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fmaxnm d3, d1, d2
-; CHECK-NEXT: fmov d4, x9
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fmaxnm d1, d0, d2
-; CHECK-NEXT: fminnm d2, d3, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzs x8, d2
-; CHECK-NEXT: fcvtzs x9, d1
-; CHECK-NEXT: csel x8, xzr, x8, vs
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel x9, xzr, x9, vs
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x9
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
ret <2 x i50> %x
@@ -2032,29 +1126,7 @@
define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-4332462841530417152
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: mov x10, #4890909195324358655
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: mov x9, #-9223372036854775808
-; CHECK-NEXT: fmov d3, x10
-; CHECK-NEXT: fcvtzs x10, d1
-; CHECK-NEXT: fcmp d1, d2
-; CHECK-NEXT: mov x11, #9223372036854775807
-; CHECK-NEXT: csel x10, x9, x10, lt
-; CHECK-NEXT: fcmp d1, d3
-; CHECK-NEXT: csel x10, x11, x10, gt
-; CHECK-NEXT: fcmp d1, d1
-; CHECK-NEXT: fcvtzs x8, d0
-; CHECK-NEXT: csel x10, xzr, x10, vs
-; CHECK-NEXT: fcmp d0, d2
-; CHECK-NEXT: csel x8, x9, x8, lt
-; CHECK-NEXT: fcmp d0, d3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp d0, d0
-; CHECK-NEXT: csel x8, xzr, x8, vs
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: mov v0.d[1], x10
+; CHECK-NEXT: fcvtzs v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
@@ -2209,41 +1281,13 @@
define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s2, #-1.00000000
-; CHECK-NEXT: fcvt s4, h0
-; CHECK-NEXT: fmov s3, wzr
-; CHECK-NEXT: fmaxnm s5, s4, s2
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fminnm s5, s5, s3
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s6, h0
-; CHECK-NEXT: fmaxnm s0, s1, s2
-; CHECK-NEXT: fminnm s0, s0, s3
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: fmaxnm s0, s5, s2
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp s4, s4
-; CHECK-NEXT: fmaxnm s1, s6, s2
-; CHECK-NEXT: fminnm s2, s0, s3
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.h[1], w9
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, vs
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fmov v1.4s, #-1.00000000
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i1> @llvm.fptosi.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -2252,43 +1296,14 @@
define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-1023410176
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov w9, #1123942400
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fmaxnm s5, s2, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fminnm s5, s5, s4
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s6, h0
-; CHECK-NEXT: fmaxnm s0, s1, s3
-; CHECK-NEXT: fminnm s0, s0, s4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: fmaxnm s0, s5, s3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmaxnm s1, s6, s3
-; CHECK-NEXT: fminnm s3, s0, s4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.h[1], w9
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, vs
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.4s, #195, lsl #24
+; CHECK-NEXT: mov w8, #1123942400
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i8> @llvm.fptosi.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -2299,42 +1314,14 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-981467136
; CHECK-NEXT: mov w9, #61440
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: movk w9, #17791, lsl #16
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fmaxnm s5, s2, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fminnm s5, s5, s4
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s6, h0
-; CHECK-NEXT: fmaxnm s0, s1, s3
-; CHECK-NEXT: fminnm s0, s0, s4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: fmaxnm s0, s5, s3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmaxnm s1, s6, s3
-; CHECK-NEXT: fminnm s3, s0, s4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.h[1], w9
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, vs
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w9
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i13> @llvm.fptosi.sat.v4f16.v4i13(<4 x half> %f)
ret <4 x i13> %x
@@ -2343,44 +1330,15 @@
define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-956301312
-; CHECK-NEXT: mov w9, #65024
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: movk w9, #18175, lsl #16
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fmaxnm s5, s2, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fminnm s5, s5, s4
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s6, h0
-; CHECK-NEXT: fmaxnm s0, s1, s3
-; CHECK-NEXT: fminnm s0, s0, s4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: fmaxnm s0, s5, s3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmaxnm s1, s6, s3
-; CHECK-NEXT: fminnm s3, s0, s4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.h[1], w9
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, vs
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: mov w8, #65024
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.4s, #199, lsl #24
+; CHECK-NEXT: movk w8, #18175, lsl #16
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
@@ -2391,41 +1349,13 @@
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-931135488
; CHECK-NEXT: mov w9, #65472
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
; CHECK-NEXT: movk w9, #18559, lsl #16
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmov s4, w9
-; CHECK-NEXT: fmaxnm s5, s2, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fminnm s5, s5, s4
-; CHECK-NEXT: fcvtzs w8, s5
-; CHECK-NEXT: mov h5, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvt s6, h0
-; CHECK-NEXT: fmaxnm s0, s1, s3
-; CHECK-NEXT: fminnm s0, s0, s4
-; CHECK-NEXT: fcvt s5, h5
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w9, s0
-; CHECK-NEXT: fmaxnm s0, s5, s3
-; CHECK-NEXT: csel w9, wzr, w9, vs
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: fmaxnm s1, s6, s3
-; CHECK-NEXT: fminnm s3, s0, s4
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fminnm s1, s1, s4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzs w8, s3
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: mov v0.s[1], w9
-; CHECK-NEXT: fcvtzs w9, s1
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s6, s6
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w9
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i19> @llvm.fptosi.sat.v4f16.v4i19(<4 x half> %f)
ret <4 x i19> %x
@@ -2434,52 +1364,8 @@
define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32_duplicate:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #-822083584
-; CHECK-NEXT: mov w10, #1325400063
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: mov w9, #-2147483648
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: fcvtzs w8, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov w11, #2147483647
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs w10, s2
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w10
-; CHECK-NEXT: fcvtzs w10, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel w10, w9, w10, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: csel w10, w11, w10, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzs w8, s2
-; CHECK-NEXT: csel w10, wzr, w10, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: csel w8, w9, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: csel w8, w11, w8, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: mov v0.s[2], w10
-; CHECK-NEXT: csel w8, wzr, w8, vs
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
ret <4 x i32> %x
@@ -2488,48 +1374,36 @@
define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i50:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-671088640
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov w10, #1476395007
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: mov x9, #-562949953421312
-; CHECK-NEXT: fcvtzs x12, s1
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fmov s3, w10
-; CHECK-NEXT: mov x11, #562949953421311
-; CHECK-NEXT: csel x8, x9, x12, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s1, s1
+; CHECK-NEXT: mov x8, #-562949953421312
+; CHECK-NEXT: fcvtzs x10, s1
; CHECK-NEXT: mov h1, v0.h[1]
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: mov x9, #562949953421311
; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: csel x0, xzr, x8, vs
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: csel x8, x9, x10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s1, s1
+; CHECK-NEXT: csel x10, x8, x10, lt
+; CHECK-NEXT: fcvtzs x11, s1
+; CHECK-NEXT: cmp x10, x9
; CHECK-NEXT: mov h1, v0.h[2]
+; CHECK-NEXT: csel x0, x9, x10, gt
+; CHECK-NEXT: cmp x11, x8
; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzs x10, s1
-; CHECK-NEXT: csel x1, xzr, x8, vs
-; CHECK-NEXT: fcmp s1, s2
+; CHECK-NEXT: csel x10, x8, x11, lt
+; CHECK-NEXT: fcvtzs x12, s1
+; CHECK-NEXT: cmp x10, x9
; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: csel x8, x9, x10, lt
-; CHECK-NEXT: fcmp s1, s3
+; CHECK-NEXT: csel x1, x9, x10, gt
+; CHECK-NEXT: cmp x12, x8
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs x12, s0
-; CHECK-NEXT: csel x2, xzr, x8, vs
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel x8, x9, x12, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s0, s0
-; CHECK-NEXT: csel x3, xzr, x8, vs
+; CHECK-NEXT: csel x10, x8, x12, lt
+; CHECK-NEXT: fcvtzs x13, s0
+; CHECK-NEXT: cmp x10, x9
+; CHECK-NEXT: csel x2, x9, x10, gt
+; CHECK-NEXT: cmp x13, x8
+; CHECK-NEXT: csel x8, x8, x13, lt
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x3, x9, x8, gt
; CHECK-NEXT: ret
%x = call <4 x i50> @llvm.fptosi.sat.v4f16.v4i50(<4 x half> %f)
ret <4 x i50> %x
@@ -2539,51 +1413,22 @@
; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #-553648128
-; CHECK-NEXT: mov w10, #1593835519
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: mov x9, #-9223372036854775808
-; CHECK-NEXT: fmov s4, w10
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: mov h2, v0.h[1]
+; CHECK-NEXT: fcvtzs x8, s1
+; CHECK-NEXT: fcvt s1, h2
+; CHECK-NEXT: fmov d2, x8
; CHECK-NEXT: fcvtzs x8, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov x11, #9223372036854775807
-; CHECK-NEXT: csel x8, x9, x8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel x8, x11, x8, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fcvtzs x10, s2
-; CHECK-NEXT: csel x8, xzr, x8, vs
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: csel x10, x9, x10, lt
-; CHECK-NEXT: fcmp s2, s4
+; CHECK-NEXT: mov h1, v0.h[2]
+; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel x10, x11, x10, gt
-; CHECK-NEXT: fcmp s2, s2
-; CHECK-NEXT: csel x10, xzr, x10, vs
-; CHECK-NEXT: fcvtzs x12, s1
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h0, v0.h[2]
-; CHECK-NEXT: csel x12, x9, x12, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s5, h0
-; CHECK-NEXT: csel x12, x11, x12, gt
-; CHECK-NEXT: fcmp s1, s1
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fcvtzs x10, s5
-; CHECK-NEXT: csel x12, xzr, x12, vs
-; CHECK-NEXT: fcmp s5, s3
-; CHECK-NEXT: csel x9, x9, x10, lt
-; CHECK-NEXT: fcmp s5, s4
-; CHECK-NEXT: csel x9, x11, x9, gt
-; CHECK-NEXT: fcmp s5, s5
-; CHECK-NEXT: csel x9, xzr, x9, vs
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: mov v0.d[1], x8
-; CHECK-NEXT: mov v1.d[1], x12
+; CHECK-NEXT: mov v2.d[1], x8
+; CHECK-NEXT: fcvtzs x8, s1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fcvtzs x8, s0
+; CHECK-NEXT: mov v1.d[1], x8
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
@@ -19,11 +19,9 @@
define i1 @test_unsigned_i1_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i1_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, #1.00000000
-; CHECK-NEXT: fminnm s0, s0, s1
; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #1 // =1
+; CHECK-NEXT: csinc w8, w8, wzr, ls
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptoui.sat.i1.f32(float %f)
@@ -33,12 +31,10 @@
define i8 @test_unsigned_i8_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i8_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: mov w8, #1132396544
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #255 // =255
+; CHECK-NEXT: mov w9, #255
+; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f32(float %f)
ret i8 %x
@@ -47,13 +43,10 @@
define i13 @test_unsigned_i13_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i13_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #63488
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #17919, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT: mov w9, #8191
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i13 @llvm.fptoui.sat.i13.f32(float %f)
ret i13 %x
@@ -62,13 +55,10 @@
define i16 @test_unsigned_i16_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i16_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #65280
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i16 @llvm.fptoui.sat.i16.f32(float %f)
ret i16 %x
@@ -77,13 +67,10 @@
define i19 @test_unsigned_i19_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i19_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #65504
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #18687, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT: mov w9, #524287
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
ret i19 %x
@@ -92,13 +79,7 @@
define i32 @test_unsigned_i32_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i32_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1333788671
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
+; CHECK-NEXT: fcvtzu w0, s0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptoui.sat.i32.f32(float %f)
ret i32 %x
@@ -107,14 +88,10 @@
define i50 @test_unsigned_i50_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i50_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1484783615
; CHECK-NEXT: fcvtzu x8, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp s0, s1
; CHECK-NEXT: mov x9, #1125899906842623
-; CHECK-NEXT: csel x0, x9, x8, gt
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%x = call i50 @llvm.fptoui.sat.i50.f32(float %f)
ret i50 %x
@@ -123,13 +100,7 @@
define i64 @test_unsigned_i64_f32(float %f) nounwind {
; CHECK-LABEL: test_unsigned_i64_f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1602224127
-; CHECK-NEXT: fcvtzu x8, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csinv x0, x8, xzr, le
+; CHECK-NEXT: fcvtzu x0, s0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptoui.sat.i64.f32(float %f)
ret i64 %x
@@ -198,11 +169,9 @@
define i1 @test_unsigned_i1_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i1_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, #1.00000000
-; CHECK-NEXT: fminnm d0, d0, d1
; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: cmp w8, #1 // =1
+; CHECK-NEXT: csinc w8, w8, wzr, ls
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptoui.sat.i1.f64(double %f)
@@ -212,13 +181,10 @@
define i8 @test_unsigned_i8_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i8_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #246290604621824
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16495, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
-; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: cmp w8, #255 // =255
+; CHECK-NEXT: mov w9, #255
+; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f64(double %f)
ret i8 %x
@@ -227,13 +193,10 @@
define i13 @test_unsigned_i13_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i13_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #280375465082880
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16575, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
-; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT: mov w9, #8191
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i13 @llvm.fptoui.sat.i13.f64(double %f)
ret i13 %x
@@ -242,13 +205,10 @@
define i16 @test_unsigned_i16_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i16_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #281337537757184
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
-; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i16 @llvm.fptoui.sat.i16.f64(double %f)
ret i16 %x
@@ -257,13 +217,10 @@
define i19 @test_unsigned_i19_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i19_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #281457796841472
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16671, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
-; CHECK-NEXT: fcvtzu w0, d0
+; CHECK-NEXT: fcvtzu w8, d0
+; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT: mov w9, #524287
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
ret i19 %x
@@ -272,12 +229,6 @@
define i32 @test_unsigned_i32_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i32_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
; CHECK-NEXT: fcvtzu w0, d0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptoui.sat.i32.f64(double %f)
@@ -287,13 +238,10 @@
define i50 @test_unsigned_i50_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i50_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-8
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #17167, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
-; CHECK-NEXT: fcvtzu x0, d0
+; CHECK-NEXT: fcvtzu x8, d0
+; CHECK-NEXT: mov x9, #1125899906842623
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
ret i50 %x
@@ -302,13 +250,7 @@
define i64 @test_unsigned_i64_f64(double %f) nounwind {
; CHECK-LABEL: test_unsigned_i64_f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x9, #4895412794951729151
-; CHECK-NEXT: fcvtzu x8, d0
-; CHECK-NEXT: fcmp d0, #0.0
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp d0, d1
-; CHECK-NEXT: csinv x0, x8, xzr, le
+; CHECK-NEXT: fcvtzu x0, d0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
ret i64 %x
@@ -378,11 +320,9 @@
; CHECK-LABEL: test_unsigned_i1_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, #1.00000000
-; CHECK-NEXT: fminnm s0, s0, s1
; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #1 // =1
+; CHECK-NEXT: csinc w8, w8, wzr, ls
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
%x = call i1 @llvm.fptoui.sat.i1.f16(half %f)
@@ -393,12 +333,10 @@
; CHECK-LABEL: test_unsigned_i8_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: mov w8, #1132396544
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #255 // =255
+; CHECK-NEXT: mov w9, #255
+; CHECK-NEXT: csel w0, w9, w8, hi
; CHECK-NEXT: ret
%x = call i8 @llvm.fptoui.sat.i8.f16(half %f)
ret i8 %x
@@ -407,14 +345,11 @@
define i13 @test_unsigned_i13_f16(half %f) nounwind {
; CHECK-LABEL: test_unsigned_i13_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #63488
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #17919, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #2, lsl #12 // =8192
+; CHECK-NEXT: mov w9, #8191
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i13 @llvm.fptoui.sat.i13.f16(half %f)
ret i13 %x
@@ -423,14 +358,11 @@
define i16 @test_unsigned_i16_f16(half %f) nounwind {
; CHECK-LABEL: test_unsigned_i16_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #65280
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #16, lsl #12 // =65536
+; CHECK-NEXT: mov w9, #65535
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i16 @llvm.fptoui.sat.i16.f16(half %f)
ret i16 %x
@@ -439,14 +371,11 @@
define i19 @test_unsigned_i19_f16(half %f) nounwind {
; CHECK-LABEL: test_unsigned_i19_f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #65504
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: movk w8, #18687, lsl #16
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fminnm s0, s0, s1
-; CHECK-NEXT: fcvtzu w0, s0
+; CHECK-NEXT: fcvtzu w8, s0
+; CHECK-NEXT: cmp w8, #128, lsl #12 // =524288
+; CHECK-NEXT: mov w9, #524287
+; CHECK-NEXT: csel w0, w9, w8, hs
; CHECK-NEXT: ret
%x = call i19 @llvm.fptoui.sat.i19.f16(half %f)
ret i19 %x
@@ -456,13 +385,7 @@
; CHECK-LABEL: test_unsigned_i32_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
+; CHECK-NEXT: fcvtzu w0, s0
; CHECK-NEXT: ret
%x = call i32 @llvm.fptoui.sat.i32.f16(half %f)
ret i32 %x
@@ -472,14 +395,10 @@
; CHECK-LABEL: test_unsigned_i50_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov w8, #1484783615
-; CHECK-NEXT: fcvtzu x9, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: csel x8, xzr, x9, lt
-; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: fcvtzu x8, s0
; CHECK-NEXT: mov x9, #1125899906842623
-; CHECK-NEXT: csel x0, x9, x8, gt
+; CHECK-NEXT: cmp x8, x9
+; CHECK-NEXT: csel x0, x9, x8, hi
; CHECK-NEXT: ret
%x = call i50 @llvm.fptoui.sat.i50.f16(half %f)
ret i50 %x
@@ -489,13 +408,7 @@
; CHECK-LABEL: test_unsigned_i64_f16:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov w8, #1602224127
-; CHECK-NEXT: fcvtzu x9, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: csel x8, xzr, x9, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csinv x0, x8, xzr, le
+; CHECK-NEXT: fcvtzu x0, s0
; CHECK-NEXT: ret
%x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
ret i64 %x
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -17,23 +17,7 @@
define <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) {
; CHECK-LABEL: test_unsigned_v1f32_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f)
ret <1 x i32> %x
@@ -42,23 +26,7 @@
define <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x
@@ -67,35 +35,7 @@
define <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
; CHECK-LABEL: test_unsigned_v3f32_v3i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: mov s2, v0.s[2]
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov s1, v0.s[3]
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
ret <3 x i32> %x
@@ -104,35 +44,7 @@
define <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
; CHECK-LABEL: test_unsigned_v4f32_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: mov s2, v0.s[2]
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov s1, v0.s[3]
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
ret <4 x i32> %x
@@ -141,33 +53,21 @@
define <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
; CHECK-LABEL: test_unsigned_v5f32_v5i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1333788671
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s5, w9
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s0, s5
-; CHECK-NEXT: fcvtzu w10, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w10, lt
-; CHECK-NEXT: fcmp s1, s5
-; CHECK-NEXT: fcvtzu w11, s2
-; CHECK-NEXT: csinv w1, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w11, lt
-; CHECK-NEXT: fcmp s2, s5
-; CHECK-NEXT: fcvtzu w12, s3
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: csel w8, wzr, w12, lt
-; CHECK-NEXT: fcmp s3, s5
-; CHECK-NEXT: fcvtzu w9, s4
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: fcmp s4, #0.0
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s4, s5
-; CHECK-NEXT: csinv w4, w8, wzr, le
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzu v4.4s, v4.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w4, s4
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
ret <5 x i32> %x
@@ -176,41 +76,24 @@
define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-LABEL: test_unsigned_v6f32_v6i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1333788671
-; CHECK-NEXT: fcvtzu w8, s5
-; CHECK-NEXT: fcmp s5, #0.0
-; CHECK-NEXT: fmov s6, w9
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s5, s6
-; CHECK-NEXT: fcvtzu w10, s4
-; CHECK-NEXT: csinv w5, w8, wzr, le
-; CHECK-NEXT: fcmp s4, #0.0
-; CHECK-NEXT: csel w8, wzr, w10, lt
-; CHECK-NEXT: fcmp s4, s6
-; CHECK-NEXT: fcvtzu w11, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s4, w8
-; CHECK-NEXT: csel w8, wzr, w11, lt
-; CHECK-NEXT: fcmp s0, s6
-; CHECK-NEXT: fcvtzu w12, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w12, lt
-; CHECK-NEXT: fcmp s1, s6
-; CHECK-NEXT: fcvtzu w13, s2
-; CHECK-NEXT: csinv w1, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w13, lt
-; CHECK-NEXT: fcmp s2, s6
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: mov v4.s[1], w5
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s6
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: fmov w4, s4
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v4.s[1], v5.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzu v1.4s, v4.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x
@@ -219,48 +102,27 @@
define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-LABEL: test_unsigned_v7f32_v7i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w9, #1333788671
-; CHECK-NEXT: fcvtzu w8, s5
-; CHECK-NEXT: fcmp s5, #0.0
-; CHECK-NEXT: fmov s7, w9
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s5, s7
-; CHECK-NEXT: fcvtzu w10, s4
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s4, #0.0
-; CHECK-NEXT: csel w10, wzr, w10, lt
-; CHECK-NEXT: fcmp s4, s7
-; CHECK-NEXT: fcvtzu w11, s6
-; CHECK-NEXT: csinv w10, w10, wzr, le
-; CHECK-NEXT: fcmp s6, #0.0
-; CHECK-NEXT: fmov s4, w10
-; CHECK-NEXT: csel w10, wzr, w11, lt
-; CHECK-NEXT: fcmp s6, s7
-; CHECK-NEXT: fcvtzu w12, s0
-; CHECK-NEXT: csinv w6, w10, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: mov v4.s[1], w8
-; CHECK-NEXT: csel w8, wzr, w12, lt
-; CHECK-NEXT: fcmp s0, s7
-; CHECK-NEXT: fcvtzu w13, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w13, lt
-; CHECK-NEXT: fcmp s1, s7
-; CHECK-NEXT: fcvtzu w14, s2
-; CHECK-NEXT: csinv w1, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w14, lt
-; CHECK-NEXT: fcmp s2, s7
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: mov v4.s[2], w6
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s7
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: mov w5, v4.s[1]
-; CHECK-NEXT: fmov w4, s4
+; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
+; CHECK-NEXT: // kill: def $s4 killed $s4 def $q4
+; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
+; CHECK-NEXT: // kill: def $s5 killed $s5 def $q5
+; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2
+; CHECK-NEXT: // kill: def $s6 killed $s6 def $q6
+; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3
+; CHECK-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-NEXT: mov v4.s[1], v5.s[0]
+; CHECK-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-NEXT: mov v4.s[2], v6.s[0]
+; CHECK-NEXT: mov v0.s[3], v3.s[0]
+; CHECK-NEXT: fcvtzu v1.4s, v4.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: mov w6, v1.s[2]
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w2, v0.s[2]
+; CHECK-NEXT: mov w3, v0.s[3]
+; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x
@@ -269,62 +131,8 @@
define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
; CHECK-LABEL: test_unsigned_v8f32_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov s2, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s4, w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s4
-; CHECK-NEXT: mov s3, v0.s[2]
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov s2, v0.s[3]
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov s3, v1.s[1]
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov v0.s[3], w9
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: mov s2, v1.s[2]
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov s3, v1.s[3]
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov v1.s[1], w9
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: mov v1.s[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v1.s[3], w8
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-NEXT: ret
%x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
ret <8 x i32> %x
@@ -344,12 +152,6 @@
define <1 x i32> @test_unsigned_v1f64_v1i32(<1 x double> %f) {
; CHECK-LABEL: test_unsigned_v1f64_v1i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fminnm d0, d0, d1
; CHECK-NEXT: fcvtzu w8, d0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: ret
@@ -361,19 +163,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x
@@ -382,26 +178,22 @@
define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
; CHECK-LABEL: test_unsigned_v3f64_v3i32:
; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d3, xzr
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: movi v3.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d3
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fmaxnm d1, d1, d3
-; CHECK-NEXT: fmaxnm d2, d2, d3
-; CHECK-NEXT: fmaxnm d3, d3, d0
-; CHECK-NEXT: fminnm d0, d0, d4
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d2, d2, d4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: fminnm d3, d3, d4
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, d2
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: fcvtzu w8, d3
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v3.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtzu v1.2d, v2.2d
+; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f)
ret <3 x i32> %x
@@ -411,27 +203,17 @@
; CHECK-LABEL: test_unsigned_v4f64_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d2, xzr
+; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: mov d3, v0.d[1]
-; CHECK-NEXT: mov d4, v1.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d2
-; CHECK-NEXT: fmaxnm d3, d3, d2
-; CHECK-NEXT: fmaxnm d1, d1, d2
-; CHECK-NEXT: fmaxnm d2, d4, d2
-; CHECK-NEXT: fmov d4, x8
-; CHECK-NEXT: fminnm d0, d0, d4
-; CHECK-NEXT: fminnm d3, d3, d4
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d4
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d3
-; CHECK-NEXT: fminnm d2, d2, d4
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: fcvtzu w8, d2
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: dup v3.2d, x8
+; CHECK-NEXT: fmaxnm v1.2d, v1.2d, v2.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v3.2d
+; CHECK-NEXT: fminnm v1.2d, v1.2d, v3.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: fcvtzu v1.2d, v1.2d
+; CHECK-NEXT: xtn2 v0.4s, v1.2d
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f)
ret <4 x i32> %x
@@ -440,25 +222,34 @@
define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
; CHECK-LABEL: test_unsigned_v5f64_v5i32:
; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d5, xzr
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: movi v5.2d, #0000000000000000
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d5
-; CHECK-NEXT: fmov d6, x8
-; CHECK-NEXT: fmaxnm d1, d1, d5
-; CHECK-NEXT: fmaxnm d2, d2, d5
-; CHECK-NEXT: fmaxnm d3, d3, d5
-; CHECK-NEXT: fmaxnm d4, d4, d5
-; CHECK-NEXT: fminnm d0, d0, d6
-; CHECK-NEXT: fminnm d1, d1, d6
-; CHECK-NEXT: fminnm d2, d2, d6
-; CHECK-NEXT: fminnm d3, d3, d6
-; CHECK-NEXT: fminnm d4, d4, d6
-; CHECK-NEXT: fcvtzu w0, d0
-; CHECK-NEXT: fcvtzu w1, d1
-; CHECK-NEXT: fcvtzu w2, d2
-; CHECK-NEXT: fcvtzu w3, d3
-; CHECK-NEXT: fcvtzu w4, d4
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v3.2d, v4.2d, v5.2d
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v5.2d
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v5.2d
+; CHECK-NEXT: fminnm v3.2d, v3.2d, v1.2d
+; CHECK-NEXT: fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v1.2d, v3.2d
+; CHECK-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v1.2s, v1.2d
+; CHECK-NEXT: xtn v2.2s, v2.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w3, v2.s[1]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w2, s2
+; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptoui.sat.v5f64.v5i32(<5 x double> %f)
ret <5 x i32> %x
@@ -467,28 +258,37 @@
define <6 x i32> @test_unsigned_v6f64_v6i32(<6 x double> %f) {
; CHECK-LABEL: test_unsigned_v6f64_v6i32:
; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d4 killed $d4 def $q4
+; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d6, xzr
+; CHECK-NEXT: // kill: def $d5 killed $d5 def $q5
+; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3
+; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
+; CHECK-NEXT: movi v6.2d, #0000000000000000
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: fmaxnm d0, d0, d6
-; CHECK-NEXT: fmov d7, x8
-; CHECK-NEXT: fmaxnm d1, d1, d6
-; CHECK-NEXT: fmaxnm d2, d2, d6
-; CHECK-NEXT: fmaxnm d3, d3, d6
-; CHECK-NEXT: fmaxnm d4, d4, d6
-; CHECK-NEXT: fmaxnm d5, d5, d6
-; CHECK-NEXT: fminnm d0, d0, d7
-; CHECK-NEXT: fminnm d1, d1, d7
-; CHECK-NEXT: fminnm d2, d2, d7
-; CHECK-NEXT: fminnm d3, d3, d7
-; CHECK-NEXT: fminnm d4, d4, d7
-; CHECK-NEXT: fminnm d5, d5, d7
-; CHECK-NEXT: fcvtzu w0, d0
-; CHECK-NEXT: fcvtzu w1, d1
-; CHECK-NEXT: fcvtzu w2, d2
-; CHECK-NEXT: fcvtzu w3, d3
-; CHECK-NEXT: fcvtzu w4, d4
-; CHECK-NEXT: fcvtzu w5, d5
+; CHECK-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-NEXT: mov v4.d[1], v5.d[0]
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fmaxnm v3.2d, v4.2d, v6.2d
+; CHECK-NEXT: fmaxnm v2.2d, v2.2d, v6.2d
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v6.2d
+; CHECK-NEXT: fminnm v3.2d, v3.2d, v1.2d
+; CHECK-NEXT: fminnm v2.2d, v2.2d, v1.2d
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v1.2d, v3.2d
+; CHECK-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v1.2s, v1.2d
+; CHECK-NEXT: xtn v2.2s, v2.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
+; CHECK-NEXT: mov w1, v0.s[1]
+; CHECK-NEXT: mov w3, v2.s[1]
+; CHECK-NEXT: mov w5, v1.s[1]
+; CHECK-NEXT: fmov w0, s0
+; CHECK-NEXT: fmov w2, s2
+; CHECK-NEXT: fmov w4, s1
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f64.v6i32(<6 x double> %f)
ret <6 x i32> %x
@@ -756,13 +556,7 @@
; CHECK-LABEL: test_unsigned_v1f16_v1i32:
; CHECK: // %bb.0:
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s1
-; CHECK-NEXT: csinv w8, w8, wzr, le
+; CHECK-NEXT: fcvtzu w8, s0
; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: ret
%x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
@@ -772,24 +566,8 @@
define <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
; CHECK-LABEL: test_unsigned_v2f16_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w9
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f)
@@ -799,40 +577,8 @@
define <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) {
; CHECK-LABEL: test_unsigned_v3f16_v3i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f)
ret <3 x i32> %x
@@ -841,40 +587,8 @@
define <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
ret <4 x i32> %x
@@ -883,42 +597,15 @@
define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
; CHECK-LABEL: test_unsigned_v5f16_v5i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: csinv w0, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: csinv w1, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu w10, s0
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w8, wzr, w10, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv w4, w8, wzr, le
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
ret <5 x i32> %x
@@ -927,52 +614,16 @@
define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
; CHECK-LABEL: test_unsigned_v6f16_v6i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov h2, v1.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: csinv w5, w8, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: mov h2, v0.h[2]
-; CHECK-NEXT: fcvtzu w10, s1
-; CHECK-NEXT: csinv w0, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: csel w9, wzr, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvtzu w11, s2
-; CHECK-NEXT: csinv w1, w9, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: csel w8, wzr, w11, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvtzu w12, s0
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: mov v1.s[1], w5
-; CHECK-NEXT: csel w8, wzr, w12, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v0.s[1]
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
ret <6 x i32> %x
@@ -981,61 +632,17 @@
define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
; CHECK-LABEL: test_unsigned_v7f16_v7i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: mov h2, v1.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvt s2, h1
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: mov h1, v1.h[2]
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fcvtzu w10, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w10, wzr, w10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: fcvtzu w11, s2
-; CHECK-NEXT: csinv w6, w10, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w10, wzr, w11, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: mov h2, v0.h[2]
-; CHECK-NEXT: fcvtzu w11, s1
-; CHECK-NEXT: csinv w0, w10, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: csel w10, wzr, w11, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvtzu w12, s2
-; CHECK-NEXT: fmov s1, w9
-; CHECK-NEXT: csinv w1, w10, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: mov v1.s[1], w8
-; CHECK-NEXT: csel w8, wzr, w12, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: fcvtzu w13, s0
-; CHECK-NEXT: csinv w2, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: mov v1.s[2], w6
-; CHECK-NEXT: csel w8, wzr, w13, lt
-; CHECK-NEXT: fcmp s0, s3
-; CHECK-NEXT: csinv w3, w8, wzr, le
-; CHECK-NEXT: mov w5, v1.s[1]
-; CHECK-NEXT: fmov w4, s1
+; CHECK-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: mov w5, v0.s[1]
+; CHECK-NEXT: mov w6, v0.s[2]
+; CHECK-NEXT: mov w1, v1.s[1]
+; CHECK-NEXT: mov w2, v1.s[2]
+; CHECK-NEXT: mov w3, v1.s[3]
+; CHECK-NEXT: fmov w4, s0
+; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
%x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
ret <7 x i32> %x
@@ -1044,71 +651,10 @@
define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s4, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: mov h3, v0.h[2]
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: mov h2, v5.h[1]
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: fcvt s1, h5
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov v0.s[3], w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: mov h2, v5.h[2]
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s4
-; CHECK-NEXT: fcvt s2, h2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov h3, v5.h[3]
-; CHECK-NEXT: fmov s1, w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s4
-; CHECK-NEXT: mov v1.s[1], w9
-; CHECK-NEXT: fcvtzu w9, s3
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s3, #0.0
-; CHECK-NEXT: mov v1.s[2], w8
-; CHECK-NEXT: csel w8, wzr, w9, lt
-; CHECK-NEXT: fcmp s3, s4
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v1.s[3], w8
+; CHECK-NEXT: fcvtl2 v1.4s, v0.8h
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
ret <8 x i32> %x
@@ -1131,19 +677,11 @@
define <2 x i1> @test_unsigned_v2f32_v2i1(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s1, wzr
-; CHECK-NEXT: fmov s2, #1.00000000
-; CHECK-NEXT: mov s3, v0.s[1]
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmaxnm s1, s3, s1
-; CHECK-NEXT: fminnm s0, s0, s2
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: movi d1, #0000000000000000
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fmov v1.2s, #1.00000000
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptoui.sat.v2f32.v2i1(<2 x float> %f)
ret <2 x i1> %x
@@ -1152,20 +690,12 @@
define <2 x i8> @test_unsigned_v2f32_v2i8(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s1, wzr
+; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: mov w8, #1132396544
-; CHECK-NEXT: mov s2, v0.s[1]
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmaxnm s1, s2, s1
-; CHECK-NEXT: fminnm s0, s0, s3
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptoui.sat.v2f32.v2i8(<2 x float> %f)
ret <2 x i8> %x
@@ -1175,20 +705,12 @@
; CHECK-LABEL: test_unsigned_v2f32_v2i13:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #63488
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s1, wzr
+; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: movk w8, #17919, lsl #16
-; CHECK-NEXT: mov s2, v0.s[1]
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmaxnm s1, s2, s1
-; CHECK-NEXT: fminnm s0, s0, s3
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptoui.sat.v2f32.v2i13(<2 x float> %f)
ret <2 x i13> %x
@@ -1198,20 +720,12 @@
; CHECK-LABEL: test_unsigned_v2f32_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65280
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s1, wzr
+; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: mov s2, v0.s[1]
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmaxnm s1, s2, s1
-; CHECK-NEXT: fminnm s0, s0, s3
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptoui.sat.v2f32.v2i16(<2 x float> %f)
ret <2 x i16> %x
@@ -1221,20 +735,12 @@
; CHECK-LABEL: test_unsigned_v2f32_v2i19:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65504
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fmov s1, wzr
+; CHECK-NEXT: movi d1, #0000000000000000
; CHECK-NEXT: movk w8, #18687, lsl #16
-; CHECK-NEXT: mov s2, v0.s[1]
-; CHECK-NEXT: fmaxnm s0, s0, s1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fmaxnm s1, s2, s1
-; CHECK-NEXT: fminnm s0, s0, s3
-; CHECK-NEXT: fcvtzu w8, s0
-; CHECK-NEXT: fminnm s1, s1, s3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: dup v1.2s, w8
+; CHECK-NEXT: fminnm v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
ret <2 x i19> %x
@@ -1243,23 +749,7 @@
define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu w9, s0
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtzu v0.2s, v0.2s
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
ret <2 x i32> %x
@@ -1268,23 +758,14 @@
define <2 x i50> @test_unsigned_v2f32_v2i50(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i50:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1484783615
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu x8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: mov x9, #1125899906842623
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu x10, s0
-; CHECK-NEXT: csel x8, x9, x8, gt
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel x10, xzr, x10, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel x9, x9, x10, gt
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: mov x8, #-8
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: movk x8, #17167, lsl #48
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i50> @llvm.fptoui.sat.v2f32.v2i50(<2 x float> %f)
ret <2 x i50> %x
@@ -1293,22 +774,8 @@
define <2 x i64> @test_unsigned_v2f32_v2i64(<2 x float> %f) {
; CHECK-LABEL: test_unsigned_v2f32_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: mov w8, #1602224127
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fcvtzu x8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu x9, s0
-; CHECK-NEXT: csinv x8, x8, xzr, le
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel x9, xzr, x9, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csinv x9, x9, xzr, le
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
ret <2 x i64> %x
@@ -1433,18 +900,12 @@
define <2 x i1> @test_unsigned_v2f64_v2i1(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d1, xzr
-; CHECK-NEXT: fmov d2, #1.00000000
-; CHECK-NEXT: mov d3, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmaxnm d1, d3, d1
-; CHECK-NEXT: fminnm d0, d0, d2
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fmov v1.2d, #1.00000000
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i1> @llvm.fptoui.sat.v2f64.v2i1(<2 x double> %f)
ret <2 x i1> %x
@@ -1454,19 +915,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i8:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #246290604621824
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16495, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i8> @llvm.fptoui.sat.v2f64.v2i8(<2 x double> %f)
ret <2 x i8> %x
@@ -1476,19 +931,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i13:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #280375465082880
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16575, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i13> @llvm.fptoui.sat.v2f64.v2i13(<2 x double> %f)
ret <2 x i13> %x
@@ -1498,19 +947,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281337537757184
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16623, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i16> @llvm.fptoui.sat.v2f64.v2i16(<2 x double> %f)
ret <2 x i16> %x
@@ -1520,19 +963,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i19:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281457796841472
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16671, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f)
ret <2 x i19> %x
@@ -1542,19 +979,13 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #281474974613504
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #16879, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, d1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
ret <2 x i32> %x
@@ -1564,18 +995,12 @@
; CHECK-LABEL: test_unsigned_v2f64_v2i50:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-8
-; CHECK-NEXT: fmov d1, xzr
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk x8, #17167, lsl #48
-; CHECK-NEXT: mov d2, v0.d[1]
-; CHECK-NEXT: fmaxnm d0, d0, d1
-; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: fmaxnm d1, d2, d1
-; CHECK-NEXT: fminnm d0, d0, d3
-; CHECK-NEXT: fcvtzu x8, d0
-; CHECK-NEXT: fminnm d1, d1, d3
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fcvtzu x8, d1
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: fmaxnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
ret <2 x i50> %x
@@ -1584,21 +1009,7 @@
define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
; CHECK-LABEL: test_unsigned_v2f64_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: mov x8, #4895412794951729151
-; CHECK-NEXT: fmov d2, x8
-; CHECK-NEXT: fcvtzu x8, d1
-; CHECK-NEXT: fcmp d1, #0.0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp d1, d2
-; CHECK-NEXT: fcvtzu x9, d0
-; CHECK-NEXT: csinv x8, x8, xzr, le
-; CHECK-NEXT: fcmp d0, #0.0
-; CHECK-NEXT: csel x9, xzr, x9, lt
-; CHECK-NEXT: fcmp d0, d2
-; CHECK-NEXT: csinv x9, x9, xzr, le
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: mov v0.d[1], x8
+; CHECK-NEXT: fcvtzu v0.2d, v0.2d
; CHECK-NEXT: ret
%x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
ret <2 x i64> %x
@@ -1721,33 +1132,13 @@
define <4 x i1> @test_unsigned_v4f16_v4i1(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fmov s2, wzr
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s1, s1, s2
-; CHECK-NEXT: fmaxnm s3, s3, s2
-; CHECK-NEXT: fmaxnm s4, s4, s2
-; CHECK-NEXT: fmaxnm s0, s0, s2
-; CHECK-NEXT: fmov s2, #1.00000000
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fminnm s1, s3, s2
-; CHECK-NEXT: fminnm s3, s4, s2
-; CHECK-NEXT: fminnm s2, s0, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.h[1], w8
-; CHECK-NEXT: fcvtzu w8, s3
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fmov v1.4s, #1.00000000
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i1> @llvm.fptoui.sat.v4f16.v4i1(<4 x half> %f)
ret <4 x i1> %x
@@ -1756,34 +1147,14 @@
define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fmov s2, wzr
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: mov w8, #1132396544
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s1, s1, s2
-; CHECK-NEXT: fmaxnm s3, s3, s2
-; CHECK-NEXT: fmaxnm s4, s4, s2
-; CHECK-NEXT: fmaxnm s0, s0, s2
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fminnm s1, s3, s2
-; CHECK-NEXT: fminnm s3, s4, s2
-; CHECK-NEXT: fminnm s2, s0, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.h[1], w8
-; CHECK-NEXT: fcvtzu w8, s3
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i8> @llvm.fptoui.sat.v4f16.v4i8(<4 x half> %f)
ret <4 x i8> %x
@@ -1792,35 +1163,15 @@
define <4 x i13> @test_unsigned_v4f16_v4i13(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i13:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fcvt s1, h0
; CHECK-NEXT: mov w8, #63488
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fmov s2, wzr
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk w8, #17919, lsl #16
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s1, s1, s2
-; CHECK-NEXT: fmaxnm s3, s3, s2
-; CHECK-NEXT: fmaxnm s4, s4, s2
-; CHECK-NEXT: fmaxnm s0, s0, s2
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fminnm s1, s3, s2
-; CHECK-NEXT: fminnm s3, s4, s2
-; CHECK-NEXT: fminnm s2, s0, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.h[1], w8
-; CHECK-NEXT: fcvtzu w8, s3
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i13> @llvm.fptoui.sat.v4f16.v4i13(<4 x half> %f)
ret <4 x i13> %x
@@ -1829,35 +1180,15 @@
define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fcvt s1, h0
; CHECK-NEXT: mov w8, #65280
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fmov s2, wzr
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk w8, #18303, lsl #16
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s1, s1, s2
-; CHECK-NEXT: fmaxnm s3, s3, s2
-; CHECK-NEXT: fmaxnm s4, s4, s2
-; CHECK-NEXT: fmaxnm s0, s0, s2
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fminnm s1, s3, s2
-; CHECK-NEXT: fminnm s3, s4, s2
-; CHECK-NEXT: fminnm s2, s0, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.h[1], w8
-; CHECK-NEXT: fcvtzu w8, s3
-; CHECK-NEXT: mov v0.h[2], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: mov v0.h[3], w8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f16.v4i16(<4 x half> %f)
ret <4 x i16> %x
@@ -1866,34 +1197,14 @@
define <4 x i19> @test_unsigned_v4f16_v4i19(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i19:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: fcvt s1, h0
; CHECK-NEXT: mov w8, #65504
-; CHECK-NEXT: mov h3, v0.h[1]
-; CHECK-NEXT: mov h4, v0.h[2]
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fmov s2, wzr
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: movi v1.2d, #0000000000000000
; CHECK-NEXT: movk w8, #18687, lsl #16
-; CHECK-NEXT: fcvt s3, h3
-; CHECK-NEXT: fcvt s4, h4
-; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: fmaxnm s1, s1, s2
-; CHECK-NEXT: fmaxnm s3, s3, s2
-; CHECK-NEXT: fmaxnm s4, s4, s2
-; CHECK-NEXT: fmaxnm s0, s0, s2
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: fminnm s1, s1, s2
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fminnm s1, s3, s2
-; CHECK-NEXT: fminnm s3, s4, s2
-; CHECK-NEXT: fminnm s2, s0, s2
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s3
-; CHECK-NEXT: mov v0.s[2], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: dup v1.4s, w8
+; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i19> @llvm.fptoui.sat.v4f16.v4i19(<4 x half> %f)
ret <4 x i19> %x
@@ -1902,40 +1213,8 @@
define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
; CHECK-LABEL: test_unsigned_v4f16_v4i32_duplicate:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1333788671
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
-; CHECK-NEXT: fcvtzu w8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fcvtzu w9, s2
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: fmov s0, w9
-; CHECK-NEXT: fcvtzu w9, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel w9, wzr, w9, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov v0.s[1], w8
-; CHECK-NEXT: fcvtzu w8, s2
-; CHECK-NEXT: csinv w9, w9, wzr, le
-; CHECK-NEXT: fcmp s2, #0.0
-; CHECK-NEXT: csel w8, wzr, w8, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov v0.s[2], w9
-; CHECK-NEXT: csinv w8, w8, wzr, le
-; CHECK-NEXT: mov v0.s[3], w8
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
; CHECK-NEXT: ret
%x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
ret <4 x i32> %x
@@ -1946,35 +1225,25 @@
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: fcvt s1, h0
-; CHECK-NEXT: mov w8, #1484783615
-; CHECK-NEXT: fcvtzu x10, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fmov s2, w8
-; CHECK-NEXT: csel x8, xzr, x10, lt
-; CHECK-NEXT: fcmp s1, s2
+; CHECK-NEXT: fcvtzu x9, s1
; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov x9, #1125899906842623
; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: mov x8, #1125899906842623
; CHECK-NEXT: fcvtzu x10, s1
-; CHECK-NEXT: csel x0, x9, x8, gt
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: csel x8, xzr, x10, lt
-; CHECK-NEXT: fcmp s1, s2
; CHECK-NEXT: mov h1, v0.h[2]
-; CHECK-NEXT: fcvt s1, h1
; CHECK-NEXT: mov h0, v0.h[3]
-; CHECK-NEXT: fcvtzu x10, s1
-; CHECK-NEXT: csel x1, x9, x8, gt
-; CHECK-NEXT: fcmp s1, #0.0
+; CHECK-NEXT: fcvt s1, h1
+; CHECK-NEXT: cmp x9, x8
; CHECK-NEXT: fcvt s0, h0
-; CHECK-NEXT: csel x8, xzr, x10, lt
-; CHECK-NEXT: fcmp s1, s2
-; CHECK-NEXT: fcvtzu x11, s0
-; CHECK-NEXT: csel x2, x9, x8, gt
-; CHECK-NEXT: fcmp s0, #0.0
-; CHECK-NEXT: csel x8, xzr, x11, lt
-; CHECK-NEXT: fcmp s0, s2
-; CHECK-NEXT: csel x3, x9, x8, gt
+; CHECK-NEXT: fcvtzu x11, s1
+; CHECK-NEXT: csel x0, x8, x9, hi
+; CHECK-NEXT: cmp x10, x8
+; CHECK-NEXT: fcvtzu x12, s0
+; CHECK-NEXT: csel x1, x8, x10, hi
+; CHECK-NEXT: cmp x11, x8
+; CHECK-NEXT: csel x2, x8, x11, hi
+; CHECK-NEXT: cmp x12, x8
+; CHECK-NEXT: csel x3, x8, x12, hi
; CHECK-NEXT: ret
%x = call <4 x i50> @llvm.fptoui.sat.v4f16.v4i50(<4 x half> %f)
ret <4 x i50> %x
@@ -1984,39 +1253,22 @@
; CHECK-LABEL: test_unsigned_v4f16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: mov w8, #1602224127
-; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: fmov s3, w8
+; CHECK-NEXT: fcvt s1, h0
+; CHECK-NEXT: mov h2, v0.h[1]
; CHECK-NEXT: fcvtzu x8, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s2, h0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: mov h1, v0.h[3]
-; CHECK-NEXT: fcvtzu x9, s2
-; CHECK-NEXT: csinv x8, x8, xzr, le
-; CHECK-NEXT: fcmp s2, #0.0
+; CHECK-NEXT: fcvt s1, h2
+; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: fcvtzu x8, s1
+; CHECK-NEXT: mov h1, v0.h[2]
+; CHECK-NEXT: mov h0, v0.h[3]
; CHECK-NEXT: fcvt s1, h1
-; CHECK-NEXT: csel x9, xzr, x9, lt
-; CHECK-NEXT: fcmp s2, s3
-; CHECK-NEXT: mov h0, v0.h[2]
-; CHECK-NEXT: csinv x9, x9, xzr, le
-; CHECK-NEXT: fcvtzu x10, s1
-; CHECK-NEXT: fcmp s1, #0.0
-; CHECK-NEXT: fcvt s4, h0
-; CHECK-NEXT: csel x10, xzr, x10, lt
-; CHECK-NEXT: fcmp s1, s3
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: fcvtzu x9, s4
-; CHECK-NEXT: csinv x10, x10, xzr, le
-; CHECK-NEXT: fcmp s4, #0.0
-; CHECK-NEXT: csel x9, xzr, x9, lt
-; CHECK-NEXT: fcmp s4, s3
-; CHECK-NEXT: csinv x9, x9, xzr, le
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: mov v0.d[1], x8
-; CHECK-NEXT: mov v1.d[1], x10
+; CHECK-NEXT: mov v2.d[1], x8
+; CHECK-NEXT: fcvtzu x8, s1
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: fmov d1, x8
+; CHECK-NEXT: fcvtzu x8, s0
+; CHECK-NEXT: mov v1.d[1], x8
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
%x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
ret <4 x i64> %x