diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -29,10 +29,6 @@ // effects. It may be CSE'd deleted if dead, etc. def IntrNoMem : IntrinsicProperty; -// IntrNoSync - Threads executing the intrinsic will not synchronize using -// memory or other means. -def IntrNoSync : IntrinsicProperty; - // IntrReadMem - This intrinsic only reads from memory. It does not write to // memory and has no other side effects. Therefore, it cannot be moved across // potentially aliasing stores. However, it can be reordered otherwise and can @@ -124,9 +120,15 @@ def IntrNoReturn : IntrinsicProperty; -def IntrNoFree : IntrinsicProperty; +// IntrNoSync - Threads executing the intrinsic will not synchronize using +// memory or other means. Applied by default. +def IntrNoSync : IntrinsicProperty<1>; + +// Applied by default. +def IntrNoFree : IntrinsicProperty<1>; -def IntrWillReturn : IntrinsicProperty; +// Applied by default. +def IntrWillReturn : IntrinsicProperty<1>; // IntrCold - Calls to this intrinsic are cold. // Parallels the cold attribute on LLVM IR functions. @@ -354,6 +356,16 @@ bit isTarget = 0; } +class DefaultIntrinsic ret_types, + list param_types = [], + list intr_properties = [], + string name = "", + list sd_properties = [], + bit disable_default_attributes = 1> + : Intrinsic {} + /// GCCBuiltin - If this intrinsic exactly corresponds to a GCC builtin, this /// specifies the name of the builtin. This provides automatic CBE and CFE /// support. @@ -376,12 +388,12 @@ //===------------------- Garbage Collection Intrinsics --------------------===// // -def int_gcroot : Intrinsic<[], +def int_gcroot : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_gcread : Intrinsic<[llvm_ptr_ty], +def int_gcread : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptrptr_ty], [IntrReadMem, IntrArgMemOnly]>; -def int_gcwrite : Intrinsic<[], +def int_gcwrite : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty], [IntrArgMemOnly, NoCapture>, NoCapture>]>; @@ -391,69 +403,69 @@ // Note these are to support the Objective-C ARC optimizer which wants to // eliminate retain and releases where possible. -def int_objc_autorelease : Intrinsic<[llvm_ptr_ty], +def int_objc_autorelease : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_autoreleasePoolPop : Intrinsic<[], [llvm_ptr_ty]>; -def int_objc_autoreleasePoolPush : Intrinsic<[llvm_ptr_ty], []>; -def int_objc_autoreleaseReturnValue : Intrinsic<[llvm_ptr_ty], +def int_objc_autoreleasePoolPop : DefaultIntrinsic<[], [llvm_ptr_ty]>; +def int_objc_autoreleasePoolPush : DefaultIntrinsic<[llvm_ptr_ty], []>; +def int_objc_autoreleaseReturnValue : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_copyWeak : Intrinsic<[], +def int_objc_copyWeak : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; -def int_objc_destroyWeak : Intrinsic<[], [llvm_ptrptr_ty]>; -def int_objc_initWeak : Intrinsic<[llvm_ptr_ty], +def int_objc_destroyWeak : DefaultIntrinsic<[], [llvm_ptrptr_ty]>; +def int_objc_initWeak : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_objc_loadWeak : Intrinsic<[llvm_ptr_ty], +def int_objc_loadWeak : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptrptr_ty]>; -def int_objc_loadWeakRetained : Intrinsic<[llvm_ptr_ty], +def int_objc_loadWeakRetained : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptrptr_ty]>; -def int_objc_moveWeak : Intrinsic<[], +def int_objc_moveWeak : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; -def int_objc_release : Intrinsic<[], [llvm_ptr_ty]>; -def int_objc_retain : Intrinsic<[llvm_ptr_ty], +def int_objc_release : DefaultIntrinsic<[], [llvm_ptr_ty]>; +def int_objc_retain : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retainAutorelease : Intrinsic<[llvm_ptr_ty], +def int_objc_retainAutorelease : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retainAutoreleaseReturnValue : Intrinsic<[llvm_ptr_ty], +def int_objc_retainAutoreleaseReturnValue : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retainAutoreleasedReturnValue : Intrinsic<[llvm_ptr_ty], +def int_objc_retainAutoreleasedReturnValue : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retainBlock : Intrinsic<[llvm_ptr_ty], +def int_objc_retainBlock : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_storeStrong : Intrinsic<[], +def int_objc_storeStrong : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_objc_storeWeak : Intrinsic<[llvm_ptr_ty], +def int_objc_storeWeak : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptrptr_ty, llvm_ptr_ty]>; -def int_objc_clang_arc_use : Intrinsic<[], +def int_objc_clang_arc_use : DefaultIntrinsic<[], [llvm_vararg_ty]>; -def int_objc_unsafeClaimAutoreleasedReturnValue : Intrinsic<[llvm_ptr_ty], +def int_objc_unsafeClaimAutoreleasedReturnValue : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retainedObject : Intrinsic<[llvm_ptr_ty], +def int_objc_retainedObject : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_unretainedObject : Intrinsic<[llvm_ptr_ty], +def int_objc_unretainedObject : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_unretainedPointer : Intrinsic<[llvm_ptr_ty], +def int_objc_unretainedPointer : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_retain_autorelease : Intrinsic<[llvm_ptr_ty], +def int_objc_retain_autorelease : DefaultIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty]>; -def int_objc_sync_enter : Intrinsic<[llvm_i32_ty], +def int_objc_sync_enter : DefaultIntrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; -def int_objc_sync_exit : Intrinsic<[llvm_i32_ty], +def int_objc_sync_exit : DefaultIntrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; -def int_objc_arc_annotation_topdown_bbstart : Intrinsic<[], +def int_objc_arc_annotation_topdown_bbstart : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; -def int_objc_arc_annotation_topdown_bbend : Intrinsic<[], +def int_objc_arc_annotation_topdown_bbend : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; -def int_objc_arc_annotation_bottomup_bbstart : Intrinsic<[], +def int_objc_arc_annotation_bottomup_bbstart : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; -def int_objc_arc_annotation_bottomup_bbend : Intrinsic<[], +def int_objc_arc_annotation_bottomup_bbend : DefaultIntrinsic<[], [llvm_ptrptr_ty, llvm_ptrptr_ty]>; @@ -466,11 +478,11 @@ def int_frameaddress : Intrinsic<[llvm_anyptr_ty], [llvm_i32_ty], [IntrNoMem, ImmArg>]>; def int_sponentry : Intrinsic<[llvm_anyptr_ty], [], [IntrNoMem]>; -def int_read_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty], +def int_read_register : DefaultIntrinsic<[llvm_anyint_ty], [llvm_metadata_ty], [IntrReadMem], "llvm.read_register">; -def int_write_register : Intrinsic<[], [llvm_metadata_ty, llvm_anyint_ty], +def int_write_register : DefaultIntrinsic<[], [llvm_metadata_ty, llvm_anyint_ty], [], "llvm.write_register">; -def int_read_volatile_register : Intrinsic<[llvm_anyint_ty], [llvm_metadata_ty], +def int_read_volatile_register : DefaultIntrinsic<[llvm_anyint_ty], [llvm_metadata_ty], [IntrHasSideEffects], "llvm.read_volatile_register">; @@ -529,24 +541,21 @@ def int_stackguard : Intrinsic<[llvm_ptr_ty], [], []>; // A counter increment for instrumentation based profiling. -def int_instrprof_increment : Intrinsic<[], +def int_instrprof_increment : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty, - llvm_i32_ty, llvm_i32_ty], - []>; + llvm_i32_ty, llvm_i32_ty]>; // A counter increment with step for instrumentation based profiling. -def int_instrprof_increment_step : Intrinsic<[], +def int_instrprof_increment_step : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty, - llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], - []>; + llvm_i32_ty, llvm_i32_ty, llvm_i64_ty]>; // A call to profile runtime for value profiling of target expressions // through instrumentation based profiling. -def int_instrprof_value_profile : Intrinsic<[], +def int_instrprof_value_profile : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, - llvm_i32_ty], - []>; + llvm_i32_ty]>; def int_call_preallocated_setup : Intrinsic<[llvm_token_ty], [llvm_i32_ty]>; def int_call_preallocated_arg : Intrinsic<[llvm_ptr_ty], [llvm_token_ty, llvm_i32_ty]>; @@ -909,35 +918,34 @@ // The result of eh.typeid.for depends on the enclosing function, but inside a // given function it is 'const' and may be CSE'd etc. -def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; +def int_eh_typeid_for : DefaultIntrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>; -def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>; -def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>; +def int_eh_return_i32 : DefaultIntrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>; +def int_eh_return_i64 : DefaultIntrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>; // eh.exceptionpointer returns the pointer to the exception caught by // the given `catchpad`. -def int_eh_exceptionpointer : Intrinsic<[llvm_anyptr_ty], [llvm_token_ty], +def int_eh_exceptionpointer : DefaultIntrinsic<[llvm_anyptr_ty], [llvm_token_ty], [IntrNoMem]>; // Gets the exception code from a catchpad token. Only used on some platforms. -def int_eh_exceptioncode : Intrinsic<[llvm_i32_ty], [llvm_token_ty], [IntrNoMem]>; +def int_eh_exceptioncode : DefaultIntrinsic<[llvm_i32_ty], [llvm_token_ty], [IntrNoMem]>; // __builtin_unwind_init is an undocumented GCC intrinsic that causes all // callee-saved registers to be saved and restored (regardless of whether they // are used) in the calling function. It is used by libgcc_eh. -def int_eh_unwind_init: Intrinsic<[]>, +def int_eh_unwind_init: DefaultIntrinsic<[]>, GCCBuiltin<"__builtin_unwind_init">; -def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>; +def int_eh_dwarf_cfa : DefaultIntrinsic<[llvm_ptr_ty], [llvm_i32_ty]>; -let IntrProperties = [IntrNoMem] in { - def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>; - def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>; -} -def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>; -def int_eh_sjlj_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; -def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>; -def int_eh_sjlj_setup_dispatch : Intrinsic<[], []>; +def int_eh_sjlj_lsda : DefaultIntrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; +def int_eh_sjlj_callsite : DefaultIntrinsic<[], [llvm_i32_ty], [IntrNoMem]>; + +def int_eh_sjlj_functioncontext : DefaultIntrinsic<[], [llvm_ptr_ty]>; +def int_eh_sjlj_setjmp : DefaultIntrinsic<[llvm_i32_ty], [llvm_ptr_ty]>; +def int_eh_sjlj_longjmp : DefaultIntrinsic<[], [llvm_ptr_ty], [IntrNoReturn]>; +def int_eh_sjlj_setup_dispatch : DefaultIntrinsic<[], []>; //===---------------- Generic Variable Attribute Intrinsics----------------===// // @@ -1224,13 +1232,13 @@ ///===-------------------------- Other Intrinsics --------------------------===// // -def int_trap : Intrinsic<[], [], [IntrNoReturn, IntrCold]>, +def int_trap : DefaultIntrinsic<[], [], [IntrNoReturn, IntrCold]>, GCCBuiltin<"__builtin_trap">; def int_debugtrap : Intrinsic<[]>, GCCBuiltin<"__builtin_debugtrap">; // Support for dynamic deoptimization (or de-specialization) -def int_experimental_deoptimize : Intrinsic<[llvm_any_ty], [llvm_vararg_ty], +def int_experimental_deoptimize : DefaultIntrinsic<[llvm_any_ty], [llvm_vararg_ty], [Throws]>; // Support for speculative runtime guards @@ -1258,7 +1266,7 @@ // Clear cache intrinsic, default to ignore (ie. emit nothing) // maps to void __clear_cache() on supporting platforms -def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], +def int_clear_cache : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [], "llvm.clear_cache">; // Intrinsic to detect whether its argument is a constant. @@ -1403,22 +1411,22 @@ [IntrReadMem, IntrArgMemOnly]>; def int_hwasan_check_memaccess : - Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], + DefaultIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [IntrInaccessibleMemOnly, ImmArg>]>; def int_hwasan_check_memaccess_shortgranules : - Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], + DefaultIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [IntrInaccessibleMemOnly, ImmArg>]>; // Xray intrinsics //===----------------------------------------------------------------------===// // Custom event logging for x-ray. // Takes a pointer to a string and the length of the string. -def int_xray_customevent : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], +def int_xray_customevent : DefaultIntrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem, NoCapture>, ReadOnly>]>; // Typed event logging for x-ray. // Takes a numeric type tag, a pointer to a string and the length of the string. -def int_xray_typedevent : Intrinsic<[], [llvm_i16_ty, llvm_ptr_ty, llvm_i32_ty], +def int_xray_typedevent : DefaultIntrinsic<[], [llvm_i16_ty, llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem, NoCapture>, ReadOnly>]>; //===----------------------------------------------------------------------===// @@ -1428,7 +1436,7 @@ // @llvm.memcpy.element.unordered.atomic.*(dest, src, length, elementsize) def int_memcpy_element_unordered_atomic - : Intrinsic<[], + : DefaultIntrinsic<[], [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i32_ty], [IntrArgMemOnly, IntrWillReturn, NoCapture>, NoCapture>, WriteOnly>, @@ -1436,7 +1444,7 @@ // @llvm.memmove.element.unordered.atomic.*(dest, src, length, elementsize) def int_memmove_element_unordered_atomic - : Intrinsic<[], + : DefaultIntrinsic<[], [llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty, llvm_i32_ty], [IntrArgMemOnly, IntrWillReturn, NoCapture>, NoCapture>, WriteOnly>, @@ -1444,7 +1452,7 @@ // @llvm.memset.element.unordered.atomic.*(dest, value, length, elementsize) def int_memset_element_unordered_atomic - : Intrinsic<[], [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty, llvm_i32_ty], + : DefaultIntrinsic<[], [llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty, llvm_i32_ty], [IntrWriteMem, IntrArgMemOnly, IntrWillReturn, NoCapture>, WriteOnly>, ImmArg>]>; diff --git a/llvm/test/Analysis/BasicAA/cs-cs.ll b/llvm/test/Analysis/BasicAA/cs-cs.ll --- a/llvm/test/Analysis/BasicAA/cs-cs.ll +++ b/llvm/test/Analysis/BasicAA/cs-cs.ll @@ -364,41 +364,42 @@ call void @an_argmemonly_func(i8* %q) #9 [ "unknown"() ] ret void -; CHECK: Just Ref: Ptr: i8* %p <-> call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] -; CHECK: Just Ref: Ptr: i8* %q <-> call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %q <-> call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] -; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] -; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] -; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] -; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: Both ModRef: call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] -; CHECK: Both ModRef: call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] -; CHECK: NoModRef: call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: Both ModRef: call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] -; CHECK: Both ModRef: call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] -; CHECK: Both ModRef (MustAlias): call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] -; CHECK: Both ModRef: call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #8 [ "unknown"() ] -; CHECK: NoModRef: call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #9 [ "unknown"() ] -; CHECK: Both ModRef (MustAlias): call void @an_argmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #10 [ "unknown"() ] +; CHECK: Just Ref: Ptr: i8* %p <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] +; CHECK: Just Ref: Ptr: i8* %q <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] +; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] +; CHECK: NoModRef: Ptr: i8* %q <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] +; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] +; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] +; CHECK: NoModRef: Ptr: i8* %p <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Both ModRef (MustAlias): Ptr: i8* %q <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] +; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] +; CHECK: Just Ref: call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Both ModRef: call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] +; CHECK: Both ModRef: call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] +; CHECK: NoModRef: call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Both ModRef: call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] +; CHECK: Both ModRef: call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] +; CHECK: Both ModRef (MustAlias): call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] <-> call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] +; CHECK: Both ModRef: call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <-> call void @a_readonly_func(i8* %p) #9 [ "unknown"() ] +; CHECK: NoModRef: call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <-> call void @an_inaccessiblememonly_func() #10 [ "unknown"() ] +; CHECK: Both ModRef (MustAlias): call void @an_argmemonly_func(i8* %q) #12 [ "unknown"() ] <-> call void @an_inaccessibleorargmemonly_func(i8* %q) #11 [ "unknown"() ] } -; CHECK: attributes #0 = { argmemonly nounwind willreturn writeonly } -; CHECK-NEXT: attributes #1 = { argmemonly nounwind willreturn } -; CHECK-NEXT: attributes #2 = { noinline nounwind readonly } -; CHECK-NEXT: attributes #3 = { noinline nounwind writeonly } -; CHECK-NEXT: attributes #4 = { nounwind ssp } -; CHECK-NEXT: attributes #5 = { inaccessiblememonly nounwind } -; CHECK-NEXT: attributes #6 = { inaccessiblemem_or_argmemonly nounwind } -; CHECK-NEXT: attributes #7 = { argmemonly nounwind } -; CHECK-NEXT: attributes #8 = { readonly } -; CHECK-NEXT: attributes #9 = { inaccessiblememonly } -; CHECK-NEXT: attributes #10 = { inaccessiblemem_or_argmemonly } -; CHECK-NEXT: attributes #11 = { argmemonly } +; CHECK: attributes #0 = { argmemonly nofree nosync nounwind willreturn writeonly } +; CHECK-NEXT: attributes #1 = { argmemonly nofree nosync nounwind willreturn } +; CHECK-NEXT: attributes #2 = { argmemonly nounwind willreturn } +; CHECK-NEXT: attributes #3 = { noinline nounwind readonly } +; CHECK-NEXT: attributes #4 = { noinline nounwind writeonly } +; CHECK-NEXT: attributes #5 = { nounwind ssp } +; CHECK-NEXT: attributes #6 = { inaccessiblememonly nounwind } +; CHECK-NEXT: attributes #7 = { inaccessiblemem_or_argmemonly nounwind } +; CHECK-NEXT: attributes #8 = { argmemonly nounwind } +; CHECK-NEXT: attributes #9 = { readonly } +; CHECK-NEXT: attributes #10 = { inaccessiblememonly } +; CHECK-NEXT: attributes #11 = { inaccessiblemem_or_argmemonly } +; CHECK-NEXT: attributes #12 = { argmemonly } attributes #0 = { argmemonly nounwind } attributes #1 = { noinline nounwind readonly } diff --git a/llvm/test/Analysis/BasicAA/intrinsics.ll b/llvm/test/Analysis/BasicAA/intrinsics.ll --- a/llvm/test/Analysis/BasicAA/intrinsics.ll +++ b/llvm/test/Analysis/BasicAA/intrinsics.ll @@ -22,6 +22,6 @@ declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>) nounwind readonly declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind -; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn } -; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly } +; CHECK: attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn } +; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly } ; CHECK: attributes [[ATTR]] = { nounwind } diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll b/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll --- a/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll +++ b/llvm/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll @@ -49,7 +49,7 @@ ret void } -; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #3 { +; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #5 { define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind { call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i1 false), !tbaa !2 ret void @@ -63,7 +63,7 @@ ret i32 %t } -; CHECK: define i32 @test3_no(i8* nocapture %p) #5 { +; CHECK: define i32 @test3_no(i8* nocapture %p) #6 { define i32 @test3_no(i8* %p) nounwind { %t = va_arg i8* %p, i32, !tbaa !2 ret i32 %t @@ -77,8 +77,9 @@ ; CHECK: attributes #2 = { nounwind readonly } ; CHECK: attributes #3 = { nounwind } ; CHECK: attributes #4 = { nounwind readnone } -; CHECK: attributes #5 = { nofree norecurse nounwind } -; CHECK: attributes #6 = { argmemonly nounwind willreturn } +; CHECK: attributes #5 = { nofree nounwind } +; CHECK: attributes #6 = { nofree norecurse nounwind } +; CHECK: attributes #7 = { argmemonly nofree nosync nounwind willreturn } ; Root note. !0 = !{ } diff --git a/llvm/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll b/llvm/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll --- a/llvm/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll +++ b/llvm/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll @@ -22,8 +22,8 @@ declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>) nounwind readonly declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>) nounwind -; CHECK: attributes #0 = { argmemonly nounwind readonly willreturn } -; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly } +; CHECK: attributes #0 = { argmemonly nofree nosync nounwind readonly willreturn } +; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly } ; CHECK: attributes [[NUW]] = { nounwind } !0 = !{!"tbaa root"} diff --git a/llvm/test/Bindings/llvm-c/debug_info.ll b/llvm/test/Bindings/llvm-c/debug_info.ll --- a/llvm/test/Bindings/llvm-c/debug_info.ll +++ b/llvm/test/Bindings/llvm-c/debug_info.ll @@ -12,13 +12,13 @@ ; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 0, metadata !41, metadata !DIExpression(DW_OP_constu, 0, DW_OP_stack_value)), !dbg !44 ; CHECK-NEXT: } -; CHECK: ; Function Attrs: nounwind readnone speculatable +; CHECK: ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn ; CHECK-NEXT: declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 -; CHECK: ; Function Attrs: nounwind readnone speculatable +; CHECK: ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn ; CHECK-NEXT: declare void @llvm.dbg.value(metadata, metadata, metadata) #0 -; CHECK: attributes #0 = { nounwind readnone speculatable willreturn } +; CHECK: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK: !llvm.dbg.cu = !{!0} ; CHECK-NEXT: !FooType = !{!28} diff --git a/llvm/test/Bitcode/compatibility-3.6.ll b/llvm/test/Bitcode/compatibility-3.6.ll --- a/llvm/test/Bitcode/compatibility-3.6.ll +++ b/llvm/test/Bitcode/compatibility-3.6.ll @@ -1179,12 +1179,12 @@ ; CHECK: attributes #26 = { sspstrong } ; CHECK: attributes #27 = { uwtable } ; CHECK: attributes #28 = { "cpu"="cortex-a8" } -; CHECK: attributes #29 = { nounwind readnone willreturn } -; CHECK: attributes #30 = { argmemonly nounwind readonly } -; CHECK: attributes #31 = { argmemonly nounwind } -; CHECK: attributes #32 = { nounwind readnone } +; CHECK: attributes #29 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #30 = { nofree nosync nounwind willreturn } +; CHECK: attributes #31 = { argmemonly nounwind readonly } +; CHECK: attributes #32 = { argmemonly nounwind } ; CHECK: attributes #33 = { nounwind readonly } -; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #35 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-3.7.ll b/llvm/test/Bitcode/compatibility-3.7.ll --- a/llvm/test/Bitcode/compatibility-3.7.ll +++ b/llvm/test/Bitcode/compatibility-3.7.ll @@ -1242,12 +1242,12 @@ ; CHECK: attributes #29 = { "thunk" } ; CHECK: attributes #30 = { uwtable } ; CHECK: attributes #31 = { "cpu"="cortex-a8" } -; CHECK: attributes #32 = { nounwind readnone willreturn } -; CHECK: attributes #33 = { argmemonly nounwind readonly } -; CHECK: attributes #34 = { argmemonly nounwind } -; CHECK: attributes #35 = { nounwind readnone } +; CHECK: attributes #32 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #33 = { nofree nosync nounwind willreturn } +; CHECK: attributes #34 = { argmemonly nounwind readonly } +; CHECK: attributes #35 = { argmemonly nounwind } ; CHECK: attributes #36 = { nounwind readonly } -; CHECK: attributes #37 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #37 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #38 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-3.8.ll b/llvm/test/Bitcode/compatibility-3.8.ll --- a/llvm/test/Bitcode/compatibility-3.8.ll +++ b/llvm/test/Bitcode/compatibility-3.8.ll @@ -1552,12 +1552,12 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } -; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #41 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-3.9.ll b/llvm/test/Bitcode/compatibility-3.9.ll --- a/llvm/test/Bitcode/compatibility-3.9.ll +++ b/llvm/test/Bitcode/compatibility-3.9.ll @@ -1625,13 +1625,13 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } ; CHECK: attributes #40 = { writeonly } -; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #42 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-4.0.ll b/llvm/test/Bitcode/compatibility-4.0.ll --- a/llvm/test/Bitcode/compatibility-4.0.ll +++ b/llvm/test/Bitcode/compatibility-4.0.ll @@ -1650,13 +1650,13 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } ; CHECK: attributes #40 = { writeonly } -; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #41 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #42 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-5.0.ll b/llvm/test/Bitcode/compatibility-5.0.ll --- a/llvm/test/Bitcode/compatibility-5.0.ll +++ b/llvm/test/Bitcode/compatibility-5.0.ll @@ -1665,14 +1665,14 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } ; CHECK: attributes #40 = { writeonly } ; CHECK: attributes #41 = { speculatable } -; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #43 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility-6.0.ll b/llvm/test/Bitcode/compatibility-6.0.ll --- a/llvm/test/Bitcode/compatibility-6.0.ll +++ b/llvm/test/Bitcode/compatibility-6.0.ll @@ -1676,14 +1676,14 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } ; CHECK: attributes #40 = { writeonly } ; CHECK: attributes #41 = { speculatable } -; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #42 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #43 = { builtin } ;; Metadata diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll --- a/llvm/test/Bitcode/compatibility.ll +++ b/llvm/test/Bitcode/compatibility.ll @@ -1884,12 +1884,12 @@ ; CHECK: attributes #32 = { norecurse } ; CHECK: attributes #33 = { inaccessiblememonly } ; CHECK: attributes #34 = { inaccessiblemem_or_argmemonly } -; CHECK: attributes #35 = { nounwind readnone willreturn } -; CHECK: attributes #36 = { argmemonly nounwind readonly } -; CHECK: attributes #37 = { argmemonly nounwind } -; CHECK: attributes #38 = { nounwind readnone } +; CHECK: attributes #35 = { nofree nosync nounwind readnone willreturn } +; CHECK: attributes #36 = { nofree nosync nounwind willreturn } +; CHECK: attributes #37 = { argmemonly nounwind readonly } +; CHECK: attributes #38 = { argmemonly nounwind } ; CHECK: attributes #39 = { nounwind readonly } -; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nounwind willreturn } +; CHECK: attributes #40 = { inaccessiblemem_or_argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #41 = { writeonly } ; CHECK: attributes #42 = { speculatable } ; CHECK: attributes #43 = { strictfp } diff --git a/llvm/test/Bitcode/ptest-new.ll b/llvm/test/Bitcode/ptest-new.ll --- a/llvm/test/Bitcode/ptest-new.ll +++ b/llvm/test/Bitcode/ptest-new.ll @@ -23,4 +23,4 @@ declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone ; CHECK: attributes #0 = { nounwind } -; CHECK: attributes #1 = { nounwind readnone } +; CHECK: attributes #1 = { nofree nosync nounwind readnone willreturn } diff --git a/llvm/test/Bitcode/ptest-old.ll b/llvm/test/Bitcode/ptest-old.ll --- a/llvm/test/Bitcode/ptest-old.ll +++ b/llvm/test/Bitcode/ptest-old.ll @@ -24,4 +24,4 @@ declare i32 @llvm.x86.sse41.ptestnzc(<4 x float>, <4 x float>) nounwind readnone ; CHECK: attributes #0 = { nounwind } -; CHECK: attributes #1 = { nounwind readnone } +; CHECK: attributes #1 = { nofree nosync nounwind readnone willreturn } diff --git a/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll b/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll --- a/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll +++ b/llvm/test/Bitcode/upgrade-invariant-group-barrier.ll @@ -13,9 +13,9 @@ ret void } -; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable +; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn ; CHECK: declare i8* @llvm.launder.invariant.group.p0i8(i8*) -; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable +; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn ; CHECK: declare i16* @llvm.launder.invariant.group.p0i16(i16*) declare i8* @llvm.invariant.group.barrier(i8*) declare i8* @llvm.invariant.group.barrier.p0i8(i8*) diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll @@ -98,7 +98,7 @@ ret i32 addrspace(3)* addrspacecast (i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) to i32 addrspace(3)*) } -; HSA: attributes #0 = { argmemonly nounwind willreturn } +; HSA: attributes #0 = { argmemonly nofree nosync nounwind willreturn } ; HSA: attributes #1 = { nounwind } ; HSA: attributes #2 = { nounwind "amdgpu-queue-ptr" } diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll @@ -314,7 +314,7 @@ attributes #2 = { nounwind "target-cpu"="gfx900" } attributes #3 = { nounwind } -; HSA: attributes #0 = { nounwind readnone speculatable willreturn } +; HSA: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn } ; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" } ; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } ; HSA: attributes #3 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -280,7 +280,7 @@ attributes #0 = { nounwind readnone speculatable } attributes #1 = { nounwind } -; HSA: attributes #0 = { nounwind readnone speculatable willreturn } +; HSA: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn } ; HSA: attributes #1 = { nounwind } ; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" } ; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" } diff --git a/llvm/test/Feature/intrinsics.ll b/llvm/test/Feature/intrinsics.ll --- a/llvm/test/Feature/intrinsics.ll +++ b/llvm/test/Feature/intrinsics.ll @@ -69,5 +69,5 @@ ret void } -; CHECK: attributes #0 = { nounwind readnone speculatable willreturn } +; CHECK: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK: attributes #1 = { cold noreturn nounwind } diff --git a/llvm/test/Instrumentation/MemorySanitizer/attributes.ll b/llvm/test/Instrumentation/MemorySanitizer/attributes.ll --- a/llvm/test/Instrumentation/MemorySanitizer/attributes.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/attributes.ll @@ -50,5 +50,5 @@ ; CHECK-NOT: argmemonly ; CHECK-NOT: speculatable -; CHECK: Function Attrs: nounwind readnone willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone willreturn ; CHECK-NEXT: declare void @llvm.donothing diff --git a/llvm/test/Other/invariant.group.ll b/llvm/test/Other/invariant.group.ll --- a/llvm/test/Other/invariant.group.ll +++ b/llvm/test/Other/invariant.group.ll @@ -92,11 +92,11 @@ declare void @useBool(i1) declare void @clobber(i8*) -; CHECK: Function Attrs: inaccessiblememonly nounwind speculatable willreturn{{$}} +; CHECK: Function Attrs: inaccessiblememonly nofree nosync nounwind speculatable willreturn{{$}} ; CHECK-NEXT: declare i8* @llvm.launder.invariant.group.p0i8(i8*) declare i8* @llvm.launder.invariant.group.p0i8(i8*) -; CHECK: Function Attrs: nounwind readnone speculatable willreturn{{$}} +; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn{{$}} ; CHECK-NEXT: declare i8* @llvm.strip.invariant.group.p0i8(i8*) declare i8* @llvm.strip.invariant.group.p0i8(i8*) diff --git a/llvm/test/Reduce/remove-attributes-from-intrinsics.ll b/llvm/test/Reduce/remove-attributes-from-intrinsics.ll --- a/llvm/test/Reduce/remove-attributes-from-intrinsics.ll +++ b/llvm/test/Reduce/remove-attributes-from-intrinsics.ll @@ -26,7 +26,7 @@ ; CHECK-ALL: declare i32 @llvm.uadd.sat.i32(i32, i32) #0 declare i32 @llvm.uadd.sat.i32(i32, i32) #0 -; CHECK-ALL: attributes #0 = { nounwind readnone speculatable willreturn } +; CHECK-ALL: attributes #0 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK-INTERESTINGNESS: attributes #1 = { ; CHECK-INTERESTINGNESS-SAME: "arg4" diff --git a/llvm/test/TableGen/intrin-side-effects.td b/llvm/test/TableGen/intrin-side-effects.td --- a/llvm/test/TableGen/intrin-side-effects.td +++ b/llvm/test/TableGen/intrin-side-effects.td @@ -18,12 +18,12 @@ def IntrNoMem : IntrinsicProperty; def IntrHasSideEffects : IntrinsicProperty; - class Intrinsic ret_types, list param_types = [], list intr_properties = [], string name = "", - list sd_properties = []> : SDPatternOperator { + list sd_properties = [], + bit disable_default_attributes = 0> : SDPatternOperator { string LLVMName = name; string TargetPrefix = ""; list RetTypes = ret_types; @@ -34,6 +34,7 @@ bit isTarget = 0; + bit DisableDefaultAttributes = disable_default_attributes; } // ... this intrinsic. diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll @@ -32,54 +32,54 @@ } define void @no_promote(<4 x i64>* %arg) #1 { -; IS__TUNIT_OPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@no_promote -; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]] -; IS__TUNIT_OPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]] +; IS__TUNIT_OPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@no_promote -; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]] -; IS__TUNIT_NPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]] +; IS__TUNIT_NPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@no_promote -; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]] -; IS__CGSCC_OPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]] +; IS__CGSCC_OPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__CGSCC_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@no_promote -; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4:#.*]] -; IS__CGSCC_NPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5:#.*]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3:#.*]] +; IS__CGSCC_NPM-NEXT: call fastcc void @no_promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4:#.*]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__CGSCC_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -121,56 +121,56 @@ } define void @promote(<4 x i64>* %arg) #0 { -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@promote -; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR2:#.*]] { +; IS__TUNIT_OPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]] -; IS__TUNIT_OPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]] +; IS__TUNIT_OPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__TUNIT_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@promote -; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR2:#.*]] { +; IS__TUNIT_NPM-SAME: (<4 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32 -; IS__TUNIT_NPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR5]] +; IS__TUNIT_NPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR4]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__TUNIT_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@promote -; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR2:#.*]] { +; IS__CGSCC_OPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]] -; IS__CGSCC_OPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR5]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]] +; IS__CGSCC_OPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64>* nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) [[ATTR4]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__CGSCC_OPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@promote -; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR2:#.*]] { +; IS__CGSCC_NPM-SAME: (<4 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <4 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR4]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR3]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* [[TMP]], align 32 -; IS__CGSCC_NPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR5]] +; IS__CGSCC_NPM-NEXT: call fastcc void @promote_avx2(<4 x i64>* noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) [[ATTR4]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* [[TMP2]], align 32 ; IS__CGSCC_NPM-NEXT: store <4 x i64> [[TMP4]], <4 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll @@ -37,56 +37,56 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* %arg) #0 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12:#.*]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7:#.*]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12:#.*]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7:#.*]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12:#.*]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7:#.*]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11:#.*]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6:#.*]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12:#.*]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7:#.*]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -107,7 +107,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1:#.*]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -115,7 +115,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR2:#.*]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR1:#.*]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64 @@ -131,56 +131,56 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg) #1 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3:#.*]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3:#.*]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -201,7 +201,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -209,7 +209,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR2]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR1]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64 @@ -225,56 +225,56 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* %arg) #0 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR1]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR0]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR0]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -319,56 +319,56 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* %arg) #1 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -389,7 +389,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -397,7 +397,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR1]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -411,54 +411,54 @@ define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* %arg) #2 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR4:#.*]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR2:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR4:#.*]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR2:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR2:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR2:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -479,7 +479,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR5:#.*]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -487,7 +487,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR5:#.*]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR2:#.*]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -501,54 +501,54 @@ define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* %arg) #1 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR3]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR1]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR1]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -569,7 +569,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR6:#.*]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR3:#.*]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -577,7 +577,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR6:#.*]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR3:#.*]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64 @@ -593,56 +593,56 @@ define void @avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* %arg) #4 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR7:#.*]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR4:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR7:#.*]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR4:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR7:#.*]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR7:#.*]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR4:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void @@ -663,7 +663,7 @@ ; ; IS________OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________OPM-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR8:#.*]] { +; IS________OPM-SAME: (<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[ARG1:%.*]]) [[ATTR4:#.*]] { ; IS________OPM-NEXT: bb: ; IS________OPM-NEXT: [[TMP:%.*]] = load <8 x i64>, <8 x i64>* [[ARG1]], align 64 ; IS________OPM-NEXT: store <8 x i64> [[TMP]], <8 x i64>* [[ARG]], align 64 @@ -671,7 +671,7 @@ ; ; IS________NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS________NPM-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR8:#.*]] { +; IS________NPM-SAME: (<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[ARG:%.*]], <8 x i64> [[TMP0:%.*]]) [[ATTR4:#.*]] { ; IS________NPM-NEXT: bb: ; IS________NPM-NEXT: [[ARG1_PRIV:%.*]] = alloca <8 x i64>, align 64 ; IS________NPM-NEXT: store <8 x i64> [[TMP0]], <8 x i64>* [[ARG1_PRIV]], align 64 @@ -687,56 +687,56 @@ define void @avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* %arg) #3 { ; -; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR9:#.*]] { +; IS__TUNIT_OPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR3:#.*]] { ; IS__TUNIT_OPM-NEXT: bb: ; IS__TUNIT_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__TUNIT_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__TUNIT_OPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_OPM-NEXT: ret void ; -; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture writeonly [[ARG:%.*]]) [[ATTR9:#.*]] { +; IS__TUNIT_NPM-SAME: (<8 x i64>* nocapture nofree writeonly [[ARG:%.*]]) [[ATTR3:#.*]] { ; IS__TUNIT_NPM-NEXT: bb: ; IS__TUNIT_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__TUNIT_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__TUNIT_NPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__TUNIT_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__TUNIT_NPM-NEXT: ret void ; -; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR9:#.*]] { +; IS__CGSCC_OPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] { ; IS__CGSCC_OPM-NEXT: bb: ; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] -; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64>* nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_OPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_OPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint norecurse nosync nounwind uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly inlinehint nofree norecurse nosync nounwind uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256 -; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR9:#.*]] { +; IS__CGSCC_NPM-SAME: (<8 x i64>* nocapture nofree nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) [[ATTR3:#.*]] { ; IS__CGSCC_NPM-NEXT: bb: ; IS__CGSCC_NPM-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 ; IS__CGSCC_NPM-NEXT: [[TMP3:%.*]] = bitcast <8 x i64>* [[TMP]] to i8* -; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR11]] +; IS__CGSCC_NPM-NEXT: call void @llvm.memset.p0i8.i64(i8* nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP3]], i8 noundef 0, i64 noundef 32, i1 noundef false) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load <8 x i64>, <8 x i64>* [[TMP]], align 64 -; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR12]] +; IS__CGSCC_NPM-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(<8 x i64>* noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) [[ATTR7]] ; IS__CGSCC_NPM-NEXT: [[TMP4:%.*]] = load <8 x i64>, <8 x i64>* [[TMP2]], align 64 ; IS__CGSCC_NPM-NEXT: store <8 x i64> [[TMP4]], <8 x i64>* [[ARG]], align 2 ; IS__CGSCC_NPM-NEXT: ret void diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/thiscall.ll @@ -41,7 +41,7 @@ ; CHECK-NEXT: [[INALLOCA_SAVE:%.*]] = tail call i8* @llvm.stacksave() ; CHECK-NEXT: [[ARGMEM:%.*]] = alloca inalloca <{ [[STRUCT_A:%.*]] }>, align 4 ; CHECK-NEXT: call x86_thiscallcc void @internalfun(%struct.a* noalias nocapture nofree readnone undef, <{ [[STRUCT_A]] }>* inalloca noundef nonnull align 4 dereferenceable(1) [[ARGMEM]]) -; CHECK-NEXT: call void @llvm.stackrestore(i8* [[INALLOCA_SAVE]]) +; CHECK-NEXT: call void @llvm.stackrestore(i8* nofree [[INALLOCA_SAVE]]) ; CHECK-NEXT: ret void ; %inalloca.save = tail call i8* @llvm.stacksave() diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll @@ -152,15 +152,15 @@ ; IS__TUNIT_NPM-NEXT: store i32 1, i32* [[TMP1]], align 8 ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 ; IS__TUNIT_NPM-NEXT: store i64 2, i64* [[TMP4]], align 4 -; IS__TUNIT_NPM-NEXT: [[S_CAST1:%.*]] = bitcast %struct.ss* [[S]] to i32* -; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[S_CAST1]], align 8 -; IS__TUNIT_NPM-NEXT: [[S_0_12:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 -; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = load i64, i64* [[S_0_12]], align 8 -; IS__TUNIT_NPM-NEXT: [[C0:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]]) [[ATTR0]] ; IS__TUNIT_NPM-NEXT: [[S_CAST:%.*]] = bitcast %struct.ss* [[S]] to i32* -; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = load i32, i32* [[S_CAST]], align 32 +; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i32, i32* [[S_CAST]], align 8 ; IS__TUNIT_NPM-NEXT: [[S_0_1:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 -; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = load i64, i64* [[S_0_1]], align 32 +; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = load i64, i64* [[S_0_1]], align 8 +; IS__TUNIT_NPM-NEXT: [[C0:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]]) [[ATTR0]] +; IS__TUNIT_NPM-NEXT: [[S_CAST1:%.*]] = bitcast %struct.ss* [[S]] to i32* +; IS__TUNIT_NPM-NEXT: [[TMP2:%.*]] = load i32, i32* [[S_CAST1]], align 32 +; IS__TUNIT_NPM-NEXT: [[S_0_12:%.*]] = getelementptr [[STRUCT_SS]], %struct.ss* [[S]], i32 0, i32 1 +; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = load i64, i64* [[S_0_12]], align 32 ; IS__TUNIT_NPM-NEXT: [[C1:%.*]] = call i32 @g(i32 [[TMP2]], i64 [[TMP3]]) [[ATTR0]] ; IS__TUNIT_NPM-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]] ; IS__TUNIT_NPM-NEXT: ret i32 [[A]] diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll @@ -34,11 +34,17 @@ } define internal void @bar(%p_t %p) { -; CHECK: Function Attrs: nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@bar -; CHECK-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR1:#.*]] { -; CHECK-NEXT: call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR3:#.*]], [[DBG5:!dbg !.*]] -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@bar +; IS__TUNIT____-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR0]] { +; IS__TUNIT____-NEXT: call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR2:#.*]], [[DBG5:!dbg !.*]] +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@bar +; IS__CGSCC____-SAME: (i16* nocapture nofree readnone [[P:%.*]]) [[ATTR1:#.*]] { +; IS__CGSCC____-NEXT: call void @llvm.dbg.value(metadata i16* [[P]], [[META3:metadata !.*]], metadata !DIExpression()) [[ATTR3:#.*]], [[DBG5:!dbg !.*]] +; IS__CGSCC____-NEXT: ret void ; call void @llvm.dbg.value(metadata %p_t %p, metadata !4, metadata !5), !dbg !6 ret void diff --git a/llvm/test/Transforms/Attributor/dereferenceable-1.ll b/llvm/test/Transforms/Attributor/dereferenceable-1.ll --- a/llvm/test/Transforms/Attributor/dereferenceable-1.ll +++ b/llvm/test/Transforms/Attributor/dereferenceable-1.ll @@ -661,8 +661,8 @@ ; IS__TUNIT_OPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR4:#.*]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]] -; IS__TUNIT_OPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]] -; IS__TUNIT_OPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]] +; IS__TUNIT_OPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]] +; IS__TUNIT_OPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]] ; IS__TUNIT_OPM-NEXT: ret void ; ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn @@ -670,8 +670,8 @@ ; IS__TUNIT_NPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR3:#.*]] { ; IS__TUNIT_NPM-NEXT: entry: ; IS__TUNIT_NPM-NEXT: [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]] -; IS__TUNIT_NPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]] -; IS__TUNIT_NPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]] +; IS__TUNIT_NPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]] +; IS__TUNIT_NPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]] ; IS__TUNIT_NPM-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind @@ -679,8 +679,8 @@ ; IS__CGSCC_OPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR4:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]] -; IS__CGSCC_OPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]] -; IS__CGSCC_OPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]] +; IS__CGSCC_OPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR7:#.*]] +; IS__CGSCC_OPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: ret void ; ; IS__CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn @@ -688,8 +688,8 @@ ; IS__CGSCC_NPM-SAME: (i32* nocapture nofree writeonly [[P:%.*]], i64* nocapture nofree nonnull readonly align 8 dereferenceable(8) [[RANGE:%.*]]) [[ATTR3:#.*]] { ; IS__CGSCC_NPM-NEXT: entry: ; IS__CGSCC_NPM-NEXT: [[TMP0:%.*]] = load i64, i64* [[RANGE]], align 8, [[RNG0:!range !.*]] -; IS__CGSCC_NPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5:#.*]] -; IS__CGSCC_NPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR5]] +; IS__CGSCC_NPM-NEXT: tail call void @fill_range_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6:#.*]] +; IS__CGSCC_NPM-NEXT: tail call void @fill_range_not_inbounds(i32* nocapture nofree writeonly [[P]], i64 [[TMP0]]) [[ATTR6]] ; IS__CGSCC_NPM-NEXT: ret void ; entry: @@ -915,7 +915,7 @@ ; IS__TUNIT_OPM-NEXT: store i32 3, i32* [[PTR]], align 4 ; IS__TUNIT_OPM-NEXT: br label [[IF_END8]] ; IS__TUNIT_OPM: if.else6: -; IS__TUNIT_OPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR5]] +; IS__TUNIT_OPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR6]] ; IS__TUNIT_OPM-NEXT: br label [[IF_END8]] ; IS__TUNIT_OPM: if.end8: ; IS__TUNIT_OPM-NEXT: ret void @@ -942,7 +942,7 @@ ; IS________NPM-NEXT: store i32 3, i32* [[PTR]], align 4 ; IS________NPM-NEXT: br label [[IF_END8]] ; IS________NPM: if.else6: -; IS________NPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR6:#.*]] +; IS________NPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR7:#.*]] ; IS________NPM-NEXT: br label [[IF_END8]] ; IS________NPM: if.end8: ; IS________NPM-NEXT: ret void @@ -969,7 +969,7 @@ ; IS__CGSCC_OPM-NEXT: store i32 3, i32* [[PTR]], align 4 ; IS__CGSCC_OPM-NEXT: br label [[IF_END8]] ; IS__CGSCC_OPM: if.else6: -; IS__CGSCC_OPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR7:#.*]] +; IS__CGSCC_OPM-NEXT: tail call void @rec-branch-2(i32 noundef 1, i32 noundef 1, i32 noundef 1, i32* nocapture nofree writeonly [[PTR]]) [[ATTR8:#.*]] ; IS__CGSCC_OPM-NEXT: br label [[IF_END8]] ; IS__CGSCC_OPM: if.end8: ; IS__CGSCC_OPM-NEXT: ret void @@ -1016,19 +1016,19 @@ ; ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos ; IS__TUNIT_OPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) { -; IS__TUNIT_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR6:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] +; IS__TUNIT_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR7:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] ; IS__TUNIT_OPM-NEXT: call void @unknown() ; IS__TUNIT_OPM-NEXT: ret void ; ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_assume_pos ; IS________NPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) { -; IS________NPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR7:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] +; IS________NPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR8:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] ; IS________NPM-NEXT: call void @unknown() ; IS________NPM-NEXT: ret void ; ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(101) [[ARG1:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(31) [[ARG2:%.*]], i8* nocapture nofree nonnull readnone [[ARG3:%.*]], i8* nocapture nofree readnone dereferenceable_or_null(42) [[ARG4:%.*]]) { -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR8:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR9:#.*]] [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i8* [[ARG1]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] ; IS__CGSCC_OPM-NEXT: call void @unknown() ; IS__CGSCC_OPM-NEXT: ret void ; @@ -1075,54 +1075,54 @@ ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@nonnull_assume_call ; IS__TUNIT_OPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) { ; IS__TUNIT_OPM-NEXT: call void @unknown() -; IS__TUNIT_OPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR7:#.*]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR7]] +; IS__TUNIT_OPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR8:#.*]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]] ; IS__TUNIT_OPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR7]] -; IS__TUNIT_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR7]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]] +; IS__TUNIT_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]] ; IS__TUNIT_OPM-NEXT: call void @unknown() ; IS__TUNIT_OPM-NEXT: ret void ; ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_assume_call ; IS________NPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) { ; IS________NPM-NEXT: call void @unknown() -; IS________NPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR8:#.*]] -; IS________NPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]] +; IS________NPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR9:#.*]] +; IS________NPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]] ; IS________NPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] -; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR8]] -; IS________NPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR8]] +; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]] +; IS________NPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]] ; IS________NPM-NEXT: call void @unknown() ; IS________NPM-NEXT: ret void ; ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_call ; IS__CGSCC_OPM-SAME: (i8* [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* [[ARG3:%.*]], i8* [[ARG4:%.*]]) { ; IS__CGSCC_OPM-NEXT: call void @unknown() -; IS__CGSCC_OPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR9:#.*]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]] +; IS__CGSCC_OPM-NEXT: [[P:%.*]] = call nonnull dereferenceable(101) i32* @unkown_ptr() [[ATTR10:#.*]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR10]] ; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [ "nonnull"(i8* [[ARG3]]), "dereferenceable"(i8* [[ARG1]], i64 1), "dereferenceable"(i8* [[ARG1]], i64 2), "dereferenceable"(i32* [[P]], i64 101), "dereferenceable_or_null"(i8* [[ARG2]], i64 31), "dereferenceable_or_null"(i8* [[ARG4]], i64 42) ] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR9]] -; IS__CGSCC_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR9]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull dereferenceable(2) [[ARG1]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(31) [[ARG2]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* nonnull [[ARG3]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use8(i8* dereferenceable_or_null(42) [[ARG4]]) [[ATTR10]] +; IS__CGSCC_OPM-NEXT: call void @unknown_use32(i32* nonnull dereferenceable(101) [[P]]) [[ATTR10]] ; IS__CGSCC_OPM-NEXT: call void @unknown() ; IS__CGSCC_OPM-NEXT: ret void ; diff --git a/llvm/test/Transforms/Attributor/heap_to_stack.ll b/llvm/test/Transforms/Attributor/heap_to_stack.ll --- a/llvm/test/Transforms/Attributor/heap_to_stack.ll +++ b/llvm/test/Transforms/Attributor/heap_to_stack.ll @@ -392,7 +392,7 @@ ; IS________OPM-LABEL: define {{[^@]+}}@test_lifetime() { ; IS________OPM-NEXT: [[TMP1:%.*]] = tail call noalias i8* @malloc(i64 noundef 4) ; IS________OPM-NEXT: tail call void @no_sync_func(i8* noalias nocapture nofree [[TMP1]]) -; IS________OPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nonnull align 4 dereferenceable(4) [[TMP1]]) +; IS________OPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nofree nonnull align 4 dereferenceable(4) [[TMP1]]) ; IS________OPM-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* ; IS________OPM-NEXT: store i32 10, i32* [[TMP2]], align 4 ; IS________OPM-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 @@ -402,7 +402,7 @@ ; IS________NPM-LABEL: define {{[^@]+}}@test_lifetime() { ; IS________NPM-NEXT: [[TMP1:%.*]] = alloca i8, i64 4, align 1 ; IS________NPM-NEXT: tail call void @no_sync_func(i8* noalias nocapture nofree [[TMP1]]) -; IS________NPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nonnull align 4 dereferenceable(4) [[TMP1]]) +; IS________NPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 4, i8* noalias nocapture nofree nonnull align 4 dereferenceable(4) [[TMP1]]) ; IS________NPM-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32* ; IS________NPM-NEXT: store i32 10, i32* [[TMP2]], align 4 ; IS________NPM-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 diff --git a/llvm/test/Transforms/Attributor/liveness.ll b/llvm/test/Transforms/Attributor/liveness.ll --- a/llvm/test/Transforms/Attributor/liveness.ll +++ b/llvm/test/Transforms/Attributor/liveness.ll @@ -789,7 +789,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree noreturn nosync nounwind ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@test_unreachable ; NOT_CGSCC_NPM-SAME: () [[ATTR0:#.*]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15:#.*]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14:#.*]] ; NOT_CGSCC_NPM-NEXT: call void @test_unreachable() [[ATTR0]] ; NOT_CGSCC_NPM-NEXT: unreachable ; @@ -1018,7 +1018,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a0 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1034,7 +1034,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a1 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1050,7 +1050,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a2 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1066,7 +1066,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a3 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1082,7 +1082,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a4 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1098,7 +1098,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a5 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1114,7 +1114,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a6 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1130,7 +1130,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a7 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1146,7 +1146,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a8 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1162,7 +1162,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a9 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1178,7 +1178,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a10 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1194,7 +1194,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a11 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1210,7 +1210,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a12 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1226,7 +1226,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a13 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1242,7 +1242,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a14 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1258,7 +1258,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_a15 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1274,7 +1274,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b0 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1290,7 +1290,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b1 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1306,7 +1306,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b2 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1322,7 +1322,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b3 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1338,7 +1338,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b4 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1354,7 +1354,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b5 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1370,7 +1370,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b6 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1386,7 +1386,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b7 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1402,7 +1402,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b8 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1418,7 +1418,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b9 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1434,7 +1434,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b10 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1450,7 +1450,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b11 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1466,7 +1466,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b12 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1482,7 +1482,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b13 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1498,7 +1498,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b14 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1514,7 +1514,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_b15 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1530,7 +1530,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c0 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1546,7 +1546,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c1 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1562,7 +1562,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c2 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1578,7 +1578,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c3 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1594,7 +1594,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c4 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1610,7 +1610,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c5 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1626,7 +1626,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c6 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1642,7 +1642,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c7 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1658,7 +1658,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c8 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1674,7 +1674,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c9 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1690,7 +1690,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c10 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1706,7 +1706,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c11 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1722,7 +1722,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c12 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1738,7 +1738,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c13 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1754,7 +1754,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c14 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1770,7 +1770,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_c15 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1786,7 +1786,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d0 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1802,7 +1802,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d1 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1818,7 +1818,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d2 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1834,7 +1834,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d3 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1850,7 +1850,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d4 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1866,7 +1866,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d5 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1882,7 +1882,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d6 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1898,7 +1898,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d7 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1914,7 +1914,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d8 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1930,7 +1930,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d9 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1946,7 +1946,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d10 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1962,7 +1962,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d11 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1978,7 +1978,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d12 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -1994,7 +1994,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d13 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -2010,7 +2010,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d14 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -2026,7 +2026,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@non_dead_d15 ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -2098,7 +2098,7 @@ ; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@useless_arg_sink ; NOT_CGSCC_NPM-SAME: () [[ATTR11]] { -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn @@ -2171,7 +2171,7 @@ ; NOT_CGSCC_NPM-NEXT: i64 10, label [[RETURN]] ; NOT_CGSCC_NPM-NEXT: ] ; NOT_CGSCC_NPM: sw.default: -; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR15]] +; NOT_CGSCC_NPM-NEXT: call void @sink() [[ATTR14]] ; NOT_CGSCC_NPM-NEXT: ret i32 undef ; NOT_CGSCC_NPM: return: ; NOT_CGSCC_NPM-NEXT: unreachable @@ -2509,13 +2509,13 @@ @p = global i8 0 define void @bad_gep() { -; NOT_CGSCC_NPM: Function Attrs: nounwind readnone willreturn +; NOT_CGSCC_NPM: Function Attrs: nofree nosync nounwind readnone willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@bad_gep -; NOT_CGSCC_NPM-SAME: () [[ATTR13:#.*]] { +; NOT_CGSCC_NPM-SAME: () [[ATTR12]] { ; NOT_CGSCC_NPM-NEXT: entry: ; NOT_CGSCC_NPM-NEXT: [[N:%.*]] = alloca i8, align 1 ; NOT_CGSCC_NPM-NEXT: [[M:%.*]] = alloca i8, align 1 -; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR16:#.*]] +; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR15:#.*]] ; NOT_CGSCC_NPM-NEXT: br label [[EXIT:%.*]] ; NOT_CGSCC_NPM: while.body: ; NOT_CGSCC_NPM-NEXT: unreachable @@ -2524,16 +2524,16 @@ ; NOT_CGSCC_NPM: if.end: ; NOT_CGSCC_NPM-NEXT: unreachable ; NOT_CGSCC_NPM: exit: -; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR16]] +; NOT_CGSCC_NPM-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR15]] ; NOT_CGSCC_NPM-NEXT: ret void ; -; IS__CGSCC____: Function Attrs: nounwind readnone willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@bad_gep ; IS__CGSCC____-SAME: () [[ATTR14:#.*]] { ; IS__CGSCC____-NEXT: entry: ; IS__CGSCC____-NEXT: [[N:%.*]] = alloca i8, align 1 ; IS__CGSCC____-NEXT: [[M:%.*]] = alloca i8, align 1 -; IS__CGSCC____-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR17:#.*]] +; IS__CGSCC____-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR17:#.*]] ; IS__CGSCC____-NEXT: br label [[EXIT:%.*]] ; IS__CGSCC____: while.body: ; IS__CGSCC____-NEXT: unreachable @@ -2542,7 +2542,7 @@ ; IS__CGSCC____: if.end: ; IS__CGSCC____-NEXT: unreachable ; IS__CGSCC____: exit: -; IS__CGSCC____-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture noundef nonnull dereferenceable(1) [[N]]) [[ATTR17]] +; IS__CGSCC____-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 1, i8* noalias nocapture nofree noundef nonnull dereferenceable(1) [[N]]) [[ATTR17]] ; IS__CGSCC____-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/Attributor/noalias.ll b/llvm/test/Transforms/Attributor/noalias.ll --- a/llvm/test/Transforms/Attributor/noalias.ll +++ b/llvm/test/Transforms/Attributor/noalias.ll @@ -577,11 +577,11 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: [[F:%.*]] = alloca [[STRUCT__IO_FILE:%.*]], align 8 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast %struct._IO_FILE* [[F]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture noundef nonnull align 8 dereferenceable(240) [[TMP0]]) [[ATTR10:#.*]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) [[ATTR10:#.*]] ; CHECK-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @sh_fromstring to i32 (%struct._IO_FILE*, i8*)*)(%struct._IO_FILE* nonnull align 8 dereferenceable(240) [[F]], i8* [[S]]) ; CHECK-NEXT: call void @__shlim(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i64 noundef 0) ; CHECK-NEXT: [[CALL1:%.*]] = call double @__floatscan(%struct._IO_FILE* noundef nonnull align 8 dereferenceable(240) [[F]], i32 noundef 1, i32 noundef 1) -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture noundef nonnull align 8 dereferenceable(240) [[TMP0]]) +; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 noundef 144, i8* nocapture nofree noundef nonnull align 8 dereferenceable(240) [[TMP0]]) ; CHECK-NEXT: ret double [[CALL1]] ; entry: diff --git a/llvm/test/Transforms/Attributor/nocapture-1.ll b/llvm/test/Transforms/Attributor/nocapture-1.ll --- a/llvm/test/Transforms/Attributor/nocapture-1.ll +++ b/llvm/test/Transforms/Attributor/nocapture-1.ll @@ -215,7 +215,7 @@ ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@c7 ; IS__TUNIT____-SAME: (i32* nofree readonly [[Q:%.*]], i32 [[BITNO:%.*]]) [[ATTR2]] { -; IS__TUNIT____-NEXT: [[PTR:%.*]] = call i1* @lookup_bit(i32* noalias nofree readnone [[Q]], i32 [[BITNO]]) [[ATTR16:#.*]] +; IS__TUNIT____-NEXT: [[PTR:%.*]] = call i1* @lookup_bit(i32* noalias nofree readnone [[Q]], i32 [[BITNO]]) [[ATTR14:#.*]] ; IS__TUNIT____-NEXT: [[VAL:%.*]] = load i1, i1* [[PTR]], align 1 ; IS__TUNIT____-NEXT: ret i1 [[VAL]] ; @@ -330,7 +330,7 @@ ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@nc2 ; IS__CGSCC____-SAME: (i32* nocapture nofree [[P:%.*]], i32* nofree [[Q:%.*]]) [[ATTR5]] { -; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i32 @nc1(i32* nofree [[Q]], i32* nocapture nofree [[P]], i1 noundef false) [[ATTR10:#.*]] +; IS__CGSCC____-NEXT: [[TMP1:%.*]] = call i32 @nc1(i32* nofree [[Q]], i32* nocapture nofree [[P]], i1 noundef false) [[ATTR18:#.*]] ; IS__CGSCC____-NEXT: ret void ; %1 = call i32 @nc1(i32* %q, i32* %p, i1 0) ; [#uses=0] @@ -352,11 +352,17 @@ ; FIXME: readonly and nocapture missing on the pointer. declare void @external(i8* readonly) nounwind argmemonly define void @nc4(i8* %p) { -; CHECK: Function Attrs: argmemonly nounwind -; CHECK-LABEL: define {{[^@]+}}@nc4 -; CHECK-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] { -; CHECK-NEXT: call void @external(i8* readonly [[P]]) [[ATTR13:#.*]] -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: argmemonly nounwind +; IS__TUNIT____-LABEL: define {{[^@]+}}@nc4 +; IS__TUNIT____-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] { +; IS__TUNIT____-NEXT: call void @external(i8* readonly [[P]]) [[ATTR11:#.*]] +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: argmemonly nounwind +; IS__CGSCC____-LABEL: define {{[^@]+}}@nc4 +; IS__CGSCC____-SAME: (i8* [[P:%.*]]) [[ATTR6:#.*]] { +; IS__CGSCC____-NEXT: call void @external(i8* readonly [[P]]) [[ATTR13:#.*]] +; IS__CGSCC____-NEXT: ret void ; call void @external(i8* %p) ret void @@ -599,13 +605,21 @@ } define void @nocaptureLaunder(i8* %p) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@nocaptureLaunder -; CHECK-SAME: (i8* nocapture [[P:%.*]]) [[ATTR10:#.*]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P]]) [[ATTR17:#.*]] -; CHECK-NEXT: store i8 42, i8* [[B]], align 1 -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@nocaptureLaunder +; IS__TUNIT____-SAME: (i8* nocapture nofree [[P:%.*]]) [[ATTR5]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR15:#.*]] +; IS__TUNIT____-NEXT: store i8 42, i8* [[B]], align 1 +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@nocaptureLaunder +; IS__CGSCC____-SAME: (i8* nocapture nofree [[P:%.*]]) [[ATTR10:#.*]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR17]] +; IS__CGSCC____-NEXT: store i8 42, i8* [[B]], align 1 +; IS__CGSCC____-NEXT: ret void ; entry: %b = call i8* @llvm.launder.invariant.group.p0i8(i8* %p) @@ -615,12 +629,19 @@ @g2 = global i8* null define void @captureLaunder(i8* %p) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@captureLaunder -; CHECK-SAME: (i8* [[P:%.*]]) [[ATTR10]] { -; CHECK-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* [[P]]) [[ATTR17]] -; CHECK-NEXT: store i8* [[B]], i8** @g2, align 8 -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@captureLaunder +; IS__TUNIT____-SAME: (i8* nofree [[P:%.*]]) [[ATTR5]] { +; IS__TUNIT____-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR15]] +; IS__TUNIT____-NEXT: store i8* [[B]], i8** @g2, align 8 +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@captureLaunder +; IS__CGSCC____-SAME: (i8* nofree [[P:%.*]]) [[ATTR10]] { +; IS__CGSCC____-NEXT: [[B:%.*]] = call i8* @llvm.launder.invariant.group.p0i8(i8* nofree [[P]]) [[ATTR17]] +; IS__CGSCC____-NEXT: store i8* [[B]], i8** @g2, align 8 +; IS__CGSCC____-NEXT: ret void ; %b = call i8* @llvm.launder.invariant.group.p0i8(i8* %p) store i8* %b, i8** @g2 @@ -628,13 +649,21 @@ } define void @nocaptureStrip(i8* %p) { -; CHECK: Function Attrs: nosync nounwind willreturn writeonly -; CHECK-LABEL: define {{[^@]+}}@nocaptureStrip -; CHECK-SAME: (i8* nocapture writeonly [[P:%.*]]) [[ATTR11:#.*]] { -; CHECK-NEXT: entry: -; CHECK-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias readnone [[P]]) [[ATTR17]] -; CHECK-NEXT: store i8 42, i8* [[B]], align 1 -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly +; IS__TUNIT____-LABEL: define {{[^@]+}}@nocaptureStrip +; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[P:%.*]]) [[ATTR1]] { +; IS__TUNIT____-NEXT: entry: +; IS__TUNIT____-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR15]] +; IS__TUNIT____-NEXT: store i8 42, i8* [[B]], align 1 +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly +; IS__CGSCC____-LABEL: define {{[^@]+}}@nocaptureStrip +; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[P:%.*]]) [[ATTR11:#.*]] { +; IS__CGSCC____-NEXT: entry: +; IS__CGSCC____-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR17]] +; IS__CGSCC____-NEXT: store i8 42, i8* [[B]], align 1 +; IS__CGSCC____-NEXT: ret void ; entry: %b = call i8* @llvm.strip.invariant.group.p0i8(i8* %p) @@ -644,12 +673,19 @@ @g3 = global i8* null define void @captureStrip(i8* %p) { -; CHECK: Function Attrs: nosync nounwind willreturn writeonly -; CHECK-LABEL: define {{[^@]+}}@captureStrip -; CHECK-SAME: (i8* writeonly [[P:%.*]]) [[ATTR11]] { -; CHECK-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias readnone [[P]]) [[ATTR17]] -; CHECK-NEXT: store i8* [[B]], i8** @g3, align 8 -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly +; IS__TUNIT____-LABEL: define {{[^@]+}}@captureStrip +; IS__TUNIT____-SAME: (i8* nofree writeonly [[P:%.*]]) [[ATTR1]] { +; IS__TUNIT____-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR15]] +; IS__TUNIT____-NEXT: store i8* [[B]], i8** @g3, align 8 +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly +; IS__CGSCC____-LABEL: define {{[^@]+}}@captureStrip +; IS__CGSCC____-SAME: (i8* nofree writeonly [[P:%.*]]) [[ATTR11]] { +; IS__CGSCC____-NEXT: [[B:%.*]] = call i8* @llvm.strip.invariant.group.p0i8(i8* noalias nofree readnone [[P]]) [[ATTR17]] +; IS__CGSCC____-NEXT: store i8* [[B]], i8** @g3, align 8 +; IS__CGSCC____-NEXT: ret void ; %b = call i8* @llvm.strip.invariant.group.p0i8(i8* %p) store i8* %b, i8** @g3 @@ -747,7 +783,7 @@ define i1 @captureDereferenceableOrNullICmp(i32* dereferenceable_or_null(4) %x) null_pointer_is_valid { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind null_pointer_is_valid readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@captureDereferenceableOrNullICmp -; IS__TUNIT____-SAME: (i32* nofree readnone dereferenceable_or_null(4) [[X:%.*]]) [[ATTR12:#.*]] { +; IS__TUNIT____-SAME: (i32* nofree readnone dereferenceable_or_null(4) [[X:%.*]]) [[ATTR10:#.*]] { ; IS__TUNIT____-NEXT: [[TMP1:%.*]] = bitcast i32* [[X]] to i8* ; IS__TUNIT____-NEXT: [[TMP2:%.*]] = icmp eq i8* [[TMP1]], null ; IS__TUNIT____-NEXT: ret i1 [[TMP2]] @@ -812,7 +848,7 @@ define void @ptr_uses(i8* %ptr, i8* %wptr) { ; CHECK: Function Attrs: nounwind ; CHECK-LABEL: define {{[^@]+}}@ptr_uses -; CHECK-SAME: (i8* [[PTR:%.*]], i8* nocapture nonnull writeonly dereferenceable(1) [[WPTR:%.*]]) [[ATTR13]] { +; CHECK-SAME: (i8* [[PTR:%.*]], i8* nocapture nonnull writeonly dereferenceable(1) [[WPTR:%.*]]) [[ATTR13:#.*]] { ; CHECK-NEXT: store i8 0, i8* [[WPTR]], align 1 ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Transforms/Attributor/nofree.ll b/llvm/test/Transforms/Attributor/nofree.ll --- a/llvm/test/Transforms/Attributor/nofree.ll +++ b/llvm/test/Transforms/Attributor/nofree.ll @@ -247,7 +247,7 @@ ; TEST 10 (positive case) ; Call intrinsic function -; CHECK: Function Attrs: nounwind readnone speculatable +; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn ; CHECK-NEXT: declare float @llvm.floor.f32(float) declare float @llvm.floor.f32(float) @@ -266,13 +266,18 @@ ret void } -; FIXME: missing nofree define float @call_floor2(float %a) #0 { -; CHECK: Function Attrs: noinline nosync nounwind readnone uwtable willreturn -; CHECK-LABEL: define {{[^@]+}}@call_floor2 -; CHECK-SAME: (float [[A:%.*]]) [[ATTR7:#.*]] { -; CHECK-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR11:#.*]] -; CHECK-NEXT: ret float [[C]] +; IS__TUNIT____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@call_floor2 +; IS__TUNIT____-SAME: (float [[A:%.*]]) [[ATTR3]] { +; IS__TUNIT____-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR11:#.*]] +; IS__TUNIT____-NEXT: ret float [[C]] +; +; IS__CGSCC____: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@call_floor2 +; IS__CGSCC____-SAME: (float [[A:%.*]]) [[ATTR7:#.*]] { +; IS__CGSCC____-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR12:#.*]] +; IS__CGSCC____-NEXT: ret float [[C]] ; %c = tail call float @llvm.floor.f32(float %a) ret float %c @@ -368,11 +373,17 @@ ; ATTRIBUTOR-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]]) ; ATTRIBUTOR-NEXT: ret void ; -; CHECK-LABEL: define {{[^@]+}}@nonnull_assume_pos -; CHECK-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) { -; CHECK-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ] -; CHECK-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]]) -; CHECK-NEXT: ret void +; IS__TUNIT____-LABEL: define {{[^@]+}}@nonnull_assume_pos +; IS__TUNIT____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) { +; IS__TUNIT____-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ] +; IS__TUNIT____-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]]) +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____-LABEL: define {{[^@]+}}@nonnull_assume_pos +; IS__CGSCC____-SAME: (i8* nofree [[ARG1:%.*]], i8* [[ARG2:%.*]], i8* nofree [[ARG3:%.*]], i8* [[ARG4:%.*]]) { +; IS__CGSCC____-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nofree"(i8* [[ARG1]]), "nofree"(i8* [[ARG3]]) ] +; IS__CGSCC____-NEXT: call void @unknown(i8* nofree [[ARG1]], i8* [[ARG2]], i8* nofree [[ARG3]], i8* [[ARG4]]) +; IS__CGSCC____-NEXT: ret void ; call void @llvm.assume(i1 true) ["nofree"(i8* %arg1), "nofree"(i8* %arg3)] call void @unknown(i8* %arg1, i8* %arg2, i8* %arg3, i8* %arg4) diff --git a/llvm/test/Transforms/Attributor/nonnull.ll b/llvm/test/Transforms/Attributor/nonnull.ll --- a/llvm/test/Transforms/Attributor/nonnull.ll +++ b/llvm/test/Transforms/Attributor/nonnull.ll @@ -37,26 +37,26 @@ define i8* @test2A(i1 %c, i8* %ret) { ; ATTRIBUTOR: define nonnull i8* @test2A(i1 %c, i8* nofree nonnull readnone returned %ret) -; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test2A ; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0:#.*]] { ; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] ; NOT_CGSCC_OPM: A: -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11:#.*]] [ "nonnull"(i8* [[RET]]) ] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12:#.*]] [ "nonnull"(i8* [[RET]]) ] ; NOT_CGSCC_OPM-NEXT: ret i8* [[RET]] ; NOT_CGSCC_OPM: B: -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nonnull"(i8* [[RET]]) ] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[RET]]) ] ; NOT_CGSCC_OPM-NEXT: ret i8* [[RET]] ; -; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test2A ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0:#.*]] { ; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] ; IS__CGSCC_OPM: A: -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12:#.*]] [ "nonnull"(i8* [[RET]]) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13:#.*]] [ "nonnull"(i8* [[RET]]) ] ; IS__CGSCC_OPM-NEXT: ret i8* [[RET]] ; IS__CGSCC_OPM: B: -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[RET]]) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "nonnull"(i8* [[RET]]) ] ; IS__CGSCC_OPM-NEXT: ret i8* [[RET]] ; br i1 %c, label %A, label %B @@ -70,26 +70,26 @@ define i8* @test2B(i1 %c, i8* %ret) { ; ATTRIBUTOR: define nonnull dereferenceable(4) i8* @test2B(i1 %c, i8* nofree nonnull readnone returned dereferenceable(4) %ret) -; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test2B ; NOT_CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0]] { ; NOT_CGSCC_OPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] ; NOT_CGSCC_OPM: A: -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] ; NOT_CGSCC_OPM-NEXT: ret i8* [[RET]] ; NOT_CGSCC_OPM: B: -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] ; NOT_CGSCC_OPM-NEXT: ret i8* [[RET]] ; -; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test2B ; IS__CGSCC_OPM-SAME: (i1 [[C:%.*]], i8* nofree nonnull readnone returned dereferenceable(4) "no-capture-maybe-returned" [[RET:%.*]]) [[ATTR0]] { ; IS__CGSCC_OPM-NEXT: br i1 [[C]], label [[A:%.*]], label [[B:%.*]] ; IS__CGSCC_OPM: A: -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "dereferenceable"(i8* [[RET]], i32 4) ] ; IS__CGSCC_OPM-NEXT: ret i8* [[RET]] ; IS__CGSCC_OPM: B: -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "dereferenceable"(i8* [[RET]], i32 4) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "dereferenceable"(i8* [[RET]], i32 4) ] ; IS__CGSCC_OPM-NEXT: ret i8* [[RET]] ; br i1 %c, label %A, label %B @@ -318,17 +318,17 @@ ; ATTRIBUTOR_OPM: define i8* @test10 ; ATTRIBUTOR_NPM: define nonnull i8* @test10 define i8* @test10(i8* %a, i64 %n) { -; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@test10 ; NOT_CGSCC_OPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) [[ATTR0]] { -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] ; NOT_CGSCC_OPM-NEXT: [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]] ; NOT_CGSCC_OPM-NEXT: ret i8* [[B]] ; -; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@test10 ; IS__CGSCC_OPM-SAME: (i8* nofree readnone "no-capture-maybe-returned" [[A:%.*]], i64 [[N:%.*]]) [[ATTR0]] { -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13]] ; IS__CGSCC_OPM-NEXT: [[B:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[N]] ; IS__CGSCC_OPM-NEXT: ret i8* [[B]] ; @@ -455,11 +455,11 @@ ; NOT_CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]] ; NOT_CGSCC_OPM: bb4: ; NOT_CGSCC_OPM-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1 -; NOT_CGSCC_OPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR12:#.*]] +; NOT_CGSCC_OPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR13:#.*]] ; NOT_CGSCC_OPM-NEXT: [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1 ; NOT_CGSCC_OPM-NEXT: br label [[BB9]] ; NOT_CGSCC_OPM: bb6: -; NOT_CGSCC_OPM-NEXT: [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR12]] +; NOT_CGSCC_OPM-NEXT: [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]] ; NOT_CGSCC_OPM-NEXT: ret i32* [[TMP7]] ; NOT_CGSCC_OPM: bb9: ; NOT_CGSCC_OPM-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ] @@ -477,11 +477,11 @@ ; IS__CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[BB6:%.*]], label [[BB4:%.*]] ; IS__CGSCC_OPM: bb4: ; IS__CGSCC_OPM-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARG]], i64 1 -; IS__CGSCC_OPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR13:#.*]] +; IS__CGSCC_OPM-NEXT: [[TMP5B:%.*]] = tail call i32* @f3(i32* nofree nonnull readonly [[TMP5]]) [[ATTR14:#.*]] ; IS__CGSCC_OPM-NEXT: [[TMP5C:%.*]] = getelementptr inbounds i32, i32* [[TMP5B]], i64 -1 ; IS__CGSCC_OPM-NEXT: br label [[BB9]] ; IS__CGSCC_OPM: bb6: -; IS__CGSCC_OPM-NEXT: [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]] +; IS__CGSCC_OPM-NEXT: [[TMP7:%.*]] = tail call nonnull i32* @f2(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR14]] ; IS__CGSCC_OPM-NEXT: ret i32* [[TMP7]] ; IS__CGSCC_OPM: bb9: ; IS__CGSCC_OPM-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP5C]], [[BB4]] ], [ inttoptr (i64 4 to i32*), [[BB:%.*]] ] @@ -517,14 +517,14 @@ ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f2 ; NOT_CGSCC_OPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR5]] { ; NOT_CGSCC_OPM-NEXT: bb: -; NOT_CGSCC_OPM-NEXT: [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR12]] +; NOT_CGSCC_OPM-NEXT: [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]] ; NOT_CGSCC_OPM-NEXT: ret i32* [[TMP]] ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f2 ; IS__CGSCC_OPM-SAME: (i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR6]] { ; IS__CGSCC_OPM-NEXT: bb: -; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR13]] +; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = tail call nonnull i32* @f1(i32* nofree nonnull readonly align 4 dereferenceable(4) [[ARG]]) [[ATTR14]] ; IS__CGSCC_OPM-NEXT: ret i32* [[TMP]] ; bb: @@ -538,14 +538,14 @@ ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f3 ; NOT_CGSCC_OPM-SAME: (i32* nofree readonly [[ARG:%.*]]) [[ATTR5]] { ; NOT_CGSCC_OPM-NEXT: bb: -; NOT_CGSCC_OPM-NEXT: [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR12]] +; NOT_CGSCC_OPM-NEXT: [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR13]] ; NOT_CGSCC_OPM-NEXT: ret i32* [[TMP]] ; ; IS__CGSCC_OPM: Function Attrs: argmemonly nofree nosync nounwind readonly ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f3 ; IS__CGSCC_OPM-SAME: (i32* nofree readonly [[ARG:%.*]]) [[ATTR6]] { ; IS__CGSCC_OPM-NEXT: bb: -; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR13]] +; IS__CGSCC_OPM-NEXT: [[TMP:%.*]] = call nonnull i32* @f1(i32* nofree readonly [[ARG]]) [[ATTR14]] ; IS__CGSCC_OPM-NEXT: ret i32* [[TMP]] ; bb: @@ -577,17 +577,29 @@ ; fun2(nonnull %a, %b) ; We can say that %a is nonnull but %b is not. define void @f16(i8* %a, i8 * %b, i8 %c) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f16 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR0:#.*]] { -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR0]] -; CHECK-NEXT: ret void -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR0]] -; CHECK-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f16 +; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR6:#.*]] { +; NOT_CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_OPM: if.then: +; NOT_CGSCC_OPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; NOT_CGSCC_OPM: if.else: +; NOT_CGSCC_OPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f16 +; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR7:#.*]] { +; IS__CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_OPM: if.then: +; IS__CGSCC_OPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* nonnull [[B]]) [[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void +; IS__CGSCC_OPM: if.else: +; IS__CGSCC_OPM-NEXT: tail call void @fun2(i8* nonnull [[A]], i8* [[B]]) [[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void ; %cmp = icmp eq i8 %c, 0 br i1 %cmp, label %if.then, label %if.else @@ -606,20 +618,35 @@ ; fun1(nonnull %a) ; We can say that %a is nonnull define void @f17(i8* %a, i8 %c) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f17 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR0]] { -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun0() [[ATTR0]] -; CHECK-NEXT: br label [[CONT:%.*]] -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun0() [[ATTR0]] -; CHECK-NEXT: br label [[CONT]] -; CHECK: cont: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR0]] -; CHECK-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f17 +; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR6]] { +; NOT_CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_OPM: if.then: +; NOT_CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT:%.*]] +; NOT_CGSCC_OPM: if.else: +; NOT_CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT]] +; NOT_CGSCC_OPM: cont: +; NOT_CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f17 +; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8 [[C:%.*]]) [[ATTR7]] { +; IS__CGSCC_OPM-NEXT: [[CMP:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_OPM: if.then: +; IS__CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT:%.*]] +; IS__CGSCC_OPM: if.else: +; IS__CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT]] +; IS__CGSCC_OPM: cont: +; IS__CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void ; %cmp = icmp eq i8 %c, 0 br i1 %cmp, label %if.then, label %if.else @@ -645,29 +672,53 @@ ; fun1(nonnull %a) define void @f18(i8* %a, i8* %b, i8 %c) { -; CHECK: Function Attrs: nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@f18 -; CHECK-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR0]] { -; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 -; CHECK-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] -; CHECK: if.then: -; CHECK-NEXT: tail call void @fun0() [[ATTR0]] -; CHECK-NEXT: br label [[CONT:%.*]] -; CHECK: if.else: -; CHECK-NEXT: tail call void @fun0() [[ATTR0]] -; CHECK-NEXT: br label [[CONT]] -; CHECK: cont: -; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 -; CHECK-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] -; CHECK: cont.then: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[B]]) [[ATTR0]] -; CHECK-NEXT: br label [[CONT2:%.*]] -; CHECK: cont.else: -; CHECK-NEXT: tail call void @fun0() [[ATTR0]] -; CHECK-NEXT: br label [[CONT2]] -; CHECK: cont2: -; CHECK-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR0]] -; CHECK-NEXT: ret void +; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn +; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@f18 +; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR6]] { +; NOT_CGSCC_OPM-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 +; NOT_CGSCC_OPM-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; NOT_CGSCC_OPM: if.then: +; NOT_CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT:%.*]] +; NOT_CGSCC_OPM: if.else: +; NOT_CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT]] +; NOT_CGSCC_OPM: cont: +; NOT_CGSCC_OPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 +; NOT_CGSCC_OPM-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] +; NOT_CGSCC_OPM: cont.then: +; NOT_CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT2:%.*]] +; NOT_CGSCC_OPM: cont.else: +; NOT_CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: br label [[CONT2]] +; NOT_CGSCC_OPM: cont2: +; NOT_CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR6]] +; NOT_CGSCC_OPM-NEXT: ret void +; +; IS__CGSCC_OPM: Function Attrs: nounwind willreturn +; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f18 +; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]], i8* [[B:%.*]], i8 [[C:%.*]]) [[ATTR7]] { +; IS__CGSCC_OPM-NEXT: [[CMP1:%.*]] = icmp eq i8 [[C]], 0 +; IS__CGSCC_OPM-NEXT: br i1 [[CMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; IS__CGSCC_OPM: if.then: +; IS__CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT:%.*]] +; IS__CGSCC_OPM: if.else: +; IS__CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT]] +; IS__CGSCC_OPM: cont: +; IS__CGSCC_OPM-NEXT: [[CMP2:%.*]] = icmp eq i8 [[C]], 1 +; IS__CGSCC_OPM-NEXT: br i1 [[CMP2]], label [[CONT_THEN:%.*]], label [[CONT_ELSE:%.*]] +; IS__CGSCC_OPM: cont.then: +; IS__CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[B]]) [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT2:%.*]] +; IS__CGSCC_OPM: cont.else: +; IS__CGSCC_OPM-NEXT: tail call void @fun0() [[ATTR7]] +; IS__CGSCC_OPM-NEXT: br label [[CONT2]] +; IS__CGSCC_OPM: cont2: +; IS__CGSCC_OPM-NEXT: tail call void @fun1(i8* nonnull [[A]]) [[ATTR7]] +; IS__CGSCC_OPM-NEXT: ret void ; %cmp1 = icmp eq i8 %c, 0 br i1 %cmp1, label %if.then, label %if.else @@ -857,13 +908,13 @@ define i8 @parent7(i8* %a) { ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@parent7 ; NOT_CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]]) { -; NOT_CGSCC_OPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR13:#.*]] +; NOT_CGSCC_OPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR14:#.*]] ; NOT_CGSCC_OPM-NEXT: call void @use1nonnull(i8* nonnull [[A]]) ; NOT_CGSCC_OPM-NEXT: ret i8 [[RET]] ; ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@parent7 ; IS__CGSCC_OPM-SAME: (i8* nonnull [[A:%.*]]) { -; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR14:#.*]] +; IS__CGSCC_OPM-NEXT: [[RET:%.*]] = call i8 @use1safecall(i8* nonnull readonly [[A]]) [[ATTR15:#.*]] ; IS__CGSCC_OPM-NEXT: call void @use1nonnull(i8* nonnull [[A]]) ; IS__CGSCC_OPM-NEXT: ret i8 [[RET]] ; @@ -928,13 +979,13 @@ ; Should't be able to derive nonnull based on gep. ; IS__TUNIT____: Function Attrs: nofree nosync nounwind null_pointer_is_valid readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@gep1_no_null_opt -; IS__TUNIT____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR7:#.*]] { +; IS__TUNIT____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR8:#.*]] { ; IS__TUNIT____-NEXT: [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1 ; IS__TUNIT____-NEXT: ret i32* [[Q]] ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind null_pointer_is_valid readnone willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@gep1_no_null_opt -; IS__CGSCC____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR7:#.*]] { +; IS__CGSCC____-SAME: (i32* nofree readnone "no-capture-maybe-returned" [[P:%.*]]) [[ATTR8:#.*]] { ; IS__CGSCC____-NEXT: [[Q:%.*]] = getelementptr inbounds i32, i32* [[P]], i32 1 ; IS__CGSCC____-NEXT: ret i32* [[Q]] ; @@ -1054,7 +1105,7 @@ define internal void @naked(i32* dereferenceable(4) %a) naked { ; CHECK: Function Attrs: naked ; CHECK-LABEL: define {{[^@]+}}@naked -; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR8:#.*]] { +; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR9:#.*]] { ; CHECK-NEXT: call void @use_i32_ptr(i32* [[A]]) ; CHECK-NEXT: ret void ; @@ -1065,7 +1116,7 @@ define internal void @optnone(i32* dereferenceable(4) %a) optnone noinline { ; CHECK: Function Attrs: noinline optnone ; CHECK-LABEL: define {{[^@]+}}@optnone -; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR9:#.*]] { +; CHECK-SAME: (i32* dereferenceable(4) [[A:%.*]]) [[ATTR10:#.*]] { ; CHECK-NEXT: call void @use_i32_ptr(i32* [[A]]) ; CHECK-NEXT: ret void ; @@ -1122,16 +1173,16 @@ ; ; IS________NPM: Function Attrs: nounwind willreturn ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1 -; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR0:#.*]] { +; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR6:#.*]] { ; IS________NPM-NEXT: en: ; IS________NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS________NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] ; IS________NPM: ex: -; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR0]] +; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR6]] ; IS________NPM-NEXT: ret i32 [[TMP5]] ; IS________NPM: hd: ; IS________NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD]] ], [ 0, [[EN:%.*]] ] -; IS________NPM-NEXT: tail call void @h(i32* [[A]]) [[ATTR0]] +; IS________NPM-NEXT: tail call void @h(i32* [[A]]) [[ATTR6]] ; IS________NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 ; IS________NPM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], [[B]] ; IS________NPM-NEXT: br i1 [[TMP9]], label [[EX]], label [[HD]] @@ -1190,16 +1241,16 @@ ; ; IS________NPM: Function Attrs: nounwind willreturn ; IS________NPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_1b -; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] { +; IS________NPM-SAME: (i32* [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] { ; IS________NPM-NEXT: en: ; IS________NPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS________NPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] ; IS________NPM: ex: -; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR0]] +; IS________NPM-NEXT: [[TMP5:%.*]] = tail call i32 @g(i32* nonnull [[A]]) [[ATTR6]] ; IS________NPM-NEXT: ret i32 [[TMP5]] ; IS________NPM: hd: ; IS________NPM-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP8:%.*]], [[HD2:%.*]] ], [ 0, [[EN:%.*]] ] -; IS________NPM-NEXT: tail call void @h(i32* [[A]]) [[ATTR0]] +; IS________NPM-NEXT: tail call void @h(i32* [[A]]) [[ATTR6]] ; IS________NPM-NEXT: br label [[HD2]] ; IS________NPM: hd2: ; IS________NPM-NEXT: [[TMP8]] = add nuw i32 [[TMP7]], 1 @@ -1247,7 +1298,7 @@ ; ; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2 -; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] { +; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] { ; NOT_CGSCC_OPM-NEXT: en: ; NOT_CGSCC_OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; NOT_CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] @@ -1263,7 +1314,7 @@ ; ; IS__CGSCC_OPM: Function Attrs: nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2 -; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR7]] { ; IS__CGSCC_OPM-NEXT: en: ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS__CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] @@ -1297,7 +1348,7 @@ ; ; NOT_CGSCC_OPM: Function Attrs: nounwind willreturn ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b -; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] { +; NOT_CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR6]] { ; NOT_CGSCC_OPM-NEXT: en: ; NOT_CGSCC_OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; NOT_CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] @@ -1315,7 +1366,7 @@ ; ; IS__CGSCC_OPM: Function Attrs: nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_exec_ctx_2b -; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR0]] { +; IS__CGSCC_OPM-SAME: (i32* nonnull [[A:%.*]], i32 [[B:%.*]]) [[ATTR7]] { ; IS__CGSCC_OPM-NEXT: en: ; IS__CGSCC_OPM-NEXT: [[TMP3:%.*]] = icmp eq i32 [[B]], 0 ; IS__CGSCC_OPM-NEXT: br i1 [[TMP3]], label [[EX:%.*]], label [[HD:%.*]] @@ -1452,8 +1503,8 @@ define i8* @mybasename(i8* nofree readonly %str) { ; NOT_CGSCC_OPM: Function Attrs: nofree nounwind readonly ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@mybasename -; NOT_CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR10:#.*]] { -; NOT_CGSCC_OPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR13]] +; NOT_CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR11:#.*]] { +; NOT_CGSCC_OPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR14]] ; NOT_CGSCC_OPM-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null ; NOT_CGSCC_OPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1 ; NOT_CGSCC_OPM-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]] @@ -1461,8 +1512,8 @@ ; ; IS__CGSCC_OPM: Function Attrs: nofree nounwind readonly ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@mybasename -; IS__CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR11:#.*]] { -; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR14]] +; IS__CGSCC_OPM-SAME: (i8* nofree readonly [[STR:%.*]]) [[ATTR12:#.*]] { +; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i8* @strrchr(i8* nofree readonly [[STR]], i32 noundef 47) [[ATTR15]] ; IS__CGSCC_OPM-NEXT: [[TOBOOL:%.*]] = icmp ne i8* [[CALL]], null ; IS__CGSCC_OPM-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[CALL]], i64 1 ; IS__CGSCC_OPM-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i8* [[ADD_PTR]], i8* [[STR]] @@ -1485,14 +1536,14 @@ ; ; NOT_CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos ; NOT_CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) { -; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR11]] [ "nonnull"(i8* [[ARG]]) ] +; NOT_CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[ARG]]) ] ; NOT_CGSCC_OPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) [[ATTR4]] ; NOT_CGSCC_OPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() ; NOT_CGSCC_OPM-NEXT: ret void ; ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@nonnull_assume_pos ; IS__CGSCC_OPM-SAME: (i8* nocapture nofree nonnull readnone [[ARG:%.*]]) { -; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR12]] [ "nonnull"(i8* [[ARG]]) ] +; IS__CGSCC_OPM-NEXT: call void @llvm.assume(i1 noundef true) [[ATTR13]] [ "nonnull"(i8* [[ARG]]) ] ; IS__CGSCC_OPM-NEXT: call void @use_i8_ptr(i8* noalias nocapture nofree nonnull readnone [[ARG]]) [[ATTR5]] ; IS__CGSCC_OPM-NEXT: [[TMP1:%.*]] = call i8* @unknown() ; IS__CGSCC_OPM-NEXT: ret void diff --git a/llvm/test/Transforms/Attributor/norecurse.ll b/llvm/test/Transforms/Attributor/norecurse.ll --- a/llvm/test/Transforms/Attributor/norecurse.ll +++ b/llvm/test/Transforms/Attributor/norecurse.ll @@ -78,16 +78,16 @@ declare i32 @k() readnone define void @intrinsic(i8* %dest, i8* %src, i32 %len) { -; NOT_CGSCC_NPM: Function Attrs: argmemonly nosync nounwind willreturn +; NOT_CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn ; NOT_CGSCC_NPM-LABEL: define {{[^@]+}}@intrinsic -; NOT_CGSCC_NPM-SAME: (i8* nocapture writeonly [[DEST:%.*]], i8* nocapture readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR5:#.*]] { -; NOT_CGSCC_NPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[DEST]], i8* noalias nocapture readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR11:#.*]] +; NOT_CGSCC_NPM-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR5:#.*]] { +; NOT_CGSCC_NPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR10:#.*]] ; NOT_CGSCC_NPM-NEXT: ret void ; -; IS__CGSCC_NPM: Function Attrs: argmemonly nosync nounwind willreturn +; IS__CGSCC_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@intrinsic -; IS__CGSCC_NPM-SAME: (i8* nocapture writeonly [[DEST:%.*]], i8* nocapture readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR4:#.*]] { -; IS__CGSCC_NPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[DEST]], i8* noalias nocapture readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR8:#.*]] +; IS__CGSCC_NPM-SAME: (i8* nocapture nofree writeonly [[DEST:%.*]], i8* nocapture nofree readonly [[SRC:%.*]], i32 [[LEN:%.*]]) [[ATTR4:#.*]] { +; IS__CGSCC_NPM-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[DEST]], i8* noalias nocapture nofree readonly [[SRC]], i32 [[LEN]], i1 noundef false) [[ATTR7:#.*]] ; IS__CGSCC_NPM-NEXT: ret void ; call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 %len, i1 false) @@ -107,7 +107,7 @@ ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@called_by_norecurse -; IS__CGSCC____-SAME: () [[ATTR6:#.*]] { +; IS__CGSCC____-SAME: () [[ATTR5:#.*]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @k() ; IS__CGSCC____-NEXT: ret i32 undef ; @@ -117,13 +117,13 @@ define void @m() norecurse { ; IS__TUNIT____: Function Attrs: norecurse nosync readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@m -; IS__TUNIT____-SAME: () [[ATTR7:#.*]] { +; IS__TUNIT____-SAME: () [[ATTR6:#.*]] { ; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse() [[ATTR3]] ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@m -; IS__CGSCC____-SAME: () [[ATTR6]] { +; IS__CGSCC____-SAME: () [[ATTR5]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse() ; IS__CGSCC____-NEXT: ret void ; @@ -150,7 +150,7 @@ ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@o -; IS__CGSCC____-SAME: () [[ATTR6]] { +; IS__CGSCC____-SAME: () [[ATTR5]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @called_by_norecurse_indirectly() ; IS__CGSCC____-NEXT: ret i32 [[A]] ; @@ -160,13 +160,13 @@ define i32 @p() norecurse { ; IS__TUNIT____: Function Attrs: norecurse nosync readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@p -; IS__TUNIT____-SAME: () [[ATTR7]] { +; IS__TUNIT____-SAME: () [[ATTR6]] { ; IS__TUNIT____-NEXT: [[A:%.*]] = call i32 @o() [[ATTR3]] ; IS__TUNIT____-NEXT: ret i32 [[A]] ; ; IS__CGSCC____: Function Attrs: norecurse nosync readnone ; IS__CGSCC____-LABEL: define {{[^@]+}}@p -; IS__CGSCC____-SAME: () [[ATTR6]] { +; IS__CGSCC____-SAME: () [[ATTR5]] { ; IS__CGSCC____-NEXT: [[A:%.*]] = call i32 @o() ; IS__CGSCC____-NEXT: ret i32 [[A]] ; @@ -177,7 +177,7 @@ define void @f(i32 %x) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@f -; IS__TUNIT____-SAME: (i32 [[X:%.*]]) [[ATTR8:#.*]] { +; IS__TUNIT____-SAME: (i32 [[X:%.*]]) [[ATTR7:#.*]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 ; IS__TUNIT____-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 @@ -185,14 +185,14 @@ ; IS__TUNIT____-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0 ; IS__TUNIT____-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; IS__TUNIT____: if.then: -; IS__TUNIT____-NEXT: call void @g() [[ATTR9:#.*]] +; IS__TUNIT____-NEXT: call void @g() [[ATTR8:#.*]] ; IS__TUNIT____-NEXT: br label [[IF_END]] ; IS__TUNIT____: if.end: ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind readnone ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@f -; IS__CGSCC_OPM-SAME: (i32 [[X:%.*]]) [[ATTR8:#.*]] { +; IS__CGSCC_OPM-SAME: (i32 [[X:%.*]]) [[ATTR7:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: ; IS__CGSCC_OPM-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4 ; IS__CGSCC_OPM-NEXT: store i32 [[X]], i32* [[X_ADDR]], align 4 @@ -236,15 +236,15 @@ define void @g() norecurse { ; IS__TUNIT____: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@g -; IS__TUNIT____-SAME: () [[ATTR9]] { +; IS__TUNIT____-SAME: () [[ATTR8]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: nofree norecurse nosync nounwind readnone ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@g -; IS__CGSCC_OPM-SAME: () [[ATTR9:#.*]] { +; IS__CGSCC_OPM-SAME: () [[ATTR8:#.*]] { ; IS__CGSCC_OPM-NEXT: entry: -; IS__CGSCC_OPM-NEXT: call void @f(i32 noundef 0) [[ATTR8]] +; IS__CGSCC_OPM-NEXT: call void @f(i32 noundef 0) [[ATTR7]] ; IS__CGSCC_OPM-NEXT: ret void ; ; IS__CGSCC_NPM: Function Attrs: nofree norecurse nosync nounwind readnone willreturn @@ -279,7 +279,7 @@ define i32 @eval_func2(i32 (i32)* , i32) local_unnamed_addr null_pointer_is_valid{ ; CHECK: Function Attrs: null_pointer_is_valid ; CHECK-LABEL: define {{[^@]+}}@eval_func2 -; CHECK-SAME: (i32 (i32)* nocapture nofree [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr [[ATTR7:#.*]] { +; CHECK-SAME: (i32 (i32)* nocapture nofree [[TMP0:%.*]], i32 [[TMP1:%.*]]) local_unnamed_addr [[ATTR6:#.*]] { ; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 [[TMP0]](i32 [[TMP1]]) ; CHECK-NEXT: ret i32 [[TMP3]] ; diff --git a/llvm/test/Transforms/Attributor/nosync.ll b/llvm/test/Transforms/Attributor/nosync.ll --- a/llvm/test/Transforms/Attributor/nosync.ll +++ b/llvm/test/Transforms/Attributor/nosync.ll @@ -401,11 +401,17 @@ ; It is odd to add nocapture but a result of the llvm.memcpy nocapture. ; define i32 @memcpy_volatile(i8* %ptr1, i8* %ptr2) { -; CHECK: Function Attrs: argmemonly nounwind willreturn -; CHECK-LABEL: define {{[^@]+}}@memcpy_volatile -; CHECK-SAME: (i8* nocapture writeonly [[PTR1:%.*]], i8* nocapture readonly [[PTR2:%.*]]) [[ATTR10:#.*]] { -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly [[PTR1]], i8* noalias nocapture readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR19:#.*]] -; CHECK-NEXT: ret i32 4 +; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@memcpy_volatile +; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) [[ATTR10:#.*]] { +; IS__TUNIT____-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR16:#.*]] +; IS__TUNIT____-NEXT: ret i32 4 +; +; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@memcpy_volatile +; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8* nocapture nofree readonly [[PTR2:%.*]]) [[ATTR10:#.*]] { +; IS__CGSCC____-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture nofree writeonly [[PTR1]], i8* noalias nocapture nofree readonly [[PTR2]], i32 noundef 8, i1 noundef true) [[ATTR18:#.*]] +; IS__CGSCC____-NEXT: ret i32 4 ; call void @llvm.memcpy(i8* %ptr1, i8* %ptr2, i32 8, i1 1) ret i32 4 @@ -416,11 +422,17 @@ ; It is odd to add nocapture but a result of the llvm.memset nocapture. ; define i32 @memset_non_volatile(i8* %ptr1, i8 %val) { -; CHECK: Function Attrs: argmemonly nosync nounwind willreturn writeonly -; CHECK-LABEL: define {{[^@]+}}@memset_non_volatile -; CHECK-SAME: (i8* nocapture writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] { -; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR20:#.*]] -; CHECK-NEXT: ret i32 4 +; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly +; IS__TUNIT____-LABEL: define {{[^@]+}}@memset_non_volatile +; IS__TUNIT____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] { +; IS__TUNIT____-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR17:#.*]] +; IS__TUNIT____-NEXT: ret i32 4 +; +; IS__CGSCC____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly +; IS__CGSCC____-LABEL: define {{[^@]+}}@memset_non_volatile +; IS__CGSCC____-SAME: (i8* nocapture nofree writeonly [[PTR1:%.*]], i8 [[VAL:%.*]]) [[ATTR11:#.*]] { +; IS__CGSCC____-NEXT: call void @llvm.memset.p0i8.i32(i8* nocapture nofree writeonly [[PTR1]], i8 [[VAL]], i32 noundef 8, i1 noundef false) [[ATTR19:#.*]] +; IS__CGSCC____-NEXT: ret i32 4 ; call void @llvm.memset(i8* %ptr1, i8 %val, i32 8, i1 0) ret i32 4 @@ -452,7 +464,7 @@ ret void } -; CHECK: Function Attrs: nounwind +; CHECK: Function Attrs: nofree nosync nounwind willreturn ; CHECK-NEXT: declare void @llvm.x86.sse2.clflush(i8*) declare void @llvm.x86.sse2.clflush(i8*) @a = common global i32 0, align 4 @@ -460,11 +472,17 @@ ; TEST 18 - negative. Synchronizing intrinsic define void @i_totally_sync() { -; CHECK: Function Attrs: nounwind -; CHECK-LABEL: define {{[^@]+}}@i_totally_sync -; CHECK-SAME: () [[ATTR14:#.*]] { -; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(i8* noundef nonnull align 4 dereferenceable(4) bitcast (i32* @a to i8*)) -; CHECK-NEXT: ret void +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@i_totally_sync +; IS__TUNIT____-SAME: () [[ATTR8]] { +; IS__TUNIT____-NEXT: tail call void @llvm.x86.sse2.clflush(i8* nofree noundef nonnull align 4 dereferenceable(4) bitcast (i32* @a to i8*)) [[ATTR16]] +; IS__TUNIT____-NEXT: ret void +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@i_totally_sync +; IS__CGSCC____-SAME: () [[ATTR14:#.*]] { +; IS__CGSCC____-NEXT: tail call void @llvm.x86.sse2.clflush(i8* nofree noundef nonnull align 4 dereferenceable(4) bitcast (i32* @a to i8*)) [[ATTR18]] +; IS__CGSCC____-NEXT: ret void ; tail call void @llvm.x86.sse2.clflush(i8* bitcast (i32* @a to i8*)) ret void @@ -477,7 +495,7 @@ define i32 @cos_test(float %x) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@cos_test -; IS__TUNIT____-SAME: (float [[X:%.*]]) [[ATTR15:#.*]] { +; IS__TUNIT____-SAME: (float [[X:%.*]]) [[ATTR14:#.*]] { ; IS__TUNIT____-NEXT: ret i32 4 ; ; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn @@ -490,11 +508,17 @@ } define float @cos_test2(float %x) { -; CHECK: Function Attrs: nosync nounwind readnone willreturn -; CHECK-LABEL: define {{[^@]+}}@cos_test2 -; CHECK-SAME: (float [[X:%.*]]) [[ATTR16:#.*]] { -; CHECK-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR19]] -; CHECK-NEXT: ret float [[C]] +; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn +; IS__TUNIT____-LABEL: define {{[^@]+}}@cos_test2 +; IS__TUNIT____-SAME: (float [[X:%.*]]) [[ATTR14]] { +; IS__TUNIT____-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR16]] +; IS__TUNIT____-NEXT: ret float [[C]] +; +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readnone willreturn +; IS__CGSCC____-LABEL: define {{[^@]+}}@cos_test2 +; IS__CGSCC____-SAME: (float [[X:%.*]]) [[ATTR16:#.*]] { +; IS__CGSCC____-NEXT: [[C:%.*]] = call float @llvm.cos.f32(float [[X]]) [[ATTR18]] +; IS__CGSCC____-NEXT: ret float [[C]] ; %c = call float @llvm.cos(float %x) ret float %c diff --git a/llvm/test/Transforms/Attributor/readattrs.ll b/llvm/test/Transforms/Attributor/readattrs.ll --- a/llvm/test/Transforms/Attributor/readattrs.ll +++ b/llvm/test/Transforms/Attributor/readattrs.ll @@ -163,13 +163,13 @@ ; CHECK-NOT: readnone ; CHECK-NOT: readonly define void @test9(<4 x i32*> %ptrs, <4 x i32>%val) { -; IS__TUNIT____: Function Attrs: nounwind willreturn writeonly +; IS__TUNIT____: Function Attrs: nofree nosync nounwind willreturn writeonly ; IS__TUNIT____-LABEL: define {{[^@]+}}@test9 -; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR4:#.*]] { -; IS__TUNIT____-NEXT: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef ) [[ATTR11:#.*]] +; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR0]] { +; IS__TUNIT____-NEXT: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef ) [[ATTR10:#.*]] ; IS__TUNIT____-NEXT: ret void ; -; IS__CGSCC____: Function Attrs: nounwind willreturn writeonly +; IS__CGSCC____: Function Attrs: nofree nosync nounwind willreturn writeonly ; IS__CGSCC____-LABEL: define {{[^@]+}}@test9 ; IS__CGSCC____-SAME: (<4 x i32*> [[PTRS:%.*]], <4 x i32> [[VAL:%.*]]) [[ATTR4:#.*]] { ; IS__CGSCC____-NEXT: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL]], <4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef ) [[ATTR12:#.*]] @@ -182,13 +182,13 @@ ; CHECK: declare <4 x i32> @llvm.masked.gather declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>) define <4 x i32> @test10(<4 x i32*> %ptrs) { -; IS__TUNIT____: Function Attrs: nounwind readonly willreturn +; IS__TUNIT____: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@test10 -; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR5:#.*]] { -; IS__TUNIT____-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef , <4 x i32> undef) [[ATTR12:#.*]] +; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR4:#.*]] { +; IS__TUNIT____-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef , <4 x i32> undef) [[ATTR11:#.*]] ; IS__TUNIT____-NEXT: ret <4 x i32> [[RES]] ; -; IS__CGSCC____: Function Attrs: nounwind readonly willreturn +; IS__CGSCC____: Function Attrs: nofree nosync nounwind readonly willreturn ; IS__CGSCC____-LABEL: define {{[^@]+}}@test10 ; IS__CGSCC____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR5:#.*]] { ; IS__CGSCC____-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[PTRS]], i32 noundef 4, <4 x i1> noundef , <4 x i32> undef) [[ATTR13:#.*]] @@ -216,8 +216,8 @@ define <4 x i32> @test12_2(<4 x i32*> %ptrs) { ; IS__TUNIT____: Function Attrs: argmemonly nounwind ; IS__TUNIT____-LABEL: define {{[^@]+}}@test12_2 -; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR7:#.*]] { -; IS__TUNIT____-NEXT: [[RES:%.*]] = call <4 x i32> @test12_1(<4 x i32*> [[PTRS]]) [[ATTR13:#.*]] +; IS__TUNIT____-SAME: (<4 x i32*> [[PTRS:%.*]]) [[ATTR6:#.*]] { +; IS__TUNIT____-NEXT: [[RES:%.*]] = call <4 x i32> @test12_1(<4 x i32*> [[PTRS]]) [[ATTR12:#.*]] ; IS__TUNIT____-NEXT: ret <4 x i32> [[RES]] ; ; IS__CGSCC____: Function Attrs: argmemonly nounwind @@ -233,7 +233,7 @@ define i32 @volatile_load(i32* %p) { ; IS__TUNIT____: Function Attrs: argmemonly nofree nounwind willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@volatile_load -; IS__TUNIT____-SAME: (i32* nofree align 4 [[P:%.*]]) [[ATTR8:#.*]] { +; IS__TUNIT____-SAME: (i32* nofree align 4 [[P:%.*]]) [[ATTR7:#.*]] { ; IS__TUNIT____-NEXT: [[LOAD:%.*]] = load volatile i32, i32* [[P]], align 4 ; IS__TUNIT____-NEXT: ret i32 [[LOAD]] ; @@ -369,7 +369,7 @@ ; IS__TUNIT____-LABEL: define {{[^@]+}}@testbyval ; IS__TUNIT____-SAME: (i8* nocapture readonly [[READ_ONLY:%.*]]) { ; IS__TUNIT____-NEXT: call void @byval_not_readonly_1(i8* nocapture readonly [[READ_ONLY]]) [[ATTR2:#.*]] -; IS__TUNIT____-NEXT: call void @byval_not_readnone_1(i8* noalias nocapture readnone [[READ_ONLY]]) [[ATTR9:#.*]] +; IS__TUNIT____-NEXT: call void @byval_not_readnone_1(i8* noalias nocapture readnone [[READ_ONLY]]) [[ATTR8:#.*]] ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: readonly diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll --- a/llvm/test/Transforms/Attributor/value-simplify.ll +++ b/llvm/test/Transforms/Attributor/value-simplify.ll @@ -379,31 +379,31 @@ ret i32* %a } define i32* @complicated_args_preallocated() { -; IS__TUNIT_OPM: Function Attrs: nounwind +; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@complicated_args_preallocated ; IS__TUNIT_OPM-SAME: () [[ATTR0:#.*]] { -; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) -; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR5:#.*]] [ "preallocated"(token [[C]]) ] +; IS__TUNIT_OPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR5:#.*]] +; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR1:#.*]] [ "preallocated"(token [[C]]) ] ; IS__TUNIT_OPM-NEXT: ret i32* [[CALL]] ; -; IS__TUNIT_NPM: Function Attrs: nounwind +; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@complicated_args_preallocated ; IS__TUNIT_NPM-SAME: () [[ATTR0:#.*]] { -; IS__TUNIT_NPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) -; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR4:#.*]] [ "preallocated"(token [[C]]) ] +; IS__TUNIT_NPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR4:#.*]] +; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR1:#.*]] [ "preallocated"(token [[C]]) ] ; IS__TUNIT_NPM-NEXT: ret i32* [[CALL]] ; -; IS__CGSCC_OPM: Function Attrs: nounwind +; IS__CGSCC_OPM: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@complicated_args_preallocated ; IS__CGSCC_OPM-SAME: () [[ATTR0:#.*]] { -; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) +; IS__CGSCC_OPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR5]] ; IS__CGSCC_OPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR6:#.*]] [ "preallocated"(token [[C]]) ] ; IS__CGSCC_OPM-NEXT: ret i32* [[CALL]] ; -; IS__CGSCC_NPM: Function Attrs: nounwind +; IS__CGSCC_NPM: Function Attrs: nofree nosync nounwind willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@complicated_args_preallocated ; IS__CGSCC_NPM-SAME: () [[ATTR0:#.*]] { -; IS__CGSCC_NPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) +; IS__CGSCC_NPM-NEXT: [[C:%.*]] = call token @llvm.call.preallocated.setup(i32 noundef 1) [[ATTR4]] ; IS__CGSCC_NPM-NEXT: [[CALL:%.*]] = call i32* @test_preallocated(i32* noalias nocapture nofree noundef writeonly preallocated(i32) align 536870912 null) [[ATTR5:#.*]] [ "preallocated"(token [[C]]) ] ; IS__CGSCC_NPM-NEXT: ret i32* [[CALL]] ; diff --git a/llvm/test/Transforms/Attributor/willreturn.ll b/llvm/test/Transforms/Attributor/willreturn.ll --- a/llvm/test/Transforms/Attributor/willreturn.ll +++ b/llvm/test/Transforms/Attributor/willreturn.ll @@ -42,9 +42,9 @@ ; IS__TUNIT_OPM-NEXT: br i1 [[TMP2]], label [[TMP9:%.*]], label [[TMP3:%.*]] ; IS__TUNIT_OPM: 3: ; IS__TUNIT_OPM-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP0]], -1 -; IS__TUNIT_OPM-NEXT: [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR16:#.*]] +; IS__TUNIT_OPM-NEXT: [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR15:#.*]] ; IS__TUNIT_OPM-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP0]], -2 -; IS__TUNIT_OPM-NEXT: [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR16]] +; IS__TUNIT_OPM-NEXT: [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR15]] ; IS__TUNIT_OPM-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP7]], [[TMP5]] ; IS__TUNIT_OPM-NEXT: ret i32 [[TMP8]] ; IS__TUNIT_OPM: 9: @@ -57,9 +57,9 @@ ; IS__TUNIT_NPM-NEXT: br i1 [[TMP2]], label [[TMP9:%.*]], label [[TMP3:%.*]] ; IS__TUNIT_NPM: 3: ; IS__TUNIT_NPM-NEXT: [[TMP4:%.*]] = add nsw i32 [[TMP0]], -1 -; IS__TUNIT_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR17:#.*]] +; IS__TUNIT_NPM-NEXT: [[TMP5:%.*]] = tail call i32 @fib(i32 [[TMP4]]) [[ATTR16:#.*]] ; IS__TUNIT_NPM-NEXT: [[TMP6:%.*]] = add nsw i32 [[TMP0]], -2 -; IS__TUNIT_NPM-NEXT: [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR17]] +; IS__TUNIT_NPM-NEXT: [[TMP7:%.*]] = tail call i32 @fib(i32 [[TMP6]]) [[ATTR16]] ; IS__TUNIT_NPM-NEXT: [[TMP8:%.*]] = add nsw i32 [[TMP7]], [[TMP5]] ; IS__TUNIT_NPM-NEXT: ret i32 [[TMP8]] ; IS__TUNIT_NPM: 9: @@ -284,8 +284,8 @@ ; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]]) [[ATTR3:#.*]] { ; IS__TUNIT_OPM-NEXT: br i1 [[C]], label [[REC:%.*]], label [[END:%.*]] ; IS__TUNIT_OPM: rec: -; IS__TUNIT_OPM-NEXT: call void @sink() [[ATTR12:#.*]] -; IS__TUNIT_OPM-NEXT: call void @mutual_recursion2(i1 [[C]]) [[ATTR17:#.*]] +; IS__TUNIT_OPM-NEXT: call void @sink() [[ATTR11:#.*]] +; IS__TUNIT_OPM-NEXT: call void @mutual_recursion2(i1 [[C]]) [[ATTR16:#.*]] ; IS__TUNIT_OPM-NEXT: br label [[END]] ; IS__TUNIT_OPM: end: ; IS__TUNIT_OPM-NEXT: ret void @@ -295,8 +295,8 @@ ; IS__TUNIT_NPM-SAME: (i1 [[C:%.*]]) [[ATTR3:#.*]] { ; IS__TUNIT_NPM-NEXT: br i1 [[C]], label [[REC:%.*]], label [[END:%.*]] ; IS__TUNIT_NPM: rec: -; IS__TUNIT_NPM-NEXT: call void @sink() [[ATTR12:#.*]] -; IS__TUNIT_NPM-NEXT: call void @mutual_recursion2(i1 noundef [[C]]) [[ATTR19:#.*]] +; IS__TUNIT_NPM-NEXT: call void @sink() [[ATTR11:#.*]] +; IS__TUNIT_NPM-NEXT: call void @mutual_recursion2(i1 noundef [[C]]) [[ATTR18:#.*]] ; IS__TUNIT_NPM-NEXT: br label [[END]] ; IS__TUNIT_NPM: end: ; IS__TUNIT_NPM-NEXT: ret void @@ -337,13 +337,13 @@ ; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind uwtable ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@mutual_recursion2 ; IS__TUNIT_OPM-SAME: (i1 [[C:%.*]]) [[ATTR3]] { -; IS__TUNIT_OPM-NEXT: call void @mutual_recursion1(i1 [[C]]) [[ATTR17]] +; IS__TUNIT_OPM-NEXT: call void @mutual_recursion1(i1 [[C]]) [[ATTR16]] ; IS__TUNIT_OPM-NEXT: ret void ; ; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind uwtable ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@mutual_recursion2 ; IS__TUNIT_NPM-SAME: (i1 [[C:%.*]]) [[ATTR3]] { -; IS__TUNIT_NPM-NEXT: call void @mutual_recursion1(i1 [[C]]) [[ATTR19]] +; IS__TUNIT_NPM-NEXT: call void @mutual_recursion1(i1 [[C]]) [[ATTR18]] ; IS__TUNIT_NPM-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind uwtable @@ -455,7 +455,7 @@ ; TEST 6 (positive case) ; Call intrinsic function -; CHECK: Function Attrs: nounwind readnone speculatable willreturn +; CHECK: Function Attrs: nofree nosync nounwind readnone speculatable willreturn ; CHECK-NEXT: declare float @llvm.floor.f32(float) declare float @llvm.floor.f32(float) @@ -475,25 +475,25 @@ } define float @call_floor2(float %a) #0 { -; IS__TUNIT_OPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn +; IS__TUNIT_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@call_floor2 -; IS__TUNIT_OPM-SAME: (float [[A:%.*]]) [[ATTR8:#.*]] { -; IS__TUNIT_OPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR18:#.*]] +; IS__TUNIT_OPM-SAME: (float [[A:%.*]]) [[ATTR0:#.*]] { +; IS__TUNIT_OPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR17:#.*]] ; IS__TUNIT_OPM-NEXT: ret float [[C]] ; -; IS__TUNIT_NPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn +; IS__TUNIT_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@call_floor2 -; IS__TUNIT_NPM-SAME: (float [[A:%.*]]) [[ATTR8:#.*]] { -; IS__TUNIT_NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR20:#.*]] +; IS__TUNIT_NPM-SAME: (float [[A:%.*]]) [[ATTR0]] { +; IS__TUNIT_NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR19:#.*]] ; IS__TUNIT_NPM-NEXT: ret float [[C]] ; -; IS__CGSCC_OPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_OPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@call_floor2 ; IS__CGSCC_OPM-SAME: (float [[A:%.*]]) [[ATTR9:#.*]] { ; IS__CGSCC_OPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR21:#.*]] ; IS__CGSCC_OPM-NEXT: ret float [[C]] ; -; IS__CGSCC_NPM: Function Attrs: noinline nosync nounwind readnone uwtable willreturn +; IS__CGSCC_NPM: Function Attrs: nofree noinline nosync nounwind readnone uwtable willreturn ; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@call_floor2 ; IS__CGSCC_NPM-SAME: (float [[A:%.*]]) [[ATTR9:#.*]] { ; IS__CGSCC_NPM-NEXT: [[C:%.*]] = tail call float @llvm.floor.f32(float [[A]]) [[ATTR23:#.*]] @@ -516,13 +516,13 @@ ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@call_maybe_noreturn ; IS__TUNIT_OPM-SAME: () [[ATTR6:#.*]] { -; IS__TUNIT_OPM-NEXT: tail call void @maybe_noreturn() [[ATTR19:#.*]] +; IS__TUNIT_OPM-NEXT: tail call void @maybe_noreturn() [[ATTR18:#.*]] ; IS__TUNIT_OPM-NEXT: ret void ; ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@call_maybe_noreturn ; IS__TUNIT_NPM-SAME: () [[ATTR6:#.*]] { -; IS__TUNIT_NPM-NEXT: tail call void @maybe_noreturn() [[ATTR21:#.*]] +; IS__TUNIT_NPM-NEXT: tail call void @maybe_noreturn() [[ATTR20:#.*]] ; IS__TUNIT_NPM-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: noinline nounwind uwtable @@ -552,14 +552,14 @@ define void @f1() #0 { ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@f1 -; IS__TUNIT_OPM-SAME: () [[ATTR10:#.*]] { -; IS__TUNIT_OPM-NEXT: tail call void @will_return() [[ATTR18]] +; IS__TUNIT_OPM-SAME: () [[ATTR9:#.*]] { +; IS__TUNIT_OPM-NEXT: tail call void @will_return() [[ATTR17]] ; IS__TUNIT_OPM-NEXT: ret void ; ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@f1 -; IS__TUNIT_NPM-SAME: () [[ATTR10:#.*]] { -; IS__TUNIT_NPM-NEXT: tail call void @will_return() [[ATTR20]] +; IS__TUNIT_NPM-SAME: () [[ATTR9:#.*]] { +; IS__TUNIT_NPM-NEXT: tail call void @will_return() [[ATTR19]] ; IS__TUNIT_NPM-NEXT: ret void ; ; IS__CGSCC_OPM: Function Attrs: noinline norecurse nounwind uwtable willreturn @@ -581,8 +581,8 @@ define void @f2() #0 { ; IS__TUNIT____: Function Attrs: noinline nounwind uwtable willreturn ; IS__TUNIT____-LABEL: define {{[^@]+}}@f2 -; IS__TUNIT____-SAME: () [[ATTR10:#.*]] { -; IS__TUNIT____-NEXT: tail call void @f1() [[ATTR12:#.*]] +; IS__TUNIT____-SAME: () [[ATTR9:#.*]] { +; IS__TUNIT____-NEXT: tail call void @f1() [[ATTR11:#.*]] ; IS__TUNIT____-NEXT: ret void ; ; IS__CGSCC____: Function Attrs: noinline norecurse nounwind uwtable willreturn @@ -639,8 +639,8 @@ define void @invoke_test() personality i32 (...)* @__gxx_personality_v0 { ; IS__TUNIT_OPM: Function Attrs: nounwind willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@invoke_test -; IS__TUNIT_OPM-SAME: () [[ATTR12]] personality i32 (...)* @__gxx_personality_v0 { -; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR18]] +; IS__TUNIT_OPM-SAME: () [[ATTR11]] personality i32 (...)* @__gxx_personality_v0 { +; IS__TUNIT_OPM-NEXT: [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR17]] ; IS__TUNIT_OPM-NEXT: to label [[N:%.*]] unwind label [[F:%.*]] ; IS__TUNIT_OPM: N: ; IS__TUNIT_OPM-NEXT: ret void @@ -651,8 +651,8 @@ ; ; IS__TUNIT_NPM: Function Attrs: nounwind willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@invoke_test -; IS__TUNIT_NPM-SAME: () [[ATTR12]] personality i32 (...)* @__gxx_personality_v0 { -; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR20]] +; IS__TUNIT_NPM-SAME: () [[ATTR11]] personality i32 (...)* @__gxx_personality_v0 { +; IS__TUNIT_NPM-NEXT: [[TMP1:%.*]] = invoke i1 @maybe_raise_exception() [[ATTR19]] ; IS__TUNIT_NPM-NEXT: to label [[N:%.*]] unwind label [[F:%.*]] ; IS__TUNIT_NPM: N: ; IS__TUNIT_NPM-NEXT: ret void @@ -711,7 +711,7 @@ define i32 @loop_constant_trip_count(i32* nocapture readonly %0) #0 { ; IS__TUNIT_OPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@loop_constant_trip_count -; IS__TUNIT_OPM-SAME: (i32* nocapture nofree readonly [[TMP0:%.*]]) [[ATTR13:#.*]] { +; IS__TUNIT_OPM-SAME: (i32* nocapture nofree readonly [[TMP0:%.*]]) [[ATTR12:#.*]] { ; IS__TUNIT_OPM-NEXT: br label [[TMP3:%.*]] ; IS__TUNIT_OPM: 2: ; IS__TUNIT_OPM-NEXT: ret i32 [[TMP8:%.*]] @@ -727,7 +727,7 @@ ; ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@loop_constant_trip_count -; IS__TUNIT_NPM-SAME: (i32* nocapture nofree nonnull readonly dereferenceable(4) [[TMP0:%.*]]) [[ATTR13:#.*]] { +; IS__TUNIT_NPM-SAME: (i32* nocapture nofree nonnull readonly dereferenceable(4) [[TMP0:%.*]]) [[ATTR12:#.*]] { ; IS__TUNIT_NPM-NEXT: br label [[TMP3:%.*]] ; IS__TUNIT_NPM: 2: ; IS__TUNIT_NPM-NEXT: ret i32 [[TMP8:%.*]] @@ -803,7 +803,7 @@ define i32 @loop_trip_count_unbound(i32 %0, i32 %1, i32* nocapture readonly %2, i32 %3) local_unnamed_addr #0 { ; IS__TUNIT____: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable ; IS__TUNIT____-LABEL: define {{[^@]+}}@loop_trip_count_unbound -; IS__TUNIT____-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32* nocapture nofree readonly [[TMP2:%.*]], i32 [[TMP3:%.*]]) local_unnamed_addr [[ATTR14:#.*]] { +; IS__TUNIT____-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32* nocapture nofree readonly [[TMP2:%.*]], i32 [[TMP3:%.*]]) local_unnamed_addr [[ATTR13:#.*]] { ; IS__TUNIT____-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP0]], [[TMP1]] ; IS__TUNIT____-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP8:%.*]] ; IS__TUNIT____: 6: @@ -873,7 +873,7 @@ define i32 @loop_trip_dec(i32 %0, i32* nocapture readonly %1) local_unnamed_addr #0 { ; IS__TUNIT_OPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@loop_trip_dec -; IS__TUNIT_OPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR13]] { +; IS__TUNIT_OPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR12]] { ; IS__TUNIT_OPM-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP0]], -1 ; IS__TUNIT_OPM-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP14:%.*]] ; IS__TUNIT_OPM: 4: @@ -894,7 +894,7 @@ ; ; IS__TUNIT_NPM: Function Attrs: argmemonly nofree noinline nosync nounwind readonly uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@loop_trip_dec -; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR13]] { +; IS__TUNIT_NPM-SAME: (i32 [[TMP0:%.*]], i32* nocapture nofree readonly [[TMP1:%.*]]) local_unnamed_addr [[ATTR12]] { ; IS__TUNIT_NPM-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[TMP0]], -1 ; IS__TUNIT_NPM-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP14:%.*]] ; IS__TUNIT_NPM: 4: @@ -1017,16 +1017,16 @@ define void @unreachable_exit_positive1() #0 { ; IS__TUNIT_OPM: Function Attrs: noinline nounwind uwtable willreturn ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@unreachable_exit_positive1 -; IS__TUNIT_OPM-SAME: () [[ATTR10]] { -; IS__TUNIT_OPM-NEXT: tail call void @will_return() [[ATTR18]] +; IS__TUNIT_OPM-SAME: () [[ATTR9]] { +; IS__TUNIT_OPM-NEXT: tail call void @will_return() [[ATTR17]] ; IS__TUNIT_OPM-NEXT: ret void ; IS__TUNIT_OPM: unreachable_label: ; IS__TUNIT_OPM-NEXT: unreachable ; ; IS__TUNIT_NPM: Function Attrs: noinline nounwind uwtable willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@unreachable_exit_positive1 -; IS__TUNIT_NPM-SAME: () [[ATTR10]] { -; IS__TUNIT_NPM-NEXT: tail call void @will_return() [[ATTR20]] +; IS__TUNIT_NPM-SAME: () [[ATTR9]] { +; IS__TUNIT_NPM-NEXT: tail call void @will_return() [[ATTR19]] ; IS__TUNIT_NPM-NEXT: ret void ; IS__TUNIT_NPM: unreachable_label: ; IS__TUNIT_NPM-NEXT: unreachable @@ -1179,7 +1179,7 @@ define void @unreachable_exit_negative2() #0 { ; IS__TUNIT____: Function Attrs: nofree noinline noreturn nosync nounwind readnone uwtable ; IS__TUNIT____-LABEL: define {{[^@]+}}@unreachable_exit_negative2 -; IS__TUNIT____-SAME: () [[ATTR15:#.*]] { +; IS__TUNIT____-SAME: () [[ATTR14:#.*]] { ; IS__TUNIT____-NEXT: br label [[L1:%.*]] ; IS__TUNIT____: L1: ; IS__TUNIT____-NEXT: br label [[L2:%.*]] @@ -1245,7 +1245,7 @@ define i32 @infinite_loop_inside_bounded_loop(i32 %n) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@infinite_loop_inside_bounded_loop -; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17:#.*]] { +; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16:#.*]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: br label [[FOR_COND:%.*]] ; IS__TUNIT____: for.cond: @@ -1327,7 +1327,7 @@ define i32 @bounded_nested_loops(i32 %n) { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@bounded_nested_loops -; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] { +; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR15]] { ; IS__TUNIT_OPM-NEXT: entry: ; IS__TUNIT_OPM-NEXT: br label [[FOR_COND:%.*]] ; IS__TUNIT_OPM: for.cond: @@ -1356,7 +1356,7 @@ ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone willreturn ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@bounded_nested_loops -; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR18:#.*]] { +; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR17:#.*]] { ; IS__TUNIT_NPM-NEXT: entry: ; IS__TUNIT_NPM-NEXT: br label [[FOR_COND:%.*]] ; IS__TUNIT_NPM: for.cond: @@ -1491,7 +1491,7 @@ define i32 @bounded_loop_inside_unbounded_loop(i32 %n) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@bounded_loop_inside_unbounded_loop -; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17]] { +; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: br label [[WHILE_COND:%.*]] ; IS__TUNIT____: while.cond: @@ -1606,7 +1606,7 @@ define i32 @nested_unbounded_loops(i32 %n) { ; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT____-LABEL: define {{[^@]+}}@nested_unbounded_loops -; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR17]] { +; IS__TUNIT____-SAME: (i32 [[N:%.*]]) [[ATTR16]] { ; IS__TUNIT____-NEXT: entry: ; IS__TUNIT____-NEXT: br label [[WHILE_COND:%.*]] ; IS__TUNIT____: while.cond: @@ -1726,9 +1726,9 @@ define void @non_loop_cycle(i32 %n) { ; IS__TUNIT_OPM: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@non_loop_cycle -; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] { +; IS__TUNIT_OPM-SAME: (i32 [[N:%.*]]) [[ATTR15]] { ; IS__TUNIT_OPM-NEXT: entry: -; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] +; IS__TUNIT_OPM-NEXT: [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]] ; IS__TUNIT_OPM-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CALL]], 5 ; IS__TUNIT_OPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] ; IS__TUNIT_OPM: if.then: @@ -1736,7 +1736,7 @@ ; IS__TUNIT_OPM: if.else: ; IS__TUNIT_OPM-NEXT: br label [[ENTRY2:%.*]] ; IS__TUNIT_OPM: entry1: -; IS__TUNIT_OPM-NEXT: [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] +; IS__TUNIT_OPM-NEXT: [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]] ; IS__TUNIT_OPM-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[CALL1]], 5 ; IS__TUNIT_OPM-NEXT: br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_ELSE4:%.*]] ; IS__TUNIT_OPM: if.then3: @@ -1744,7 +1744,7 @@ ; IS__TUNIT_OPM: if.else4: ; IS__TUNIT_OPM-NEXT: br label [[ENTRY2]] ; IS__TUNIT_OPM: entry2: -; IS__TUNIT_OPM-NEXT: [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] +; IS__TUNIT_OPM-NEXT: [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR15]] ; IS__TUNIT_OPM-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[CALL5]], 5 ; IS__TUNIT_OPM-NEXT: br i1 [[CMP6]], label [[IF_THEN7:%.*]], label [[IF_ELSE8:%.*]] ; IS__TUNIT_OPM: if.then7: @@ -1756,9 +1756,9 @@ ; ; IS__TUNIT_NPM: Function Attrs: nofree nosync nounwind readnone ; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@non_loop_cycle -; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR17]] { +; IS__TUNIT_NPM-SAME: (i32 [[N:%.*]]) [[ATTR16]] { ; IS__TUNIT_NPM-NEXT: entry: -; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]] +; IS__TUNIT_NPM-NEXT: [[CALL:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] ; IS__TUNIT_NPM-NEXT: [[CMP:%.*]] = icmp sgt i32 [[CALL]], 5 ; IS__TUNIT_NPM-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] ; IS__TUNIT_NPM: if.then: @@ -1766,7 +1766,7 @@ ; IS__TUNIT_NPM: if.else: ; IS__TUNIT_NPM-NEXT: br label [[ENTRY2:%.*]] ; IS__TUNIT_NPM: entry1: -; IS__TUNIT_NPM-NEXT: [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]] +; IS__TUNIT_NPM-NEXT: [[CALL1:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] ; IS__TUNIT_NPM-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[CALL1]], 5 ; IS__TUNIT_NPM-NEXT: br i1 [[CMP2]], label [[IF_THEN3:%.*]], label [[IF_ELSE4:%.*]] ; IS__TUNIT_NPM: if.then3: @@ -1774,7 +1774,7 @@ ; IS__TUNIT_NPM: if.else4: ; IS__TUNIT_NPM-NEXT: br label [[ENTRY2]] ; IS__TUNIT_NPM: entry2: -; IS__TUNIT_NPM-NEXT: [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR17]] +; IS__TUNIT_NPM-NEXT: [[CALL5:%.*]] = call i32 @fact_loop(i32 [[N]]) [[ATTR16]] ; IS__TUNIT_NPM-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[CALL5]], 5 ; IS__TUNIT_NPM-NEXT: br i1 [[CMP6]], label [[IF_THEN7:%.*]], label [[IF_ELSE8:%.*]] ; IS__TUNIT_NPM: if.then7: diff --git a/llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll b/llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll --- a/llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll +++ b/llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll @@ -158,7 +158,7 @@ ; CHECK-NEXT: [[N_VAL_SPILL_ADDR:%.*]] = getelementptr inbounds i8, i8* [[BUFFER]], i64 8 ; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[N_VAL_SPILL_ADDR]] to i32* ; CHECK-NEXT: store i32 [[N]], i32* [[TMP0]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = tail call i8* @allocate(i32 [[N]]) [[ATTR0]] +; CHECK-NEXT: [[TMP1:%.*]] = tail call i8* @allocate(i32 [[N]]) [[ATTR2:#.*]] ; CHECK-NEXT: [[DOTSPILL_ADDR:%.*]] = bitcast i8* [[BUFFER]] to i8** ; CHECK-NEXT: store i8* [[TMP1]], i8** [[DOTSPILL_ADDR]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { i8*, i8*, i32 } { i8* bitcast ({ i8*, i8*, i32 } (i8*, i1)* @f.resume.0 to i8*), i8* undef, i32 undef }, i8* [[TMP1]], 1 @@ -171,21 +171,19 @@ ; CHECK-NEXT: entryresume.0: ; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i8** ; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i8*, i8** [[DOTRELOAD_ADDR]], align 8 -; CHECK-NEXT: tail call void @deallocate(i8* [[DOTRELOAD]]) -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i64 8 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[N_VAL_RELOAD_ADDR]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[TMP2]], align 8 +; CHECK-NEXT: tail call void @deallocate(i8* [[DOTRELOAD]]) +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP3]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: store i32 [[INC]], i32* [[TMP2]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = tail call i8* @allocate(i32 [[INC]]) -; CHECK-NEXT: store i8* [[TMP3]], i8** [[DOTRELOAD_ADDR]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i8*, i8*, i32 } { i8* bitcast ({ i8*, i8*, i32 } (i8*, i1)* @f.resume.0 to i8*), i8* undef, i32 undef }, i8* [[TMP3]], 1 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i8*, i8*, i32 } [[TMP4]], i32 [[INC]], 2 -; CHECK-NEXT: ret { i8*, i8*, i32 } [[TMP5]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret { i8*, i8*, i32 } { i8* null, i8* undef, i32 undef } +; CHECK-NEXT: [[TMP4:%.*]] = tail call i8* @allocate(i32 [[INC]]) +; CHECK-NEXT: store i8* [[TMP4]], i8** [[DOTRELOAD_ADDR]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i8*, i8*, i32 } { i8* bitcast ({ i8*, i8*, i32 } (i8*, i1)* @f.resume.0 to i8*), i8* undef, i32 undef }, i8* [[TMP4]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i8*, i8*, i32 } [[TMP5]], i32 [[INC]], 2 +; CHECK-NEXT: ret { i8*, i8*, i32 } [[TMP6]] ; ; ; CHECK-LABEL: define {{[^@]+}}@g @@ -203,19 +201,17 @@ ; CHECK-LABEL: define {{[^@]+}}@g.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 8 dereferenceable(1024) [[TMP0:%.*]], i1 [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 8 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[INC]] to i64 -; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8 -; CHECK-NEXT: call void @use(i8* nonnull [[TMP3]]) -; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*, i1)* @g.resume.0 to i8*), i32 undef }, i32 [[INC]], 1 -; CHECK-NEXT: ret { i8*, i32 } [[TMP4]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret { i8*, i32 } { i8* null, i32 undef } +; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = alloca i8, i64 [[TMP3]], align 8 +; CHECK-NEXT: call void @use(i8* nonnull [[TMP4]]) +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*, i1)* @g.resume.0 to i8*), i32 undef }, i32 [[INC]], 1 +; CHECK-NEXT: ret { i8*, i32 } [[TMP5]] ; ; ; CHECK-LABEL: define {{[^@]+}}@h @@ -230,19 +226,17 @@ ; CHECK-LABEL: define {{[^@]+}}@h.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 8 dereferenceable(1024) [[TMP0:%.*]], i1 [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 -; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[INC]] to i64 -; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8 -; CHECK-NEXT: call void @use(i8* nonnull [[TMP3]]) +; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = alloca i8, i64 [[TMP3]], align 8 +; CHECK-NEXT: call void @use(i8* nonnull [[TMP4]]) ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 8 -; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*, i1)* @h.resume.0 to i8*), i32 undef }, i32 [[INC]], 1 -; CHECK-NEXT: ret { i8*, i32 } [[TMP4]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret { i8*, i32 } { i8* null, i32 undef } +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*, i1)* @h.resume.0 to i8*), i32 undef }, i32 [[INC]], 1 +; CHECK-NEXT: ret { i8*, i32 } [[TMP5]] ; ; ; CHECK-LABEL: define {{[^@]+}}@i @@ -298,11 +292,8 @@ ; CHECK-NEXT: call void @llvm.stackrestore(i8* [[TMP1]]) ; CHECK-NEXT: [[K:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[K]], 128 -; CHECK-NEXT: br i1 [[CMP]], label [[CORO_RETURN:%.*]], label [[COROEND:%.*]] -; CHECK: coro.return: +; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: store i32 [[K]], i32* [[N_VAL_RELOAD_ADDR]], align 8 ; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*)* @j.resume.0 to i8*), i32 undef }, i32 [[K]], 1 ; CHECK-NEXT: ret { i8*, i32 } [[TMP4]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret { i8*, i32 } { i8* null, i32 undef } ; diff --git a/llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll b/llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll --- a/llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll +++ b/llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll @@ -67,10 +67,8 @@ declare void @print(i32) ; CHECK-LABEL: define {{[^@]+}}@f -; CHECK-SAME: (i8* [[BUFFER:%.*]], i32* [[ARRAY:%.*]]) local_unnamed_addr [[ATTR0:#.*]] { +; CHECK-SAME: (i8* [[BUFFER:%.*]], i32* nocapture readonly [[ARRAY:%.*]]) local_unnamed_addr [[ATTR0:#.*]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[ARRAY_SPILL_ADDR:%.*]] = bitcast i8* [[BUFFER]] to i32** -; CHECK-NEXT: store i32* [[ARRAY]], i32** [[ARRAY_SPILL_ADDR]], align 8 ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[ARRAY]], align 4 ; CHECK-NEXT: [[LOAD_POS:%.*]] = icmp sgt i32 [[LOAD]], 0 ; CHECK-NEXT: [[TMP0:%.*]] = select i1 [[LOAD_POS]], void (i8*, i1)* @f.resume.0, void (i8*, i1)* @f.resume.1 @@ -84,35 +82,20 @@ ; CHECK-LABEL: define {{[^@]+}}@f.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 8 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[POS_CONT:%.*]] -; CHECK: pos.cont: -; CHECK-NEXT: [[ARRAY_RELOAD_ADDR3:%.*]] = bitcast i8* [[TMP0]] to i32** -; CHECK-NEXT: [[ARRAY_RELOAD4:%.*]] = load i32*, i32** [[ARRAY_RELOAD_ADDR3]], align 8 -; CHECK-NEXT: store i32 0, i32* [[ARRAY_RELOAD4]], align 4 -; CHECK-NEXT: br label [[COROEND]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret void +; CHECK-NEXT: unreachable ; ; ; CHECK-LABEL: define {{[^@]+}}@f.resume.1 ; CHECK-SAME: (i8* noalias nonnull align 8 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.1: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[NEG_CONT:%.*]] -; CHECK: neg.cont: -; CHECK-NEXT: [[ARRAY_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32** -; CHECK-NEXT: [[ARRAY_RELOAD:%.*]] = load i32*, i32** [[ARRAY_RELOAD_ADDR]], align 8 -; CHECK-NEXT: store i32 10, i32* [[ARRAY_RELOAD]], align 4 -; CHECK-NEXT: br label [[COROEND]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret void +; CHECK-NEXT: unreachable ; ; ; CHECK-LABEL: define {{[^@]+}}@test -; CHECK-SAME: (i32* [[ARRAY:%.*]]) local_unnamed_addr { +; CHECK-SAME: (i32* nocapture readonly [[ARRAY:%.*]]) local_unnamed_addr { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = alloca i32*, align 8 -; CHECK-NEXT: [[DOTSUB:%.*]] = bitcast i32** [[TMP0]] to i8* -; CHECK-NEXT: store i32* [[ARRAY]], i32** [[TMP0]], align 8 +; CHECK-NEXT: [[TMP0:%.*]] = alloca [8 x i8], align 8 +; CHECK-NEXT: [[DOTSUB:%.*]] = getelementptr inbounds [8 x i8], [8 x i8]* [[TMP0]], i64 0, i64 0 ; CHECK-NEXT: [[LOAD_I:%.*]] = load i32, i32* [[ARRAY]], align 4 ; CHECK-NEXT: [[LOAD_POS_I:%.*]] = icmp sgt i32 [[LOAD_I]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[LOAD_POS_I]], void (i8*, i1)* @f.resume.0, void (i8*, i1)* @f.resume.1 diff --git a/llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll b/llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll --- a/llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll +++ b/llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll @@ -71,14 +71,14 @@ ; CHECK-NEXT: entryresume.0: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 4 -; CHECK-NEXT: br i1 [[TMP2]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] +; CHECK-NEXT: br i1 [[TMP2]], label [[CLEANUP:%.*]], label [[LOOP_FROM_RESUME:%.*]] ; CHECK: loop.from.resume: ; CHECK-NEXT: [[SUM:%.*]] = add i32 [[N_VAL_RELOAD]], [[TMP1]] ; CHECK-NEXT: store i32 [[SUM]], i32* [[N_VAL_RELOAD_ADDR]], align 4 ; CHECK-NEXT: ret i8* bitcast (i8* (i8*, i32, i1)* @f.resume.0 to i8*) -; CHECK: CoroEnd: +; CHECK: cleanup: ; CHECK-NEXT: tail call void @print(i32 [[N_VAL_RELOAD]]) -; CHECK-NEXT: ret i8* null +; CHECK-NEXT: unreachable ; ; ; CHECK-LABEL: define {{[^@]+}}@main() local_unnamed_addr { @@ -88,5 +88,5 @@ ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR1_I1:%.*]] = bitcast [8 x i8]* [[TMP0]] to i32* ; CHECK-NEXT: store i32 7, i32* [[N_VAL_RELOAD_ADDR1_I1]], align 4, !alias.scope !0 ; CHECK-NEXT: call void @print(i32 7), !noalias !3 -; CHECK-NEXT: ret i32 0 +; CHECK-NEXT: unreachable ; diff --git a/llvm/test/Transforms/Coroutines/coro-retcon-value.ll b/llvm/test/Transforms/Coroutines/coro-retcon-value.ll --- a/llvm/test/Transforms/Coroutines/coro-retcon-value.ll +++ b/llvm/test/Transforms/Coroutines/coro-retcon-value.ll @@ -78,17 +78,14 @@ ; CHECK-LABEL: define {{[^@]+}}@f.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 4 dereferenceable(8) [[TMP0:%.*]], i8 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: [[UNWIND0_NOT:%.*]] = icmp eq i8 [[TMP1]], 0 -; CHECK-NEXT: br i1 [[UNWIND0_NOT]], label [[LOOP_FROM_RESUME:%.*]], label [[COROEND:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 4 +; CHECK-NEXT: [[UNWIND0_NOT:%.*]] = icmp eq i8 [[TMP1]], 0 +; CHECK-NEXT: tail call void @llvm.assume(i1 [[UNWIND0_NOT]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = insertvalue { i8*, i32 } { i8* bitcast ({ i8*, i32 } (i8*, i8)* @f.resume.0 to i8*), i32 undef }, i32 [[INC]], 1 ; CHECK-NEXT: ret { i8*, i32 } [[TMP2]] -; CHECK: CoroEnd: -; CHECK-NEXT: ret { i8*, i32 } { i8* null, i32 undef } ; ; ; CHECK-LABEL: define {{[^@]+}}@main() local_unnamed_addr { @@ -106,5 +103,5 @@ ; CHECK-NEXT: [[INC_I2:%.*]] = add i32 [[N_VAL_RELOAD_I1]], 1 ; CHECK-NEXT: store i32 [[INC_I2]], i32* [[N_VAL_SPILL_ADDR_I]], align 4, !alias.scope !3 ; CHECK-NEXT: call void @print(i32 [[INC_I2]]) -; CHECK-NEXT: ret i32 0 +; CHECK-NEXT: unreachable ; diff --git a/llvm/test/Transforms/Coroutines/coro-retcon.ll b/llvm/test/Transforms/Coroutines/coro-retcon.ll --- a/llvm/test/Transforms/Coroutines/coro-retcon.ll +++ b/llvm/test/Transforms/Coroutines/coro-retcon.ll @@ -89,16 +89,14 @@ ; CHECK-LABEL: define {{[^@]+}}@f.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 4 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 4 ; CHECK-NEXT: tail call void @print(i32 [[INC]]) ; CHECK-NEXT: ret i8* bitcast (i8* (i8*, i1)* @f.resume.0 to i8*) -; CHECK: CoroEnd: -; CHECK-NEXT: ret i8* null ; ; ; CHECK-LABEL: define {{[^@]+}}@main() local_unnamed_addr { @@ -116,13 +114,13 @@ ; CHECK-NEXT: [[INC_I2:%.*]] = add i32 [[N_VAL_RELOAD_I1]], 1 ; CHECK-NEXT: store i32 [[INC_I2]], i32* [[N_VAL_SPILL_ADDR_I]], align 4, !alias.scope !3 ; CHECK-NEXT: call void @print(i32 [[INC_I2]]), !noalias !3 -; CHECK-NEXT: ret i32 0 +; CHECK-NEXT: unreachable ; ; ; CHECK-LABEL: define {{[^@]+}}@g ; CHECK-SAME: (i8* [[BUFFER:%.*]], i16* [[PTR:%.*]]) local_unnamed_addr [[ATTR0:#.*]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = tail call i8* @allocate(i32 8) [[ATTR0]] +; CHECK-NEXT: [[TMP0:%.*]] = tail call i8* @allocate(i32 8) [[ATTR2:#.*]] ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[BUFFER]] to i8** ; CHECK-NEXT: store i8* [[TMP0]], i8** [[TMP1]], align 8 ; CHECK-NEXT: [[PTR_SPILL_ADDR:%.*]] = bitcast i8* [[TMP0]] to i16** @@ -135,16 +133,11 @@ ; CHECK-LABEL: define {{[^@]+}}@g.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 4 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to %g.Frame** -; CHECK-NEXT: [[FRAMEPTR:%.*]] = load %g.Frame*, %g.Frame** [[TMP2]], align 8 -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[CORO_RETURN:%.*]] -; CHECK: coro.return: -; CHECK-NEXT: [[TMP3:%.*]] = bitcast %g.Frame* [[FRAMEPTR]] to i8** -; CHECK-NEXT: [[PTR_RELOAD1:%.*]] = load i8*, i8** [[TMP3]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to i8*** +; CHECK-NEXT: [[FRAMEPTR2:%.*]] = load i8**, i8*** [[TMP2]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP3]]) +; CHECK-NEXT: [[PTR_RELOAD1:%.*]] = load i8*, i8** [[FRAMEPTR2]], align 8 ; CHECK-NEXT: [[TMP4:%.*]] = insertvalue { i8*, i8* } { i8* bitcast ({ i8*, i8* } (i8*, i1)* @g.resume.0 to i8*), i8* undef }, i8* [[PTR_RELOAD1]], 1 ; CHECK-NEXT: ret { i8*, i8* } [[TMP4]] -; CHECK: CoroEnd: -; CHECK-NEXT: [[TMP5:%.*]] = bitcast %g.Frame* [[FRAMEPTR]] to i8* -; CHECK-NEXT: tail call void @deallocate(i8* [[TMP5]]) -; CHECK-NEXT: ret { i8*, i8* } { i8* null, i8* undef } ; diff --git a/llvm/test/Transforms/Coroutines/coro-swifterror.ll b/llvm/test/Transforms/Coroutines/coro-swifterror.ll --- a/llvm/test/Transforms/Coroutines/coro-swifterror.ll +++ b/llvm/test/Transforms/Coroutines/coro-swifterror.ll @@ -91,22 +91,20 @@ ; CHECK-LABEL: define {{[^@]+}}@f.resume.0 ; CHECK-SAME: (i8* noalias nonnull align 4 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]], i8** swifterror [[TMP2:%.*]]) { ; CHECK-NEXT: entryresume.0: -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: -; CHECK-NEXT: [[TMP3:%.*]] = load i8*, i8** [[TMP2]], align 4 ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i8*, i8** [[TMP2]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP4]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 4 ; CHECK-NEXT: tail call void @print(i32 [[INC]]) ; CHECK-NEXT: store i8* [[TMP3]], i8** [[TMP2]], align 4 ; CHECK-NEXT: tail call void @maybeThrow(i8** nonnull swifterror [[TMP2]]) -; CHECK-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4 -; CHECK-NEXT: tail call void @logError(i8* [[TMP4]]) -; CHECK-NEXT: store i8* [[TMP4]], i8** [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP2]], align 4 +; CHECK-NEXT: tail call void @logError(i8* [[TMP5]]) +; CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP2]], align 4 ; CHECK-NEXT: ret i8* bitcast (i8* (i8*, i1, i8**)* @f.resume.0 to i8*) -; CHECK: CoroEnd: -; CHECK-NEXT: ret i8* null ; ; ; CHECK-LABEL: define {{[^@]+}}@g @@ -130,22 +128,20 @@ ; CHECK-SAME: (i8* noalias nonnull align 4 dereferenceable(8) [[TMP0:%.*]], i1 zeroext [[TMP1:%.*]]) { ; CHECK-NEXT: entryresume.0: ; CHECK-NEXT: [[TMP2:%.*]] = alloca swifterror i8*, align 4 -; CHECK-NEXT: br i1 [[TMP1]], label [[COROEND:%.*]], label [[LOOP_FROM_RESUME:%.*]] -; CHECK: loop.from.resume: ; CHECK-NEXT: [[N_VAL_RELOAD_ADDR:%.*]] = bitcast i8* [[TMP0]] to i32* ; CHECK-NEXT: [[N_VAL_RELOAD:%.*]] = load i32, i32* [[N_VAL_RELOAD_ADDR]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP1]], true +; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP3]]) ; CHECK-NEXT: [[INC:%.*]] = add i32 [[N_VAL_RELOAD]], 1 ; CHECK-NEXT: [[DOTRELOAD_ADDR:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i32 4 -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[DOTRELOAD_ADDR]] to i8** -; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i8*, i8** [[TMP3]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[DOTRELOAD_ADDR]] to i8** +; CHECK-NEXT: [[DOTRELOAD:%.*]] = load i8*, i8** [[TMP4]], align 4 ; CHECK-NEXT: store i32 [[INC]], i32* [[N_VAL_RELOAD_ADDR]], align 4 ; CHECK-NEXT: tail call void @print(i32 [[INC]]) ; CHECK-NEXT: store i8* [[DOTRELOAD]], i8** [[TMP2]], align 4 ; CHECK-NEXT: call void @maybeThrow(i8** nonnull swifterror [[TMP2]]) -; CHECK-NEXT: [[TMP4:%.*]] = load i8*, i8** [[TMP2]], align 4 -; CHECK-NEXT: store i8* [[TMP4]], i8** [[TMP3]], align 4 -; CHECK-NEXT: call void @logError(i8* [[TMP4]]) +; CHECK-NEXT: [[TMP5:%.*]] = load i8*, i8** [[TMP2]], align 4 +; CHECK-NEXT: store i8* [[TMP5]], i8** [[TMP4]], align 4 +; CHECK-NEXT: call void @logError(i8* [[TMP5]]) ; CHECK-NEXT: ret i8* bitcast (i8* (i8*, i1)* @g.resume.0 to i8*) -; CHECK: CoroEnd: -; CHECK-NEXT: ret i8* null ; diff --git a/llvm/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll b/llvm/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll --- a/llvm/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll +++ b/llvm/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll @@ -1,8 +1,10 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature ; RUN: opt -S -deadargelim < %s | FileCheck %s @.str = private constant [1 x i8] zeroinitializer, align 1 ; <[1 x i8]*> [#uses=1] define i8* @vfs_addname(i8* %name, i32 %len, i32 %hash, i32 %flags) nounwind ssp { +; entry: call void @llvm.dbg.value(metadata i8* %name, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1) call void @llvm.dbg.value(metadata i32 %len, metadata !10, metadata !DIExpression()), !dbg !DILocation(scope: !1) @@ -16,6 +18,7 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone define internal fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext %extra, i32 %flags) noinline nounwind ssp { +; entry: call void @llvm.dbg.value(metadata i8* %name, metadata !15, metadata !DIExpression()), !dbg !DILocation(scope: !16) call void @llvm.dbg.value(metadata i32 %len, metadata !20, metadata !DIExpression()), !dbg !DILocation(scope: !16) @@ -39,7 +42,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone ; CHECK: attributes #0 = { nounwind ssp } -; CHECK: attributes #1 = { nounwind readnone speculatable willreturn } +; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK: attributes #2 = { noinline nounwind ssp } ; CHECK: attributes [[NUW]] = { nounwind } diff --git a/llvm/test/Transforms/DeadArgElim/keepalive.ll b/llvm/test/Transforms/DeadArgElim/keepalive.ll --- a/llvm/test/Transforms/DeadArgElim/keepalive.ll +++ b/llvm/test/Transforms/DeadArgElim/keepalive.ll @@ -10,59 +10,74 @@ ; the function and then changing too much. ; This checks if the return value attributes are not removed -; CHECK: define internal zeroext i32 @test1() #0 +; CHECK: define internal zeroext i32 @test1() #1 define internal zeroext i32 @test1(i32 %DEADARG1) nounwind { - ret i32 1 +; +; + ret i32 1 } ; This checks if the struct doesn't get non-packed ; CHECK-LABEL: define internal <{ i32, i32 }> @test2( define internal <{ i32, i32 }> @test2(i32 %DEADARG1) { - ret <{ i32, i32 }> <{ i32 1, i32 2 }> +; +; + ret <{ i32, i32 }> <{ i32 1, i32 2 }> } ; We use this external function to make sure the return values don't become dead declare void @user(i32, <{ i32, i32 }>) define void @caller() { - %B = call i32 @test1(i32 1) - %C = call <{ i32, i32 }> @test2(i32 2) - call void @user(i32 %B, <{ i32, i32 }> %C) - ret void +; +; + %B = call i32 @test1(i32 1) + %C = call <{ i32, i32 }> @test2(i32 2) + call void @user(i32 %B, <{ i32, i32 }> %C) + ret void } ; We can't remove 'this' here, as that would put argmem in ecx instead of ; memory. define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) { - %v = load i32, i32* %argmem - ret i32 %v +; +; + %v = load i32, i32* %argmem + ret i32 %v } ; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this(i32* %this, i32* inalloca %argmem) define i32 @caller2() { - %t = alloca i32 - %m = alloca inalloca i32 - store i32 42, i32* %m - %v = call x86_thiscallcc i32 @unused_this(i32* %t, i32* inalloca %m) - ret i32 %v +; +; + %t = alloca i32 + %m = alloca inalloca i32 + store i32 42, i32* %m + %v = call x86_thiscallcc i32 @unused_this(i32* %t, i32* inalloca %m) + ret i32 %v } ; We can't remove 'this' here, as that would put argmem in ecx instead of ; memory. define internal x86_thiscallcc i32 @unused_this_preallocated(i32* %this, i32* preallocated(i32) %argmem) { - %v = load i32, i32* %argmem - ret i32 %v +; +; + %v = load i32, i32* %argmem + ret i32 %v } ; CHECK-LABEL: define internal x86_thiscallcc i32 @unused_this_preallocated(i32* %this, i32* preallocated(i32) %argmem) define i32 @caller3() { - %t = alloca i32 - %c = call token @llvm.call.preallocated.setup(i32 1) - %M = call i8* @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32) - %m = bitcast i8* %M to i32* - store i32 42, i32* %m - %v = call x86_thiscallcc i32 @unused_this_preallocated(i32* %t, i32* preallocated(i32) %m) ["preallocated"(token %c)] - ret i32 %v +; +; + %t = alloca i32 + %c = call token @llvm.call.preallocated.setup(i32 1) + %M = call i8* @llvm.call.preallocated.arg(token %c, i32 0) preallocated(i32) + %m = bitcast i8* %M to i32* + store i32 42, i32* %m + %v = call x86_thiscallcc i32 @unused_this_preallocated(i32* %t, i32* preallocated(i32) %m) ["preallocated"(token %c)] + ret i32 %v } -; CHECK: attributes #0 = { nounwind } +; CHECK: attributes #0 = { nofree nosync nounwind willreturn } +; CHECK: attributes #1 = { nounwind } diff --git a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll --- a/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MemDepAnalysis/simple.ll @@ -11,7 +11,7 @@ define void @test1(i32* %Q, i32* %P) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: store i32 0, i32* [[P:%.*]] +; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4 ; CHECK-NEXT: ret void ; %DEAD = load i32, i32* %Q @@ -56,7 +56,7 @@ define void @test4(i32* %Q) { ; CHECK-LABEL: @test4( ; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q:%.*]], align 4 -; CHECK-NEXT: store volatile i32 [[A]], i32* [[Q]] +; CHECK-NEXT: store volatile i32 [[A]], i32* [[Q]], align 4 ; CHECK-NEXT: ret void ; %a = load i32, i32* %Q @@ -133,9 +133,9 @@ ; Do not delete stores that are only partially killed. define i32 @test8() { ; CHECK-LABEL: @test8( -; CHECK-NEXT: [[V:%.*]] = alloca i32 -; CHECK-NEXT: store i32 1234567, i32* [[V]] -; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[V]] +; CHECK-NEXT: [[V:%.*]] = alloca i32, align 4 +; CHECK-NEXT: store i32 1234567, i32* [[V]], align 4 +; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[V]], align 4 ; CHECK-NEXT: ret i32 [[X]] ; %V = alloca i32 @@ -182,8 +182,8 @@ ; va_arg has fuzzy dependence, the store shouldn't be zapped. define double @test10(i8* %X) { ; CHECK-LABEL: @test10( -; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8* -; CHECK-NEXT: store i8* [[X:%.*]], i8** [[X_ADDR]] +; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i8*, align 8 +; CHECK-NEXT: store i8* [[X:%.*]], i8** [[X_ADDR]], align 8 ; CHECK-NEXT: [[TMP_0:%.*]] = va_arg i8** [[X_ADDR]], double ; CHECK-NEXT: ret double [[TMP_0]] ; @@ -234,7 +234,7 @@ ; CHECK-NEXT: [[PTR:%.*]] = tail call i8* @malloc(i32 4) ; CHECK-NEXT: [[P:%.*]] = bitcast i8* [[PTR]] to i32* ; CHECK-NEXT: call void @test13f() -; CHECK-NEXT: store i32 0, i32* [[P]] +; CHECK-NEXT: store i32 0, i32* [[P]], align 4 ; CHECK-NEXT: ret i32* [[P]] ; %ptr = tail call i8* @malloc(i32 4) @@ -253,7 +253,7 @@ ; CHECK-NEXT: [[P_BC:%.*]] = bitcast i8* [[P]] to i32* ; CHECK-NEXT: [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)* ; CHECK-NEXT: call void @test13f() -; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]] +; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]], align 4 ; CHECK-NEXT: ret i32 addrspace(1)* [[P]] ; %p = tail call i8* @malloc(i32 4) @@ -287,8 +287,9 @@ ; Dead store on an aligned_alloc: should know that %M doesn't alias with %A. define i32 @test14a(i8* %M, i8 %value) { ; CHECK-LABEL: @test14a( -; CHECK-NOT: store -; CHECK: ret i32 0 +; CHECK-NEXT: [[A:%.*]] = tail call i8* @aligned_alloc(i32 32, i32 1024) +; CHECK-NEXT: tail call void @free(i8* [[A]]) +; CHECK-NEXT: ret i32 0 ; %A = tail call i8* @aligned_alloc(i32 32, i32 1024) store i8 %value, i8* %A @@ -481,7 +482,7 @@ ; CHECK-LABEL: @test19( ; CHECK-NEXT: bb: ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i32 }, { i32 }* [[ARG5:%.*]], i32 0, i32 0 -; CHECK-NEXT: store i32 912, i32* [[TMP7]] +; CHECK-NEXT: store i32 912, i32* [[TMP7]], align 4 ; CHECK-NEXT: call void @test19f({ i32 }* byval align 4 [[ARG5]]) ; CHECK-NEXT: ret void ; @@ -531,7 +532,7 @@ ; CHECK-NEXT: store i8 97, i8* [[ARRAYIDX]], align 1 ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], [2 x i8]* [[X]], i64 0, i64 1 ; CHECK-NEXT: store i8 0, i8* [[ARRAYIDX1]], align 1 -; CHECK-NEXT: [[CALL:%.*]] = call i8* @strdup(i8* [[ARRAYIDX]]) #3 +; CHECK-NEXT: [[CALL:%.*]] = call i8* @strdup(i8* [[ARRAYIDX]]) #4 ; CHECK-NEXT: ret i8* [[CALL]] ; %x = alloca [2 x i8], align 1 @@ -569,7 +570,7 @@ ; CHECK-NEXT: [[P_4:%.*]] = getelementptr i8, i8* [[P:%.*]], i64 4 ; CHECK-NEXT: [[TMP:%.*]] = load i8, i8* [[P_4]], align 1 ; CHECK-NEXT: store i8 0, i8* [[P_4]], align 1 -; CHECK-NEXT: [[Q:%.*]] = call i8* @strdup(i8* [[P]]) #6 +; CHECK-NEXT: [[Q:%.*]] = call i8* @strdup(i8* [[P]]) #7 ; CHECK-NEXT: store i8 [[TMP]], i8* [[P_4]], align 1 ; CHECK-NEXT: ret i8* [[Q]] ; @@ -794,9 +795,9 @@ ; Don't remove redundant store: unknown_func could unwind define void @test34(i32* noalias %p) { ; CHECK-LABEL: @test34( -; CHECK-NEXT: store i32 1, i32* [[P:%.*]] +; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4 ; CHECK-NEXT: call void @unknown_func() -; CHECK-NEXT: store i32 0, i32* [[P]] +; CHECK-NEXT: store i32 0, i32* [[P]], align 4 ; CHECK-NEXT: ret void ; store i32 1, i32* %p @@ -809,7 +810,7 @@ define void @test35(i32* noalias %p) { ; CHECK-LABEL: @test35( ; CHECK-NEXT: call void @unknown_func() -; CHECK-NEXT: store i32 0, i32* [[P:%.*]] +; CHECK-NEXT: store i32 0, i32* [[P:%.*]], align 4 ; CHECK-NEXT: ret void ; call void @unknown_func() @@ -925,9 +926,9 @@ ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]] -; CHECK-NEXT: store i8 1, i8* [[P_NEXT]] +; CHECK-NEXT: store i8 1, i8* [[P_NEXT]], align 1 ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15 ; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]] ; CHECK: return: @@ -958,11 +959,11 @@ ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT:%.*]] ] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]] -; CHECK-NEXT: store i8 1, i8* [[P_NEXT]] +; CHECK-NEXT: store i8 1, i8* [[P_NEXT]], align 1 ; CHECK-NEXT: br label [[CONT]] ; CHECK: cont: ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15 ; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]] ; CHECK: return: @@ -1004,7 +1005,7 @@ ; CHECK-NEXT: br label [[CONT]] ; CHECK: cont: ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15 ; CHECK-NEXT: br i1 [[CONTINUE]], label [[LOOP]], label [[RETURN:%.*]] ; CHECK: return: @@ -1037,11 +1038,11 @@ ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[CONT_2:%.*]] ] ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]] -; CHECK-NEXT: store i8 1, i8* [[P_NEXT]] +; CHECK-NEXT: store i8 1, i8* [[P_NEXT]], align 1 ; CHECK-NEXT: br label [[CONT:%.*]] ; CHECK: cont: ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: br label [[CONT_2]] ; CHECK: cont.2: ; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15 @@ -1082,10 +1083,10 @@ ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[P_NEXT:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV_NEXT]] ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[INDVARS_IV]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: br label [[CONT:%.*]] ; CHECK: cont: -; CHECK-NEXT: store i8 1, i8* [[P_NEXT]] +; CHECK-NEXT: store i8 1, i8* [[P_NEXT]], align 1 ; CHECK-NEXT: br label [[CONT_2]] ; CHECK: cont.2: ; CHECK-NEXT: [[CONTINUE:%.*]] = icmp ugt i64 [[INDVARS_IV]], 15 @@ -1127,16 +1128,16 @@ ; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK: true: ; CHECK-NEXT: [[P_1:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 1 -; CHECK-NEXT: store i8 1, i8* [[P_1]] +; CHECK-NEXT: store i8 1, i8* [[P_1]], align 1 ; CHECK-NEXT: br label [[CONT:%.*]] ; CHECK: false: ; CHECK-NEXT: [[P_2:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 2 -; CHECK-NEXT: store i8 1, i8* [[P_2]] +; CHECK-NEXT: store i8 1, i8* [[P_2]], align 1 ; CHECK-NEXT: br label [[CONT]] ; CHECK: cont: ; CHECK-NEXT: [[OFFSET:%.*]] = phi i64 [ 2, [[TRUE]] ], [ 1, [[FALSE]] ] ; CHECK-NEXT: [[P:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 [[OFFSET]] -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, i8* [[P]], align 1 ; CHECK-NEXT: br label [[RETURN:%.*]] ; CHECK: return: ; CHECK-NEXT: ret i32 0 @@ -1176,10 +1177,10 @@ ; CHECK-NEXT: [[P_2:%.*]] = getelementptr inbounds i8, i8* [[M]], i64 2 ; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK: true: -; CHECK-NEXT: store i8 1, i8* [[P_1]] +; CHECK-NEXT: store i8 1, i8* [[P_1]], align 1 ; CHECK-NEXT: br label [[CONT:%.*]] ; CHECK: false: -; CHECK-NEXT: store i8 1, i8* [[P_1]] +; CHECK-NEXT: store i8 1, i8* [[P_1]], align 1 ; CHECK-NEXT: br label [[CONT]] ; CHECK: cont: ; CHECK-NEXT: br label [[RETURN:%.*]] diff --git a/llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll b/llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll --- a/llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll +++ b/llvm/test/Transforms/Inline/dynamic-alloca-simplified-large.ll @@ -46,7 +46,7 @@ ; CHECK-NEXT: [[SAVEDSTACK:%.*]] = call i8* @llvm.stacksave() ; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VLA_I]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 60000, i8* [[TMP0]]) -; CHECK-NEXT: call void @extern_call(float* nonnull [[VLA_I]]) #2 +; CHECK-NEXT: call void @extern_call(float* nonnull [[VLA_I]]) #3 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[VLA_I]] to i8* ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 60000, i8* [[TMP1]]) ; CHECK-NEXT: call void @llvm.stackrestore(i8* [[SAVEDSTACK]]) @@ -155,7 +155,7 @@ ; CHECK-NEXT: [[TMP0:%.*]] = alloca i8, i64 [[CONV_I]], align 8 ; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT:%.*]] ; CHECK: if.end.i: -; CHECK-NEXT: [[CALL_I:%.*]] = tail call i8* @malloc(i64 [[CONV_I]]) #2 +; CHECK-NEXT: [[CALL_I:%.*]] = tail call i8* @malloc(i64 [[CONV_I]]) #3 ; CHECK-NEXT: br label [[STACK_ALLOCATE_EXIT]] ; CHECK: stack_allocate.exit: ; CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i8* [ [[TMP0]], [[IF_THEN_I]] ], [ [[CALL_I]], [[IF_END_I]] ] diff --git a/llvm/test/Transforms/Inline/inline_invoke.ll b/llvm/test/Transforms/Inline/inline_invoke.ll --- a/llvm/test/Transforms/Inline/inline_invoke.ll +++ b/llvm/test/Transforms/Inline/inline_invoke.ll @@ -345,5 +345,5 @@ ; CHECK: attributes [[NUW]] = { nounwind } ; CHECK: attributes #1 = { nounwind readnone } ; CHECK: attributes #2 = { ssp uwtable } -; CHECK: attributes #3 = { argmemonly nounwind willreturn } +; CHECK: attributes #3 = { argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #4 = { noreturn nounwind } diff --git a/llvm/test/Transforms/Inline/noalias-calls.ll b/llvm/test/Transforms/Inline/noalias-calls.ll --- a/llvm/test/Transforms/Inline/noalias-calls.ll +++ b/llvm/test/Transforms/Inline/noalias-calls.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature ; RUN: opt -basic-aa -inline -enable-noalias-to-md-conversion -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -41,27 +42,28 @@ ; CHECK: define void @foo(i8* nocapture %a, i8* nocapture readonly %c, i8* nocapture %b) #2 { ; CHECK: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #1, !noalias !0 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #1, !noalias !3 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #1, !alias.scope !5 -; CHECK: call void @hey() #1, !noalias !5 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #1, !noalias !3 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #2, !noalias !0 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #2, !noalias !3 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #2, !alias.scope !5 +; CHECK: call void @hey() #2, !noalias !5 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #2, !noalias !3 ; CHECK: ret void ; CHECK: } ; CHECK: define void @foo_cs(i8* nocapture %a, i8* nocapture readonly %c, i8* nocapture %b) #2 { ; CHECK: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #1, !noalias !6 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #1, !noalias !9 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #1, !alias.scope !11 -; CHECK: call void @hey() #1, !noalias !11 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #1, !noalias !9 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %b, i64 16, i1 false) #2, !noalias !6 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %b, i8* align 16 %c, i64 16, i1 false) #2, !noalias !9 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %a, i8* align 16 %c, i64 16, i1 false) #2, !alias.scope !11 +; CHECK: call void @hey() #2, !noalias !11 +; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %{{.*}}, i8* align 16 %c, i64 16, i1 false) #2, !noalias !9 ; CHECK: ret void ; CHECK: } -attributes #0 = { nounwind argmemonly willreturn } -attributes #1 = { nounwind } -attributes #2 = { nounwind uwtable } +attributes #0 = { argmemonly nofree nosync nounwind willreturn } +attributes #1 = { argmemonly nounwind willreturn } +attributes #2 = { nounwind } +attributes #3 = { nounwind uwtable } ; CHECK: !0 = !{!1} ; CHECK: !1 = distinct !{!1, !2, !"hello: %c"} @@ -76,4 +78,3 @@ ; CHECK: !9 = !{!10} ; CHECK: !10 = distinct !{!10, !8, !"hello_cs: %a"} ; CHECK: !11 = !{!10, !7} - diff --git a/llvm/test/Transforms/InstCombine/sdiv-guard.ll b/llvm/test/Transforms/InstCombine/sdiv-guard.ll --- a/llvm/test/Transforms/InstCombine/sdiv-guard.ll +++ b/llvm/test/Transforms/InstCombine/sdiv-guard.ll @@ -6,9 +6,8 @@ ; Regression test. If %flag is false then %s == 0 and guard should be triggered. define i32 @a(i1 %flag, i32 %X) nounwind readnone { ; CHECK-LABEL: @a( -; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[X:%.*]], 0 -; CHECK-NEXT: [[CMP:%.*]] = and i1 [[CMP1]], [[FLAG:%.*]] -; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #1 [ "deopt"() ] +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[X:%.*]], 0 +; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[CMP]]) #2 [ "deopt"() ] ; CHECK-NEXT: [[R:%.*]] = sdiv i32 100, [[X]] ; CHECK-NEXT: ret i32 [[R]] ; diff --git a/llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll b/llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll --- a/llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll +++ b/llvm/test/Transforms/LowerMatrixIntrinsics/strided-load-double.ll @@ -66,4 +66,4 @@ } ; CHECK: declare <9 x double> @llvm.matrix.column.major.load.v9f64(double* nocapture, i64, i1 immarg, i32 immarg, i32 immarg) [[READONLY]] -; CHECK: attributes [[READONLY]] = { argmemonly nosync nounwind readonly willreturn } +; CHECK: attributes [[READONLY]] = { argmemonly nofree nosync nounwind readonly willreturn } diff --git a/llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll b/llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll --- a/llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll +++ b/llvm/test/Transforms/LowerMatrixIntrinsics/strided-store-double.ll @@ -65,6 +65,6 @@ declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double*, i64, i1, i32, i32) declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double*, i64, i1, i32, i32) -; CHECK: declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 -; CHECK: declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 -; CHECK: attributes #0 = { argmemonly nosync nounwind willreturn writeonly } +; CHECK: declare void @llvm.matrix.column.major.store.v6f64(<6 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 +; CHECK: declare void @llvm.matrix.column.major.store.v10f64(<10 x double>, double* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg) #0 +; CHECK: attributes #0 = { argmemonly nofree nosync nounwind willreturn writeonly } diff --git a/llvm/test/Transforms/MemCpyOpt/memcpy.ll b/llvm/test/Transforms/MemCpyOpt/memcpy.ll --- a/llvm/test/Transforms/MemCpyOpt/memcpy.ll +++ b/llvm/test/Transforms/MemCpyOpt/memcpy.ll @@ -248,6 +248,7 @@ declare void @f2(%struct.big*) ; CHECK: attributes [[$NUW]] = { nounwind } -; CHECK: attributes #1 = { argmemonly nounwind willreturn } +; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn } ; CHECK: attributes #2 = { nounwind ssp } ; CHECK: attributes #3 = { nounwind ssp uwtable } +; CHECK: attributes #4 = { argmemonly nofree nosync nounwind willreturn writeonly } diff --git a/llvm/test/Transforms/ObjCARC/basic.ll b/llvm/test/Transforms/ObjCARC/basic.ll --- a/llvm/test/Transforms/ObjCARC/basic.ll +++ b/llvm/test/Transforms/ObjCARC/basic.ll @@ -3087,5 +3087,5 @@ !5 = !{i32 2, !"Debug Info Version", i32 3} ; CHECK: attributes [[NUW]] = { nounwind } -; CHECK: attributes #1 = { nounwind readnone speculatable willreturn } +; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK: ![[RELEASE]] = !{} diff --git a/llvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll b/llvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll --- a/llvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll +++ b/llvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll @@ -105,7 +105,7 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone ; CHECK: attributes #0 = { ssp uwtable } -; CHECK: attributes #1 = { nounwind readnone speculatable willreturn } +; CHECK: attributes #1 = { nofree nosync nounwind readnone speculatable willreturn } ; CHECK: attributes #2 = { nonlazybind } ; CHECK: attributes [[NUW]] = { nounwind } ; CHECK: attributes #4 = { noinline ssp uwtable } diff --git a/llvm/test/Transforms/ObjCARC/nested.ll b/llvm/test/Transforms/ObjCARC/nested.ll --- a/llvm/test/Transforms/ObjCARC/nested.ll +++ b/llvm/test/Transforms/ObjCARC/nested.ll @@ -821,5 +821,5 @@ ; CHECK: attributes [[NUW]] = { nounwind } -; CHECK: attributes #1 = { argmemonly nounwind willreturn writeonly } +; CHECK: attributes #1 = { argmemonly nofree nosync nounwind willreturn writeonly } ; CHECK: attributes #2 = { nonlazybind } diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/statepoint-attrs.ll b/llvm/test/Transforms/RewriteStatepointsForGC/statepoint-attrs.ll --- a/llvm/test/Transforms/RewriteStatepointsForGC/statepoint-attrs.ll +++ b/llvm/test/Transforms/RewriteStatepointsForGC/statepoint-attrs.ll @@ -7,7 +7,7 @@ ; copy over norecurse noimplicitfloat to statepoint call define void @test1(i8 addrspace(1)* %arg) gc "statepoint-example" { ; CHECK-LABEL: test1( -; CHECK: %statepoint_token = call token (i64, i32, void (i8 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i8f(i64 2882400000, i32 0, void (i8 addrspace(1)*)* @f, i32 1, i32 0, i8 addrspace(1)* %arg, i32 0, i32 0) #1 [ "gc-live"(i8 addrspace(1)* %arg) ] +; CHECK: %statepoint_token = call token (i64, i32, void (i8 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i8f(i64 2882400000, i32 0, void (i8 addrspace(1)*)* @f, i32 1, i32 0, i8 addrspace(1)* %arg, i32 0, i32 0) #2 [ "gc-live"(i8 addrspace(1)* %arg) ] call void @f(i8 addrspace(1)* %arg) #1 ret void diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call.ll b/llvm/test/Transforms/SLPVectorizer/X86/call.ll --- a/llvm/test/Transforms/SLPVectorizer/X86/call.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/call.ll @@ -173,5 +173,5 @@ ; CHECK: declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) [[ATTR0]] ; CHECK: declare <2 x double> @llvm.exp2.v2f64(<2 x double>) [[ATTR0]] -; CHECK: attributes [[ATTR0]] = { nounwind readnone speculatable willreturn } +; CHECK: attributes [[ATTR0]] = { nofree nosync nounwind readnone speculatable willreturn } diff --git a/llvm/test/Verifier/fp-intrinsics.ll b/llvm/test/Verifier/fp-intrinsics.ll --- a/llvm/test/Verifier/fp-intrinsics.ll +++ b/llvm/test/Verifier/fp-intrinsics.ll @@ -12,7 +12,7 @@ ; attached to the FP intrinsic. ; CHECK1: declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata) #[[ATTR:[0-9]+]] ; CHECK1: declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata) #[[ATTR]] -; CHECK1: attributes #[[ATTR]] = { inaccessiblememonly nounwind willreturn } +; CHECK1: attributes #[[ATTR]] = { inaccessiblememonly nofree nosync nounwind willreturn } ; Note: FP exceptions aren't usually caught through normal unwind mechanisms, ; but we may want to revisit this for asynchronous exception handling. define double @f1(double %a, double %b) #0 {