Index: llvm/lib/Target/AMDGPU/AMDGPUGISel.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -68,19 +68,12 @@ GIComplexOperandMatcher, GIComplexPatternEquiv; -// FIXME: Why are the atomic versions separated? def gi_flat_offset : GIComplexOperandMatcher, GIComplexPatternEquiv; def gi_flat_offset_signed : GIComplexOperandMatcher, GIComplexPatternEquiv; -def gi_flat_atomic : - GIComplexOperandMatcher, - GIComplexPatternEquiv; -def gi_flat_signed_atomic : - GIComplexOperandMatcher, - GIComplexPatternEquiv; def gi_mubuf_scratch_offset : GIComplexOperandMatcher, Index: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -234,10 +234,6 @@ template bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr, SDValue &Offset, SDValue &SLC) const; - bool SelectFlatAtomic(SDNode *N, SDValue Addr, SDValue &VAddr, - SDValue &Offset, SDValue &SLC) const; - bool SelectFlatAtomicSigned(SDNode *N, SDValue Addr, SDValue &VAddr, - SDValue &Offset, SDValue &SLC) const; bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset, bool &Imm) const; @@ -1756,22 +1752,6 @@ return true; } -bool AMDGPUDAGToDAGISel::SelectFlatAtomic(SDNode *N, - SDValue Addr, - SDValue &VAddr, - SDValue &Offset, - SDValue &SLC) const { - return SelectFlatOffset(N, Addr, VAddr, Offset, SLC); -} - -bool AMDGPUDAGToDAGISel::SelectFlatAtomicSigned(SDNode *N, - SDValue Addr, - SDValue &VAddr, - SDValue &Offset, - SDValue &SLC) const { - return SelectFlatOffset(N, Addr, VAddr, Offset, SLC); -} - bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset, bool &Imm) const { ConstantSDNode *C = dyn_cast(ByteOffsetNode); Index: llvm/lib/Target/AMDGPU/FLATInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/FLATInstructions.td +++ llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -6,11 +6,8 @@ // //===----------------------------------------------------------------------===// -def FLATAtomic : ComplexPattern; def FLATOffset : ComplexPattern", [], [SDNPWantRoot], -10>; - def FLATOffsetSigned : ComplexPattern", [], [SDNPWantRoot], -10>; -def FLATSignedAtomic : ComplexPattern; //===----------------------------------------------------------------------===// // FLAT classes @@ -326,7 +323,7 @@ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc), " $vdst, $vaddr, $vdata$offset glc$slc", [(set vt:$vdst, - (atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>, + (atomic (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>, GlobalSaddrTable<0, opName#"_rtn">, AtomicNoRet { let FPAtomic = isFP; @@ -381,7 +378,7 @@ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc), " $vdst, $vaddr, $vdata, off$offset glc$slc", [(set vt:$vdst, - (atomic (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>, + (atomic (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>, GlobalSaddrTable<0, opName#"_rtn">, AtomicNoRet { let has_saddr = 1; @@ -744,11 +741,6 @@ (inst $vaddr, $offset, 0, 0, $slc, $in) >; -class FlatLoadAtomicPat : GCNPat < - (vt (node (FLATAtomic (i64 VReg_64:$vaddr), i16:$offset, i1:$slc))), - (inst $vaddr, $offset, 0, 0, $slc) ->; - class FlatLoadSignedPat : GCNPat < (vt (node (FLATOffsetSigned (i64 VReg_64:$vaddr), i16:$offset, i1:$slc))), (inst $vaddr, $offset, 0, 0, $slc) @@ -767,31 +759,31 @@ class FlatStoreAtomicPat : GCNPat < // atomic store follows atomic binop convention so the address comes // first. - (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), + (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (inst $vaddr, rc:$data, $offset, 0, 0, $slc) >; class FlatStoreSignedAtomicPat : GCNPat < // atomic store follows atomic binop convention so the address comes // first. - (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), + (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (inst $vaddr, rc:$data, $offset, 0, 0, $slc) >; class FlatAtomicPat : GCNPat < - (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), + (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), (inst $vaddr, $data, $offset, $slc) >; class FlatAtomicPatNoRtn : GCNPat < - (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), + (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (inst VReg_64:$vaddr, getVregSrcForVT.ret:$data, $offset, $slc) >; class FlatSignedAtomicPat : GCNPat < - (vt (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), + (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), (inst $vaddr, $data, $offset, $slc) >; @@ -809,8 +801,8 @@ def : FlatLoadPat ; def : FlatLoadPat ; -def : FlatLoadAtomicPat ; -def : FlatLoadAtomicPat ; +def : FlatLoadPat ; +def : FlatLoadPat ; def : FlatStorePat ; def : FlatStorePat ; @@ -917,8 +909,9 @@ def : FlatStoreSignedPat ; } -def : FlatLoadAtomicPat ; -def : FlatLoadAtomicPat ; +// FIXME: Should be using signed pat +def : FlatLoadPat ; +def : FlatLoadPat ; def : FlatStoreSignedPat ; def : FlatStoreSignedPat ;