diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -655,8 +655,7 @@ [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128, FeatureWavefrontSize64, FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureLDSBankCount32, FeatureMovrel, - FeatureTrigReducedRange, FeatureDoesNotSupportSRAMECC, - FeatureDoesNotSupportXNACK] + FeatureTrigReducedRange] >; def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS", @@ -665,7 +664,7 @@ FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange, FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, - FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC] + FeatureDsSrc2Insts] >; def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS", @@ -678,7 +677,7 @@ FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP, FeatureIntClamp, FeatureTrigReducedRange, FeatureGFX8Insts, FeatureGFX7GFX8GFX9Insts, FeatureSMemTimeInst, FeatureMadMacF32Insts, - FeatureDsSrc2Insts, FeatureDoesNotSupportSRAMECC, FeatureFastDenormalF32 + FeatureDsSrc2Insts, FeatureFastDenormalF32 ] >; @@ -712,7 +711,7 @@ FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts, FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking, FeatureVOP3Literal, FeatureDPP8, - FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC, + FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureGFX10A16, FeatureFastDenormalF32, FeatureG16 ] >; @@ -725,19 +724,16 @@ FeatureFastFMAF32, HalfRate64Ops, FeatureLDSBankCount32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion6_0_1 : FeatureSet< [FeatureSouthernIslands, FeatureLDSBankCount32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion7_0_0 : FeatureSet< [FeatureSeaIslands, FeatureLDSBankCount32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion7_0_1 : FeatureSet< @@ -745,26 +741,22 @@ HalfRate64Ops, FeatureLDSBankCount32, FeatureFastFMAF32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion7_0_2 : FeatureSet< [FeatureSeaIslands, FeatureLDSBankCount16, FeatureFastFMAF32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion7_0_3 : FeatureSet< [FeatureSeaIslands, FeatureLDSBankCount16, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion7_0_4 : FeatureSet< [FeatureSeaIslands, FeatureLDSBankCount32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion8_0_1 : FeatureSet< @@ -781,14 +773,12 @@ FeatureLDSBankCount32, FeatureSGPRInitBug, FeatureUnpackedD16VMem, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion8_0_3 : FeatureSet< [FeatureVolcanicIslands, FeatureLDSBankCount32, FeatureUnpackedD16VMem, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion8_1_0 : FeatureSet< @@ -801,24 +791,19 @@ [FeatureGFX9, FeatureMadMixInsts, FeatureLDSBankCount32, - FeatureCodeObjectV3, - FeatureDoesNotSupportXNACK, - FeatureDoesNotSupportSRAMECC]>; + FeatureCodeObjectV3]>; def FeatureISAVersion9_0_2 : FeatureSet< [FeatureGFX9, FeatureMadMixInsts, FeatureLDSBankCount32, FeatureXNACK, - FeatureDoesNotSupportSRAMECC, FeatureCodeObjectV3]>; def FeatureISAVersion9_0_4 : FeatureSet< [FeatureGFX9, FeatureLDSBankCount32, FeatureFmaMixInsts, - FeatureDoesNotSupportXNACK, - FeatureDoesNotSupportSRAMECC, FeatureCodeObjectV3]>; def FeatureISAVersion9_0_6 : FeatureSet< @@ -829,7 +814,6 @@ FeatureDLInsts, FeatureDot1Insts, FeatureDot2Insts, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; def FeatureISAVersion9_0_8 : FeatureSet< @@ -847,6 +831,7 @@ FeatureMAIInsts, FeaturePkFmacF16Inst, FeatureAtomicFaddInsts, + FeatureXNACK, FeatureSRAMECC, FeatureMFMAInlineLiteralBug, FeatureCodeObjectV3]>; @@ -889,7 +874,6 @@ FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureLdsMisalignedBug, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3])>; def FeatureISAVersion10_1_1 : FeatureSet< @@ -910,7 +894,6 @@ FeatureSMemTimeInst, FeatureMadMacF32Insts, FeatureDsSrc2Insts, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3])>; def FeatureISAVersion10_1_2 : FeatureSet< @@ -932,7 +915,6 @@ FeatureMadMacF32Insts, FeatureDsSrc2Insts, FeatureLdsMisalignedBug, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3])>; def FeatureISAVersion10_3_0 : FeatureSet< @@ -947,7 +929,6 @@ FeatureDot6Insts, FeatureNSAEncoding, FeatureWavefrontSize32, - FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -61,6 +61,20 @@ GFX10 = 8 }; + enum XnackSetting { + XnackDefault = 1, + XnackOn = 2, + XnackOff = 3, + XnackNotSupported = 4 + }; + + enum SramEccSetting { + SramEccDefault = 1, + SramEccOn = 2, + SramEccOff = 3, + SramEccNotSupported = 4 + }; + private: Triple TargetTriple; @@ -122,6 +136,14 @@ unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const; + /// Returns the current XNACK setting for the subtarget, possible options + /// are Off, On, Default, and NotSupported. + virtual XnackSetting getXnackSetting() const; + + /// Returns the current SRAMECC setting for the subtarget, possible options + /// are Off, On, Default, and NotSupported. + virtual SramEccSetting getSramEccSetting() const; + bool isAmdHsaOS() const { return TargetTriple.getOS() == Triple::AMDHSA; } @@ -288,6 +310,9 @@ LLVMTrapHandlerRegValue = 1 }; + XnackSetting getXnackSetting() const override; + SramEccSetting getSramEccSetting() const override; + private: /// GlobalISel related APIs. std::unique_ptr CallLoweringInfo; @@ -328,6 +353,8 @@ bool EnableDS128; bool EnablePRTStrictNull; bool DumpCode; + bool UseSRAMECCDefault; + bool UseXNACKDefault; // Subtarget statically properties set by tablegen bool FP64; @@ -418,6 +445,10 @@ // See COMPUTE_TMPRING_SIZE.WAVESIZE, 13-bit field in units of 256-dword. static const unsigned MaxWaveScratchSize = (256 * 4) * ((1 << 13) - 1); + // Initialize Xnack and SramEcc settings based on subtarget support and + // requested features. + void initializeXnackAndSramEcc(StringRef FS, StringRef GPU); + public: GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM); @@ -708,7 +739,13 @@ } bool isXNACKEnabled() const { - return EnableXNACK; + // FIXME: XNACK should be enabled with XnackDefault as well as XnackOn. We + // can then remove this function and start using getXnackSetting directly. + return getXnackSetting() == XnackOn; + } + + bool useDefaultXNACKSetting() const { + return UseXNACKDefault; } bool isCuModeEnabled() const { @@ -764,7 +801,9 @@ } bool d16PreservesUnusedBits() const { - return hasD16LoadStore() && !isSRAMECCEnabled(); + SramEccSetting Setting = getSramEccSetting(); + return hasD16LoadStore() && + (Setting == SramEccOff || Setting == SramEccNotSupported); } bool hasD16Images() const { @@ -872,8 +911,8 @@ return HasAtomicFaddInsts; } - bool isSRAMECCEnabled() const { - return EnableSRAMECC; + bool useDefaultSRAMECCSetting() const { + return UseSRAMECCDefault; } bool hasNoSdstCMPX() const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -20,6 +20,7 @@ #include "AMDGPURegisterBankInfo.h" #include "SIMachineFunctionInfo.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "Utils/AMDGPUBaseInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -78,7 +79,7 @@ // unset everything else if it is disabled // Assuming ECC is enabled is the conservative default. - SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,+sram-ecc,+xnack,"); + SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,"); if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA. FullFS += "+flat-for-global,+unaligned-buffer-access,+trap-handler,"; @@ -131,20 +132,7 @@ HasFminFmaxLegacy = getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS; - // Disable XNACK on targets where it is not enabled by default unless it is - // explicitly requested. - if (!FS.contains("+xnack") && DoesNotSupportXNACK && EnableXNACK) { - ToggleFeature(AMDGPU::FeatureXNACK); - EnableXNACK = false; - } - - // ECC is on by default, but turn it off if the hardware doesn't support it - // anyway. This matters for the gfx9 targets with d16 loads, but don't support - // ECC. - if (DoesNotSupportSRAMECC && EnableSRAMECC) { - ToggleFeature(AMDGPU::FeatureSRAMECC); - EnableSRAMECC = false; - } + initializeXnackAndSramEcc(FS, GPU); return *this; } @@ -201,6 +189,10 @@ EnablePRTStrictNull(false), DumpCode(false), + // Initialize with the conservative defaults. + UseSRAMECCDefault(true), + UseXNACKDefault(true), + FP64(false), GCN3Encoding(false), CIInsts(false), @@ -539,6 +531,14 @@ return alignTo(TotalSize, 4); } +AMDGPUSubtarget::XnackSetting AMDGPUSubtarget::getXnackSetting() const { + return XnackNotSupported; +} + +AMDGPUSubtarget::SramEccSetting AMDGPUSubtarget::getSramEccSetting() const { + return SramEccNotSupported; +} + R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS, const TargetMachine &TM) : R600GenSubtargetInfo(TT, GPU, FS), @@ -893,6 +893,114 @@ Mutations.push_back(std::make_unique(&InstrInfo)); } +void GCNSubtarget::initializeXnackAndSramEcc(StringRef FS, StringRef GPU) { + bool XnackOnSupportRequested = FS.contains("+xnack"); + bool SramEccOnSupportRequested = FS.contains("+sram-ecc"); + bool XnackOffSupportRequested = FS.contains("-xnack"); + bool SramEccOffSupportRequested = FS.contains("-sram-ecc"); + + bool SupportsXnack = AMDGPU::IsaInfo::isXnackSupported(this); + bool SupportsSramEcc = AMDGPU::IsaInfo::isXnackSupported(this); + + // Check if support for XNACK or SRAMECC is explicitly enabled or disabled. In + // these cases the subtarget is not asking for the portable default settings. + UseXNACKDefault = !(XnackOnSupportRequested || XnackOffSupportRequested); + UseSRAMECCDefault = !(SramEccOnSupportRequested || SramEccOffSupportRequested); + + if (XnackOnSupportRequested && !SupportsXnack) + report_fatal_error( + "Xnack On was requested for a processor that does not support it!"); + + if (SramEccOnSupportRequested && !SupportsSramEcc) + report_fatal_error( + "SramEcc On was requested for a processor that does not support it!"); + + if (XnackOffSupportRequested && !SupportsXnack) + report_fatal_error( + "Xnack Off was requested for a processor that does not support it!"); + + if (SramEccOffSupportRequested && !SupportsSramEcc) + report_fatal_error( + "SramEcc Off was requested for a processor that does not support it!"); + + // FIXME: These hacks are necessary to support backwards compatibility with the + // old defaults for xnack. When the new targetid feature is enabled this, + // along with the change in isXNACKEnabled can be updated to reflect the true + // intended meaning of "default" for these settings. + if (EnableXNACK) + UseXNACKDefault = false; + if (GPU == "generic" || GPU == "generic-hsa") { + UseSRAMECCDefault = true; + + // FIXME + UseXNACKDefault = false; + EnableXNACK = true; + } + + LLVM_DEBUG({ + XnackSetting Xnack = getXnackSetting(); + SramEccSetting SramEcc = getSramEccSetting(); + + dbgs() << "XNACK setting for subtarget: "; + switch (Xnack) { + case (AMDGPUSubtarget::XnackOn): + dbgs() << "On"; + break; + case (AMDGPUSubtarget::XnackOff): + dbgs() << "Off"; + break; + case (AMDGPUSubtarget::XnackDefault): + dbgs() << "Default"; + break; + case (AMDGPUSubtarget::XnackNotSupported): + dbgs() << "Not Supported"; + break; + }; + dbgs() << "\n"; + + dbgs() << "SRAMECC setting for subtarget: "; + switch (SramEcc) { + case (AMDGPUSubtarget::SramEccOn): + dbgs() << "On"; + break; + case (AMDGPUSubtarget::SramEccOff): + dbgs() << "Off"; + break; + case (AMDGPUSubtarget::SramEccDefault): + dbgs() << "Default"; + break; + case (AMDGPUSubtarget::SramEccNotSupported): + dbgs() << "Not Supported"; + break; + }; + dbgs() << "\n"; + }); +} + +AMDGPUSubtarget::XnackSetting GCNSubtarget::getXnackSetting() const { + if (!AMDGPU::IsaInfo::isXnackSupported(this)) + return XnackNotSupported; + + if (useDefaultXNACKSetting()) + return XnackDefault; + + if (EnableXNACK) + return XnackOn; + return XnackOff; +} + +AMDGPUSubtarget::SramEccSetting GCNSubtarget::getSramEccSetting() const { + if (!AMDGPU::IsaInfo::isSramEccSupported(this)) + return SramEccNotSupported; + + if (useDefaultSRAMECCSetting()) + return SramEccDefault; + + if (EnableSRAMECC) + return SramEccOn; + return SramEccOff; +} + const AMDGPUSubtarget &AMDGPUSubtarget::get(const MachineFunction &MF) { if (MF.getTarget().getTargetTriple().getArch() == Triple::amdgcn) return static_cast(MF.getSubtarget()); diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -180,6 +180,12 @@ unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs, Optional EnableWavefrontSize32 = None); +/// \returns True if the subtarget \p STI supports XNACK. +bool isXnackSupported(const MCSubtargetInfo *STI); + +/// \returns True if the subtarget \p STI supports SRAMECC. +bool isSramEccSupported(const MCSubtargetInfo *STI); + } // end namespace IsaInfo LLVM_READONLY diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -496,6 +496,49 @@ return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1; } +bool isXnackSupported(const MCSubtargetInfo *STI) { + AMDGPU::GPUKind AK = parseArchAMDGCN(STI->getCPU()); + if (AK == AMDGPU::GPUKind::GK_NONE) + AK = parseArchR600(STI->getCPU()); + + switch (AK) { + case GK_NONE: + case GK_GFX801: + case GK_GFX802: + case GK_GFX803: + case GK_GFX810: + case GK_GFX900: + case GK_GFX902: + case GK_GFX904: + case GK_GFX906: + case GK_GFX908: + case GK_GFX909: + case GK_GFX1010: + case GK_GFX1011: + case GK_GFX1012: + case GK_GFX1030: + case GK_GFX1031: + return true; + default: + return false; + } +} + +/// \returns True if the subtarget \p STI has support for SRAMECC. +bool isSramEccSupported(const MCSubtargetInfo *STI) { + AMDGPU::GPUKind AK = parseArchAMDGCN(STI->getCPU()); + if (AK == AMDGPU::GPUKind::GK_NONE) + AK = parseArchR600(STI->getCPU()); + + switch (AK) { + case GK_GFX906: + case GK_GFX908: + return true; + default: + return false; + } +} + } // end namespace IsaInfo void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, diff --git a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll --- a/llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll +++ b/llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll @@ -1,7 +1,3 @@ -; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx902 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX902 %s -; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx902 -mattr=-sram-ecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX902 %s -; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx902 -mattr=+sram-ecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX902 %s - ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=-sram-ecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sram-ecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s @@ -9,17 +5,6 @@ ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s -; NO-SRAM-ECC-GFX902: Flags [ -; NO-SRAM-ECC-GFX902-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX902 (0x2D) -; NO-SRAM-ECC-GFX902-NEXT: EF_AMDGPU_XNACK (0x100) -; NO-SRAM-ECC-GFX902-NEXT: ] - -; SRAM-ECC-GFX902: Flags [ -; SRAM-ECC-GFX902-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX902 (0x2D) -; SRAM-ECC-GFX902-NEXT: EF_AMDGPU_SRAM_ECC (0x200) -; SRAM-ECC-GFX902-NEXT: EF_AMDGPU_XNACK (0x100) -; SRAM-ECC-GFX902-NEXT: ] - ; NO-SRAM-ECC-GFX906: Flags [ ; NO-SRAM-ECC-GFX906-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F) ; NO-SRAM-ECC-GFX906-NEXT: ] diff --git a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-default.ll b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-default.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-default.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=NOT-SUPPORTED %s +; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=DEFAULT %s +; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=DEFAULT %s + +; REQUIRES: asserts + +; NOT-SUPPORTED: SRAMECC setting for subtarget: Not Supported +; DEFAULT: SRAMECC setting for subtarget: Default +define void @sramecc-subtarget-feature-default() #0 { + ret void +} + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll @@ -0,0 +1,14 @@ +; RUN: not --crash llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s +; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s + +; REQUIRES: asserts + +; ERR: LLVM ERROR: SramEcc Off was requested for a processor that does not support it! +; OFF: SRAMECC setting for subtarget: Off + +define void @sramecc-subtarget-feature-disabled() #0 { + ret void +} + +attributes #0 = { "target-features"="-sram-ecc" } diff --git a/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll @@ -0,0 +1,13 @@ +; RUN: not --crash llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s +; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s + +; REQUIRES: asserts + +; ERR: LLVM ERROR: SramEcc On was requested for a processor that does not support it! +; ON: SRAMECC setting for subtarget: On +define void @sramecc-subtarget-feature-enabled() #0 { + ret void +} + +attributes #0 = { "target-features"="+sram-ecc" } diff --git a/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-default.ll b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-default.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-default.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=NOT-SUPPORTED %s +; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=NOT-SUPPORTED %s +; RUN: llc -march=amdgcn -mcpu=gfx802 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=DEFAULT %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=DEFAULT %s +; RUN: llc -march=amdgcn -mcpu=gfx902 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=DEFAULT %s + +; REQUIRES: asserts + +; Some subtargets have a default setting of 'On' instead of 'Default' to maintain +; backwards compatibility. This is a temporary measure until the new TargetID is +; implemented. + +; NOT-SUPPORTED: XNACK setting for subtarget: Not Supported +; DEFAULT: XNACK setting for subtarget: Default +; ON: XNACK setting for subtarget: On +define void @xnack-subtarget-feature-default() #0 { + ret void +} + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll @@ -0,0 +1,17 @@ +; RUN: not --crash llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: not --crash llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: llc -march=amdgcn -mcpu=gfx802 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s +; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=OFF %s + +; REQUIRES: asserts + +; ERR: LLVM ERROR: Xnack Off was requested for a processor that does not support it! +; OFF: XNACK setting for subtarget: Off + +define void @xnack-subtarget-feature-disabled() #0 { + ret void +} + +attributes #0 = { "target-features"="-xnack" } diff --git a/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll @@ -0,0 +1,16 @@ +; RUN: not --crash llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: not --crash llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck --check-prefix=ERR %s +; RUN: llc -march=amdgcn -mcpu=gfx802 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s +; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check-prefix=ON %s + +; REQUIRES: asserts + +; ERR: LLVM ERROR: Xnack On was requested for a processor that does not support it! +; ON: XNACK setting for subtarget: On +define void @xnack-subtarget-feature-enabled() #0 { + ret void +} + +attributes #0 = { "target-features"="+xnack" }