Index: include/llvm/CodeGen/MachineValueType.h =================================================================== --- include/llvm/CodeGen/MachineValueType.h +++ include/llvm/CodeGen/MachineValueType.h @@ -86,22 +86,23 @@ v4i64 = 39, // 4 x i64 v8i64 = 40, // 8 x i64 v16i64 = 41, // 16 x i64 - + v1i128 = 42, // 1 x i128 + FIRST_INTEGER_VECTOR_VALUETYPE = v2i1, - LAST_INTEGER_VECTOR_VALUETYPE = v16i64, + LAST_INTEGER_VECTOR_VALUETYPE = v1i128, - v2f16 = 42, // 2 x f16 - v4f16 = 43, // 4 x f16 - v8f16 = 44, // 8 x f16 - v1f32 = 45, // 1 x f32 - v2f32 = 46, // 2 x f32 - v4f32 = 47, // 4 x f32 - v8f32 = 48, // 8 x f32 - v16f32 = 49, // 16 x f32 - v1f64 = 50, // 1 x f64 - v2f64 = 51, // 2 x f64 - v4f64 = 52, // 4 x f64 - v8f64 = 53, // 8 x f64 + v2f16 = 43, // 2 x f16 + v4f16 = 44, // 4 x f16 + v8f16 = 45, // 8 x f16 + v1f32 = 46, // 1 x f32 + v2f32 = 47, // 2 x f32 + v4f32 = 48, // 4 x f32 + v8f32 = 49, // 8 x f32 + v16f32 = 50, // 16 x f32 + v1f64 = 51, // 1 x f64 + v2f64 = 52, // 2 x f64 + v4f64 = 53, // 4 x f64 + v8f64 = 54, // 8 x f64 FIRST_FP_VECTOR_VALUETYPE = v2f16, LAST_FP_VECTOR_VALUETYPE = v8f64, @@ -109,18 +110,18 @@ FIRST_VECTOR_VALUETYPE = v2i1, LAST_VECTOR_VALUETYPE = v8f64, - x86mmx = 54, // This is an X86 MMX value + x86mmx = 55, // This is an X86 MMX value - Glue = 55, // This glues nodes together during pre-RA sched + Glue = 56, // This glues nodes together during pre-RA sched - isVoid = 56, // This has no value + isVoid = 57, // This has no value - Untyped = 57, // This value takes a register, but has + Untyped = 58, // This value takes a register, but has // unspecified type. The register class // will be determined by the opcode. FIRST_VALUETYPE = 0, // This is always the beginning of the list. - LAST_VALUETYPE = 58, // This always remains at the end of the list. + LAST_VALUETYPE = 59, // This always remains at the end of the list. // This is the current maximum for LAST_VALUETYPE. // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors @@ -222,10 +223,10 @@ /// is128BitVector - Return true if this is a 128-bit vector type. bool is128BitVector() const { - return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 || - SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 || - SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 || - SimpleTy == MVT::v2f64); + return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 || + SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 || + SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 || + SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64); } /// is256BitVector - Return true if this is a 256-bit vector type. @@ -310,6 +311,7 @@ case v4i64: case v8i64: case v16i64: return i64; + case v1i128: return i128; case v2f16: case v4f16: case v8f16: return f16; @@ -368,6 +370,7 @@ case v1i16: case v1i32: case v1i64: + case v1i128: case v1f32: case v1f64: return 1; } @@ -427,6 +430,7 @@ case v8i16: case v4i32: case v2i64: + case v1i128: case v8f16: case v4f32: case v2f64: return 128; @@ -562,6 +566,9 @@ if (NumElements == 8) return MVT::v8i64; if (NumElements == 16) return MVT::v16i64; break; + case MVT::i128: + if (NumElements == 1) return MVT::v1i128; + break; case MVT::f16: if (NumElements == 2) return MVT::v2f16; if (NumElements == 4) return MVT::v4f16; Index: include/llvm/CodeGen/ValueTypes.td =================================================================== --- include/llvm/CodeGen/ValueTypes.td +++ include/llvm/CodeGen/ValueTypes.td @@ -62,25 +62,26 @@ def v4i64 : ValueType<256, 39>; // 4 x i64 vector value def v8i64 : ValueType<512, 40>; // 8 x i64 vector value def v16i64 : ValueType<1024,41>; // 16 x i64 vector value +def v1i128 : ValueType<128, 42>; // 1 x i128 vector value -def v2f16 : ValueType<32 , 42>; // 2 x f16 vector value -def v4f16 : ValueType<64 , 43>; // 4 x f16 vector value -def v8f16 : ValueType<128, 44>; // 8 x f16 vector value -def v1f32 : ValueType<32 , 45>; // 1 x f32 vector value -def v2f32 : ValueType<64 , 46>; // 2 x f32 vector value -def v4f32 : ValueType<128, 47>; // 4 x f32 vector value -def v8f32 : ValueType<256, 48>; // 8 x f32 vector value -def v16f32 : ValueType<512, 49>; // 16 x f32 vector value -def v1f64 : ValueType<64, 50>; // 1 x f64 vector value -def v2f64 : ValueType<128, 51>; // 2 x f64 vector value -def v4f64 : ValueType<256, 52>; // 4 x f64 vector value -def v8f64 : ValueType<512, 53>; // 8 x f64 vector value - - -def x86mmx : ValueType<64 , 54>; // X86 MMX value -def FlagVT : ValueType<0 , 55>; // Pre-RA sched glue -def isVoid : ValueType<0 , 56>; // Produces no value -def untyped: ValueType<8 , 57>; // Produces an untyped value +def v2f16 : ValueType<32 , 43>; // 2 x f16 vector value +def v4f16 : ValueType<64 , 44>; // 4 x f16 vector value +def v8f16 : ValueType<128, 45>; // 8 x f16 vector value +def v1f32 : ValueType<32 , 46>; // 1 x f32 vector value +def v2f32 : ValueType<64 , 47>; // 2 x f32 vector value +def v4f32 : ValueType<128, 48>; // 4 x f32 vector value +def v8f32 : ValueType<256, 49>; // 8 x f32 vector value +def v16f32 : ValueType<512, 50>; // 16 x f32 vector value +def v1f64 : ValueType<64, 51>; // 1 x f64 vector value +def v2f64 : ValueType<128, 52>; // 2 x f64 vector value +def v4f64 : ValueType<256, 53>; // 4 x f64 vector value +def v8f64 : ValueType<512, 54>; // 8 x f64 vector value + + +def x86mmx : ValueType<64 , 55>; // X86 MMX value +def FlagVT : ValueType<0 , 56>; // Pre-RA sched glue +def isVoid : ValueType<0 , 57>; // Produces no value +def untyped: ValueType<8 , 58>; // Produces an untyped value def MetadataVT: ValueType<0, 250>; // Metadata // Pseudo valuetype mapped to the current pointer size to any address space. Index: include/llvm/IR/IRBuilder.h =================================================================== --- include/llvm/IR/IRBuilder.h +++ include/llvm/IR/IRBuilder.h @@ -320,6 +320,11 @@ return Type::getInt64Ty(Context); } + /// \brief Fetch the type representing a 128-bit integer. + IntegerType *getInt128Ty() { + return Type::getInt128Ty(Context); + } + /// \brief Fetch the type representing an N-bit integer. IntegerType *getIntNTy(unsigned N) { return Type::getIntNTy(Context, N); Index: include/llvm/IR/Type.h =================================================================== --- include/llvm/IR/Type.h +++ include/llvm/IR/Type.h @@ -395,7 +395,8 @@ static IntegerType *getInt16Ty(LLVMContext &C); static IntegerType *getInt32Ty(LLVMContext &C); static IntegerType *getInt64Ty(LLVMContext &C); - + static IntegerType *getInt128Ty(LLVMContext &C); + //===--------------------------------------------------------------------===// // Convenience methods for getting pointer types with one of the above builtin // types as pointee. Index: lib/IR/Core.cpp =================================================================== --- lib/IR/Core.cpp +++ lib/IR/Core.cpp @@ -310,6 +310,9 @@ LLVMTypeRef LLVMInt64TypeInContext(LLVMContextRef C) { return (LLVMTypeRef) Type::getInt64Ty(*unwrap(C)); } +LLVMTypeRef LLVMInt128TypeInContext(LLVMContextRef C) { + return (LLVMTypeRef) Type::getInt128Ty(*unwrap(C)); +} LLVMTypeRef LLVMIntTypeInContext(LLVMContextRef C, unsigned NumBits) { return wrap(IntegerType::get(*unwrap(C), NumBits)); } @@ -329,6 +332,9 @@ LLVMTypeRef LLVMInt64Type(void) { return LLVMInt64TypeInContext(LLVMGetGlobalContext()); } +LLVMTypeRef LLVMInt128Type(void) { + return LLVMInt128TypeInContext(LLVMGetGlobalContext()); +} LLVMTypeRef LLVMIntType(unsigned NumBits) { return LLVMIntTypeInContext(LLVMGetGlobalContext(), NumBits); } Index: lib/IR/LLVMContextImpl.h =================================================================== --- lib/IR/LLVMContextImpl.h +++ lib/IR/LLVMContextImpl.h @@ -919,7 +919,7 @@ // Basic type instances. Type VoidTy, LabelTy, HalfTy, FloatTy, DoubleTy, MetadataTy; Type X86_FP80Ty, FP128Ty, PPC_FP128Ty, X86_MMXTy; - IntegerType Int1Ty, Int8Ty, Int16Ty, Int32Ty, Int64Ty; + IntegerType Int1Ty, Int8Ty, Int16Ty, Int32Ty, Int64Ty, Int128Ty; /// TypeAllocator - All dynamically allocated types are allocated from this. Index: lib/IR/LLVMContextImpl.cpp =================================================================== --- lib/IR/LLVMContextImpl.cpp +++ lib/IR/LLVMContextImpl.cpp @@ -35,7 +35,8 @@ Int8Ty(C, 8), Int16Ty(C, 16), Int32Ty(C, 32), - Int64Ty(C, 64) { + Int64Ty(C, 64), + Int128Ty(C, 128) { InlineAsmDiagHandler = nullptr; InlineAsmDiagContext = nullptr; DiagnosticHandler = nullptr; Index: lib/IR/Type.cpp =================================================================== --- lib/IR/Type.cpp +++ lib/IR/Type.cpp @@ -238,6 +238,7 @@ IntegerType *Type::getInt16Ty(LLVMContext &C) { return &C.pImpl->Int16Ty; } IntegerType *Type::getInt32Ty(LLVMContext &C) { return &C.pImpl->Int32Ty; } IntegerType *Type::getInt64Ty(LLVMContext &C) { return &C.pImpl->Int64Ty; } +IntegerType *Type::getInt128Ty(LLVMContext &C) { return &C.pImpl->Int128Ty; } IntegerType *Type::getIntNTy(LLVMContext &C, unsigned N) { return IntegerType::get(C, N); Index: lib/IR/ValueTypes.cpp =================================================================== --- lib/IR/ValueTypes.cpp +++ lib/IR/ValueTypes.cpp @@ -157,6 +157,7 @@ case MVT::v4i64: return "v4i64"; case MVT::v8i64: return "v8i64"; case MVT::v16i64: return "v16i64"; + case MVT::v1i128: return "v1i128"; case MVT::v1f32: return "v1f32"; case MVT::v2f32: return "v2f32"; case MVT::v2f16: return "v2f16"; @@ -225,6 +226,7 @@ case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); case MVT::v8i64: return VectorType::get(Type::getInt64Ty(Context), 8); case MVT::v16i64: return VectorType::get(Type::getInt64Ty(Context), 16); + case MVT::v1i128: return VectorType::get(Type::getInt128Ty(Context), 1); case MVT::v2f16: return VectorType::get(Type::getHalfTy(Context), 2); case MVT::v4f16: return VectorType::get(Type::getHalfTy(Context), 4); case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8); Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -620,8 +620,11 @@ addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); } - if (Subtarget.hasP8Altivec()) + if (Subtarget.hasP8Altivec()) { addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); + addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); + setOperationAction(ISD::ADD, MVT::v1i128, Legal); + } } if (Subtarget.hasQPX()) { @@ -3150,6 +3153,7 @@ case MVT::v16i8: case MVT::v2f64: case MVT::v2i64: + case MVT::v1i128: if (!Subtarget.hasQPX()) { // These can be scalar arguments or elements of a vector array type // passed directly. The latter are used to implement ELFv2 homogenous Index: lib/Target/PowerPC/PPCInstrAltivec.td =================================================================== --- lib/Target/PowerPC/PPCInstrAltivec.td +++ lib/Target/PowerPC/PPCInstrAltivec.td @@ -802,26 +802,37 @@ def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; def : Pat<(v16i8 (bitconvert (v2i64 VRRC:$src))), (v16i8 VRRC:$src)>; +def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>; def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; def : Pat<(v8i16 (bitconvert (v2i64 VRRC:$src))), (v8i16 VRRC:$src)>; +def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>; def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; def : Pat<(v4i32 (bitconvert (v2i64 VRRC:$src))), (v4i32 VRRC:$src)>; +def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>; def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; def : Pat<(v4f32 (bitconvert (v2i64 VRRC:$src))), (v4f32 VRRC:$src)>; +def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>; def : Pat<(v2i64 (bitconvert (v16i8 VRRC:$src))), (v2i64 VRRC:$src)>; def : Pat<(v2i64 (bitconvert (v8i16 VRRC:$src))), (v2i64 VRRC:$src)>; def : Pat<(v2i64 (bitconvert (v4i32 VRRC:$src))), (v2i64 VRRC:$src)>; def : Pat<(v2i64 (bitconvert (v4f32 VRRC:$src))), (v2i64 VRRC:$src)>; +def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>; + +def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>; +def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>; +def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>; +def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>; +def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>; // Shuffles. @@ -987,11 +998,17 @@ def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vaddudm $vD, $vA, $vB", IIC_VecGeneral, [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; +def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vadduqm $vD, $vA, $vB", IIC_VecGeneral, + [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; } // isCommutable def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), "vsubudm $vD, $vA, $vB", IIC_VecGeneral, [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; +def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), + "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, + [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; // Count Leading Zeros def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), Index: lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- lib/Target/PowerPC/PPCInstrVSX.td +++ lib/Target/PowerPC/PPCInstrVSX.td @@ -872,6 +872,11 @@ def : Pat<(v2i64 (bitconvert v2f64:$A)), (COPY_TO_REGCLASS $A, VRRC)>; +def : Pat<(v2f64 (bitconvert v1i128:$A)), + (COPY_TO_REGCLASS $A, VRRC)>; +def : Pat<(v1i128 (bitconvert v2f64:$A)), + (COPY_TO_REGCLASS $A, VRRC)>; + // sign extension patterns // To extend "in place" from v2i32 to v2i64, we have input data like: // | undef | i32 | undef | i32 | Index: lib/Target/PowerPC/PPCRegisterInfo.td =================================================================== --- lib/Target/PowerPC/PPCRegisterInfo.td +++ lib/Target/PowerPC/PPCRegisterInfo.td @@ -288,7 +288,7 @@ (sequence "F%u", 31, 14))>; def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; -def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v4f32], 128, +def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128, (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; Index: test/CodeGen/PowerPC/vec_add_sub_quadword.ll =================================================================== --- test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -0,0 +1,48 @@ +; Check VMX 64-bit integer operations +; +; KRUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; KRUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s + +define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind { + %result = add <1 x i128> %x, %y + ret <1 x i128> %result +; CHECK: vadduqm 2, 2, 3 +} + +define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { + %result = add <1 x i128> %x, + ret <1 x i128> %result +; CHECK vadduqm 2, 2, 3* +} + +define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { + %tmpvec = insertelement <1 x i128> , i128 %val, i32 0 + %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1 + %result = add <1 x i128> %x, %tmpvec2 + ret <1 x i128> %result +; CHECK: vadduqm 2, 2, 3 +} + +define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind { + %result = sub <1 x i128> %x, %y + ret <1 x i128> %result +; CHECK: vsubuqm 2, 2, 3 +} + +define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { + %result = sub <1 x i128> %x, + ret <1 x i128> %result +; CHECK vsubuqm 2, 2, 3 +} + +define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { + %tmpvec = insertelement <1 x i128> , i128 %val, i32 0 + %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1 + %result = sub <1 x i128> %x, %tmpvec2 + ret <1 x i128> %result +; CHECK vsubuqm 2, 2, 3 +} + + + + Index: test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt =================================================================== --- test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt +++ test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt @@ -207,6 +207,9 @@ # CHECK: vadduws 2, 3, 4 0x10 0x43 0x22 0x80 +# CHECK: vadduqm 2, 3, 4 +0x10 0x43 0x21 0x00 + # CHECK: vsubcuw 2, 3, 4 0x10 0x43 0x25 0x80 @@ -240,6 +243,9 @@ # CHECK: vsubuws 2, 3, 4 0x10 0x43 0x26 0x80 +# CHECK: vsubuqm 2, 3, 4 +0x10 0x43 0x25 0x00 + # CHECK: vmulesb 2, 3, 4 0x10 0x43 0x23 0x08 Index: test/MC/PowerPC/ppc64-encoding-vmx.s =================================================================== --- test/MC/PowerPC/ppc64-encoding-vmx.s +++ test/MC/PowerPC/ppc64-encoding-vmx.s @@ -237,7 +237,10 @@ # CHECK-BE: vadduws 2, 3, 4 # encoding: [0x10,0x43,0x22,0x80] # CHECK-LE: vadduws 2, 3, 4 # encoding: [0x80,0x22,0x43,0x10] vadduws 2, 3, 4 - +# CHECK-BE: vadduqm 2, 3, 4 # encoding: [0x10,0x43,0x21,0x00] +# CHECK-LE: vadduqm 2, 3, 4 # encoding: [0x00,0x21,0x43,0x10] + vadduqm 2, 3, 4 + # CHECK-BE: vsubcuw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x80] # CHECK-LE: vsubcuw 2, 3, 4 # encoding: [0x80,0x25,0x43,0x10] vsubcuw 2, 3, 4 @@ -271,7 +274,10 @@ # CHECK-BE: vsubuws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x80] # CHECK-LE: vsubuws 2, 3, 4 # encoding: [0x80,0x26,0x43,0x10] vsubuws 2, 3, 4 - +# CHECK-BE: vsubuqm 2, 3, 4 # encoding: [0x10,0x43,0x25,0x00] +# CHECK-LE: vsubuqm 2, 3, 4 # encoding: [0x00,0x25,0x43,0x10] + vsubuqm 2, 3, 4 + # CHECK-BE: vmulesb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x08] # CHECK-LE: vmulesb 2, 3, 4 # encoding: [0x08,0x23,0x43,0x10] vmulesb 2, 3, 4 Index: test/TableGen/intrinsic-varargs.td =================================================================== --- test/TableGen/intrinsic-varargs.td +++ test/TableGen/intrinsic-varargs.td @@ -23,7 +23,7 @@ } // isVoid needs to match the definition in ValueTypes.td -def isVoid : ValueType<0, 56>; // Produces no value +def isVoid : ValueType<0, 57>; // Produces no value def llvm_vararg_ty : LLVMType; // this means vararg here // CHECK: /* 0 */ 0, 28, 0, Index: utils/TableGen/CodeGenTarget.cpp =================================================================== --- utils/TableGen/CodeGenTarget.cpp +++ utils/TableGen/CodeGenTarget.cpp @@ -99,6 +99,7 @@ case MVT::v4i64: return "MVT::v4i64"; case MVT::v8i64: return "MVT::v8i64"; case MVT::v16i64: return "MVT::v16i64"; + case MVT::v1i128: return "MVT::v1i128"; case MVT::v2f16: return "MVT::v2f16"; case MVT::v4f16: return "MVT::v4f16"; case MVT::v8f16: return "MVT::v8f16";