Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -169,6 +169,13 @@
 def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
                               AssemblerPredicate<(all_of FeatureExtZvamo),
                               "'Zvamo'(Vector AMO Operations)">;
+def FeatureExtZvqmac
+    : SubtargetFeature<"experimental-zvqmac", "HasStdExtZvqmac", "true",
+                       "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)",
+                       [FeatureStdExtV]>;
+def HasStdExtZvqmac : Predicate<"Subtarget->hasStdExtZvqmac()">,
+                                AssemblerPredicate<(all_of FeatureExtZvqmac),
+                                "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1099,3 +1099,11 @@
   defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">;
   defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">;
 } // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64]
+
+// Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqmac)
+let Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VQMACCU_V : VALUr_IV_V_X<"vqmaccu", 0b111100>;
+defm VQMACC_V : VALUr_IV_V_X<"vqmacc", 0b111101>;
+defm VQMACCSU_V : VALUr_IV_V_X<"vqmaccsu", 0b111111>;
+defm VQMACCUS_V : VALUr_IV_X<"vqmaccus", 0b111110>;
+} // Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
\ No newline at end of file
Index: llvm/lib/Target/RISCV/RISCVSchedRocket32.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedRocket32.td
+++ llvm/lib/Target/RISCV/RISCVSchedRocket32.td
@@ -17,7 +17,7 @@
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 1;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo, HasStdExtZvqmac];
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/RISCVSchedRocket64.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedRocket64.td
+++ llvm/lib/Target/RISCV/RISCVSchedRocket64.td
@@ -16,7 +16,7 @@
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo, HasStdExtZvqmac];
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -53,6 +53,7 @@
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
+  bool HasStdExtZvqmac = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -116,6 +117,7 @@
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
+  bool hasStdExtZvqmac() const { return HasStdExtZvqmac; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/test/MC/RISCV/rvv/zvqmac.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvqmac.s
@@ -0,0 +1,93 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvqmac %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-zvqmac - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vqmaccu.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmaccu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf0]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f0 <unknown>
+
+vqmaccu.vv v8, v20, v4
+# CHECK-INST: vqmaccu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf2]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f2 <unknown>
+
+vqmaccu.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf0]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f0 <unknown>
+
+vqmaccu.vx v8, a0, v4
+# CHECK-INST: vqmaccu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf2]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f2 <unknown>
+
+vqmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf4]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f4 <unknown>
+
+vqmacc.vv v8, v20, v4
+# CHECK-INST: vqmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xf6]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a f6 <unknown>
+
+vqmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf4]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f4 <unknown>
+
+vqmacc.vx v8, a0, v4
+# CHECK-INST: vqmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf6]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f6 <unknown>
+
+vqmaccsu.vv v8, v20, v4, v0.t
+# CHECK-INST: vqmaccsu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xfc]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a fc <unknown>
+
+vqmaccsu.vv v8, v20, v4
+# CHECK-INST: vqmaccsu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xfe]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 04 4a fe <unknown>
+
+vqmaccsu.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccsu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfc]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fc <unknown>
+
+vqmaccsu.vx v8, a0, v4
+# CHECK-INST: vqmaccsu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfe]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fe <unknown>
+
+vqmaccus.vx v8, a0, v4, v0.t
+# CHECK-INST: vqmaccus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xf8]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 f8 <unknown>
+
+vqmaccus.vx v8, a0, v4
+# CHECK-INST: vqmaccus.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x44,0x45,0xfa]
+# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
+# CHECK-UNKNOWN: 57 44 45 fa <unknown>