Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -211,6 +211,9 @@ bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + void createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -1624,6 +1627,14 @@ case Mips::JalTwoReg: case Mips::BneImm: case Mips::BeqImm: + case Mips::BLT: + case Mips::BLE: + case Mips::BGE: + case Mips::BGT: + case Mips::BLTU: + case Mips::BLEU: + case Mips::BGEU: + case Mips::BGTU: return true; default: return false; @@ -1653,6 +1664,15 @@ case Mips::BneImm: case Mips::BeqImm: return expandBranchImm(Inst, IDLoc, Instructions); + case Mips::BLT: + case Mips::BLE: + case Mips::BGE: + case Mips::BGT: + case Mips::BLTU: + case Mips::BLEU: + case Mips::BGEU: + case Mips::BGTU: + return expandCondBranches(Inst, IDLoc, Instructions); } } @@ -2235,6 +2255,206 @@ return false; } +bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + unsigned PseudoOpcode = Inst.getOpcode(); + unsigned SrcReg = Inst.getOperand(0).getReg(); + unsigned TrgReg = Inst.getOperand(1).getReg(); + const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr(); + + unsigned ZeroSrcOpcode, ZeroTrgOpcode; + bool ReverseOrderSLT, IsUnsigned, AcceptsEquality; + + switch (PseudoOpcode) { + case Mips::BLT: + case Mips::BLTU: + AcceptsEquality = false; + ReverseOrderSLT = false; + IsUnsigned = (PseudoOpcode == Mips::BLTU); + ZeroSrcOpcode = Mips::BGTZ; + ZeroTrgOpcode = Mips::BLTZ; + break; + case Mips::BLE: + case Mips::BLEU: + AcceptsEquality = true; + ReverseOrderSLT = true; + IsUnsigned = (PseudoOpcode == Mips::BLEU); + ZeroSrcOpcode = Mips::BGEZ; + ZeroTrgOpcode = Mips::BLEZ; + break; + case Mips::BGE: + case Mips::BGEU: + AcceptsEquality = true; + ReverseOrderSLT = false; + IsUnsigned = (PseudoOpcode == Mips::BGEU); + ZeroSrcOpcode = Mips::BLEZ; + ZeroTrgOpcode = Mips::BGEZ; + break; + case Mips::BGT: + case Mips::BGTU: + AcceptsEquality = false; + ReverseOrderSLT = true; + IsUnsigned = (PseudoOpcode == Mips::BGTU); + ZeroSrcOpcode = Mips::BLTZ; + ZeroTrgOpcode = Mips::BGTZ; + break; + default: + llvm_unreachable("unknown opcode for branch pseudo-instruction"); + } + + MCInst BranchInst; + bool IsTrgRegZero = (TrgReg == Mips::ZERO); + bool IsSrcRegZero = (SrcReg == Mips::ZERO); + if (IsSrcRegZero && IsTrgRegZero) { + // FIXME: All of these Opcode-specific if's are needed for compatibility + // with GAS' behaviour. However, they may not generate the most efficient + // code in some circumstances. + if (PseudoOpcode == Mips::BLT) { + BranchInst.setOpcode(Mips::BLTZ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; + } + if (PseudoOpcode == Mips::BLE) { + BranchInst.setOpcode(Mips::BLEZ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + Warning(IDLoc, "branch is always taken"); + return false; + } + if (PseudoOpcode == Mips::BGE) { + BranchInst.setOpcode(Mips::BGEZ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + Warning(IDLoc, "branch is always taken"); + return false; + } + if (PseudoOpcode == Mips::BGT) { + BranchInst.setOpcode(Mips::BGTZ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; + } + if (PseudoOpcode == Mips::BGTU) { + BranchInst.setOpcode(Mips::BNE); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; + } + if (AcceptsEquality) { + // If both registers are $0 and the pseudo-branch accepts equality, it + // will always be taken, so we emit an unconditional branch. + BranchInst.setOpcode(Mips::BEQ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + Warning(IDLoc, "branch is always taken"); + return false; + } + // If both registers are $0 and the pseudo-branch does not accept + // equality, it will never be taken, so we don't have to emit anything. + return false; + } + if (IsSrcRegZero || IsTrgRegZero) { + if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) || + (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) { + // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or + // if the $rt is $0 and the pseudo-branch is BLTU (x < 0), + // the pseudo-branch will never be taken, so we don't emit anything. + // This only applies to unsigned pseudo-branches. + return false; + } + if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) || + (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) { + // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or + // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0), + // the pseudo-branch will always be taken, so we emit an unconditional + // branch. + // This only applies to unsigned pseudo-branches. + BranchInst.setOpcode(Mips::BEQ); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + Warning(IDLoc, "branch is always taken"); + return false; + } + if (IsUnsigned) { + // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or + // if the $rt is $0 and the pseudo-branch is BGTU (x > 0), + // the pseudo-branch will be taken only when the non-zero register is + // different from 0, so we emit a BNEZ. + // + // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or + // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0), + // the pseudo-branch will be taken only when the non-zero register is + // equal to 0, so we emit a BEQZ. + // + // Because only BLEU and BGEU branch on equality, we can use the + // AcceptsEquality variable to decide when to emit the BEQZ. + BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE); + BranchInst.addOperand( + MCOperand::createReg(IsSrcRegZero ? TrgReg : SrcReg)); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; + } + // If we have a signed pseudo-branch and one of the registers is $0, + // we can use an appropriate compare-to-zero branch. We select which one + // to use in the switch statement above. + BranchInst.setOpcode(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode); + BranchInst.addOperand(MCOperand::createReg(IsSrcRegZero ? TrgReg : SrcReg)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; + } + + // If neither the SrcReg nor the TrgReg are $0, we need AT to perform the + // expansions. If it is not available, we return. + unsigned ATRegNum = getATReg(IDLoc); + if (!ATRegNum) + return true; + + warnIfNoMacro(IDLoc); + + // SLT fits well with 2 of our 4 pseudo-branches: + // BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and + // BGT, where $rs > $rt, translates into "slt $at, $rt, $rs". + // If the result of the SLT is 1, we branch, and if it's 0, we don't. + // This is accomplished by using a BNEZ with the result of the SLT. + // + // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT + // and BLE with BGT), so we change the BNEZ into a a BEQZ. + // Because only BGE and BLE branch on equality, we can use the + // AcceptsEquality variable to decide when to emit the BEQZ. + // Note that the order of the SLT arguments doesn't change between + // opposites. + // + // The same applies to the unsigned variants, except that SLTu is used + // instead of SLT. + MCInst SetInst; + SetInst.setOpcode(IsUnsigned ? Mips::SLTu : Mips::SLT); + SetInst.addOperand(MCOperand::createReg(ATRegNum)); + SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? TrgReg : SrcReg)); + SetInst.addOperand(MCOperand::createReg(ReverseOrderSLT ? SrcReg : TrgReg)); + Instructions.push_back(SetInst); + + BranchInst.setOpcode(AcceptsEquality ? Mips::BEQ : Mips::BNE); + BranchInst.addOperand(MCOperand::createReg(ATRegNum)); + BranchInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BranchInst.addOperand(MCOperand::createExpr(OffsetExpr)); + Instructions.push_back(BranchInst); + return false; +} + void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, SmallVectorImpl &Instructions) { MCInst NopInst; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1691,8 +1691,22 @@ def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins imm64:$imm64, brtarget:$offset), "beq\t$rt, $imm64, $offset">; + +class CondBranchPseudo : + MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, + brtarget:$offset), + !strconcat(instr_asm, "\t$rs, $rt, $offset")>; } +def BLT : CondBranchPseudo<"blt">; +def BLE : CondBranchPseudo<"ble">; +def BGE : CondBranchPseudo<"bge">; +def BGT : CondBranchPseudo<"bgt">; +def BLTU : CondBranchPseudo<"bltu">; +def BLEU : CondBranchPseudo<"bleu">; +def BGEU : CondBranchPseudo<"bgeu">; +def BGTU : CondBranchPseudo<"bgtu">; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// Index: test/MC/Mips/branch-pseudos-bad.s =================================================================== --- /dev/null +++ test/MC/Mips/branch-pseudos-bad.s @@ -0,0 +1,21 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s + +# Check for errors when using conditional branch pseudos after .set noat. + .set noat +local_label: + blt $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bltu $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + ble $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bleu $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bge $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgeu $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgt $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available + bgtu $7, $8, local_label +# CHECK: :[[@LINE-1]]:3: error: pseudo-instruction requires $at, which is not available Index: test/MC/Mips/branch-pseudos.s =================================================================== --- /dev/null +++ test/MC/Mips/branch-pseudos.s @@ -0,0 +1,189 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding | FileCheck %s +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | \ +# RUN: FileCheck %s --check-prefix=WARNING + + .text +local_label: + blt $7, $8, local_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + blt $7, $8, global_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + blt $7, $0, local_label +# CHECK: bltz $7, local_label # encoding: [0x04,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + blt $0, $8, local_label +# CHECK: bgtz $8, local_label # encoding: [0x1d,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + blt $0, $0, local_label +# CHECK: bltz $zero, local_label # encoding: [0x04,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bltu $7, $8, local_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bltu $7, $8, global_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bltu $7, $0, local_label +# CHECK: nop + bltu $0, $8, local_label +# CHECK: bnez $8, local_label # encoding: [0x15,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bltu $0, $0, local_label +# CHECK: nop + + ble $7, $8, local_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + ble $7, $8, global_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + ble $7, $0, local_label +# CHECK: blez $7, local_label # encoding: [0x18,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + ble $0, $8, local_label +# CHECK: bgez $8, local_label # encoding: [0x05,0x01,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + ble $0, $0, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: blez $zero, local_label # encoding: [0x18,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bleu $7, $8, local_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bleu $7, $8, global_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bleu $7, $0, local_label +# CHECK: beqz $7, local_label # encoding: [0x10,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bleu $0, $8, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bleu $0, $0, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bge $7, $8, local_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bge $7, $8, global_label +# CHECK: slt $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2a] +# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bge $7, $0, local_label +# CHECK: bgez $7, local_label # encoding: [0x04,0xe1,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bge $0, $8, local_label +# CHECK: blez $8, local_label # encoding: [0x19,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bge $0, $0, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: bgez $zero, local_label # encoding: [0x04,0x01,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bgeu $7, $8, local_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: beqz $1, local_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgeu $7, $8, global_label +# CHECK: sltu $1, $7, $8 # encoding: [0x00,0xe8,0x08,0x2b] +# CHECK: beqz $1, global_label # encoding: [0x10,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgeu $7, $0, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgeu $0, $8, local_label +# CHECK: beqz $8, local_label # encoding: [0x11,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgeu $0, $0, local_label +# WARNING: :[[@LINE-1]]:3: warning: branch is always taken +# CHECK: b local_label # encoding: [0x10,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bgt $7, $8, local_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgt $7, $8, global_label +# CHECK: slt $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2a] +# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgt $7, $0, local_label +# CHECK: bgtz $7, local_label # encoding: [0x1c,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgt $0, $8, local_label +# CHECK: bltz $8, local_label # encoding: [0x05,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgt $0, $0, local_label +# CHECK: bgtz $zero, local_label # encoding: [0x1c,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + + bgtu $7, $8, local_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: bnez $1, local_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgtu $7, $8, global_label +# CHECK: sltu $1, $8, $7 # encoding: [0x01,0x07,0x08,0x2b] +# CHECK: bnez $1, global_label # encoding: [0x14,0x20,A,A] +# CHECK: # fixup A - offset: 0, value: global_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgtu $7, $0, local_label +# CHECK: bnez $7, local_label # encoding: [0x14,0xe0,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop + bgtu $0, $8, local_label +# CHECK: nop + bgtu $0, $0, local_label +# CHECK: bnez $zero, local_label # encoding: [0x14,0x00,A,A] +# CHECK: # fixup A - offset: 0, value: local_label, kind: fixup_Mips_PC16 +# CHECK: nop Index: test/MC/Mips/set-nomacro.s =================================================================== --- test/MC/Mips/set-nomacro.s +++ test/MC/Mips/set-nomacro.s @@ -20,6 +20,46 @@ beq $2, 0, 1332 beq $2, 1, 1332 + blt $7, $8, local_label + blt $7, $0, local_label + blt $0, $8, local_label + blt $0, $0, local_label + + bltu $7, $8, local_label + bltu $7, $0, local_label + bltu $0, $8, local_label + bltu $0, $0, local_label + + ble $7, $8, local_label + ble $7, $0, local_label + ble $0, $8, local_label + ble $0, $0, local_label + + bleu $7, $8, local_label + bleu $7, $0, local_label + bleu $0, $8, local_label + bleu $0, $0, local_label + + bge $7, $8, local_label + bge $7, $0, local_label + bge $0, $8, local_label + bge $0, $0, local_label + + bgeu $7, $8, local_label + bgeu $7, $0, local_label + bgeu $0, $8, local_label + bgeu $0, $0, local_label + + bgt $7, $8, local_label + bgt $7, $0, local_label + bgt $0, $8, local_label + bgt $0, $0, local_label + + bgtu $7, $8, local_label + bgtu $7, $0, local_label + bgtu $0, $8, local_label + bgtu $0, $0, local_label + add $4, $5, $6 .set noreorder @@ -56,5 +96,77 @@ beq $2, 1, 1332 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + blt $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + blt $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + blt $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + blt $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bltu $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bltu $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bltu $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bltu $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + ble $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ble $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ble $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + ble $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bleu $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bleu $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bleu $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bleu $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bge $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bge $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bge $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bge $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bgeu $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgeu $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgeu $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgeu $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bgt $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgt $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgt $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgt $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + + bgtu $7, $8, local_label +# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgtu $7, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgtu $0, $8, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + bgtu $0, $0, local_label +# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions + add $4, $5, $6 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions