diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -38,6 +38,10 @@ STATISTIC(NumFrameOffFoldInPreEmit, "Number of folding frame offset by using r+r in pre-emit peephole"); +static cl::opt +EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), + cl::desc("enable PC Relative linker optimization")); + static cl::opt RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), cl::desc("Run pre-emit peephole optimizations.")); @@ -234,6 +238,10 @@ bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) { MachineFunction *MF = MBB.getParent(); + // If the linker opt is disabled then just return. + if (!EnablePCRelLinkerOpt) + return false; + // Add this linker opt only if we are using PC Relative memops. if (!MF->getSubtarget().isUsingPCRelativeCalls()) return false; diff --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll @@ -0,0 +1,39 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: < %s | FileCheck %s --check-prefix=DEFAULT +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -ppc-pcrel-linker-opt=true < %s | FileCheck %s --check-prefix=ON +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -ppc-pcrel-linker-opt=false < %s | FileCheck %s --check-prefix=OFF + +@input8 = external local_unnamed_addr global i8, align 1 + +define dso_local i8 @Read8() local_unnamed_addr { +; DEFAULT-LABEL: Read8: +; DEFAULT: # %bb.0: # %entry +; DEFAULT-NEXT: pld r3, input8@got@pcrel(0), 1 +; DEFAULT-NEXT: .Lpcrel: +; DEFAULT-NEXT: .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8) +; DEFAULT-NEXT: lbz r3, 0(r3) +; DEFAULT-NEXT: blr +; +; ON-LABEL: Read8: +; ON: # %bb.0: # %entry +; ON-NEXT: pld r3, input8@got@pcrel(0), 1 +; ON-NEXT: .Lpcrel: +; ON-NEXT: .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8) +; ON-NEXT: lbz r3, 0(r3) +; ON-NEXT: blr +; +; OFF-LABEL: Read8: +; OFF: # %bb.0: # %entry +; OFF-NEXT: pld r3, input8@got@pcrel(0), 1 +; OFF-NEXT: lbz r3, 0(r3) +; OFF-NEXT: blr +entry: + %0 = load i8, i8* @input8, align 1 + ret i8 %0 +}