diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3160,11 +3160,11 @@
   Register InUseReg = MI.getOperand(OpNo).getReg();
   MI.getOperand(OpNo).ChangeToImmediate(Imm);
 
-  if (MI.implicit_operands().empty())
-    return;
-
   // We need to make sure that the MI didn't have any implicit use
-  // of this REG any more.
+  // of this REG any more. We don't call MI.implicit_operands().empty() to
+  // return early, since MI's MCID might be changed in calling context, as a
+  // result its number of explicit operands may be changed, thus the begin of
+  // implicit operand is changed.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
   if (UseOpIdx >= 0) {
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=powerpc64-unknown-unknown -stop-after ppc-pre-emit-peephole \
+# RUN:   %s -o - -verify-machineinstrs | FileCheck %s
+
+---
+name: testRedundantLiImplicitReg
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x4, $x5
+
+    STW killed $r3, killed $x5, 100
+    renamable $x5 = LI8 2
+    renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5
+    STD $x4, $x4, 100
+    BLR8 implicit $lr8, implicit $rm
+
+  ; CHECK-LABEL: testRedundantLiImplicitReg
+  ; CHECK: bb.0.entry:
+  ; CHECK:   STW killed $r3, killed $x5, 100
+  ; CHECK:   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
+  ; CHECK:   STD killed $x4, $x4, 100
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm