diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -4210,6 +4210,20 @@
     }
   }
 
+  // Remove the implicit registers defined by DefMI.
+  const TargetRegisterInfo *TRI = &getRegisterInfo();
+  int idx = MI.findRegisterUseOperandIdx(DefMI.getOperand(0).getReg(),
+                                         false, TRI);
+  if (idx != -1 && MI.getOperand(idx).isImplicit()) {
+    // Below is an example:
+    // renamable $x5 = LI8 2
+    // renamable $x4 = exact RLDICL killed renamable $x4, 62, 2, implicit $x5
+    // ==> Remove the implicit $x5
+    // dead renamable $x5 = LI8 2
+    // renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
+    MI.RemoveOperand(idx);
+  }
+
   // Fix up killed/dead flag after transformation.
   // Pattern:
   // ForwardKilledOperandReg = LI imm
diff --git a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mtriple=powerpc64le--linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s
+
+
+---
+name: testRedundantLiImplicitReg
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x4, $x5
+
+    STW killed $r3, killed $x5, 100
+    renamable $x5 = LI8 2
+    renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5
+    STD $x4, $x4, 100
+    BLR8 implicit $lr8, implicit $rm
+
+  ; CHECK-LABEL: testRedundantLiImplicitReg
+  ; CHECK: bb.0.entry:
+  ; CHECK:   STW killed $r3, killed $x5, 100
+  ; CHECK:   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
+  ; CHECK:   STD killed $x4, $x4, 100
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm
+...