diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1845,13 +1845,8 @@ return selectBinaryOp(I, ISD::FADD); case Instruction::Sub: return selectBinaryOp(I, ISD::SUB); - case Instruction::FSub: { - // FNeg is currently represented in LLVM IR as a special case of FSub. - Value *X; - if (match(I, m_FNeg(m_Value(X)))) - return selectFNeg(I, X); + case Instruction::FSub: return selectBinaryOp(I, ISD::FSUB); - } case Instruction::Mul: return selectBinaryOp(I, ISD::MUL); case Instruction::FMul: diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll b/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll deleted file mode 100644 --- a/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll +++ /dev/null @@ -1,22 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s - -; Make sure we output the right kill flag for the xor conversion. - -define void @goo(double* %x, double* %y) nounwind { -; CHECK: %[[REG2:.*]]:gr64 = COPY $rsi -; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi -; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]] -; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]] -; CHECK-NEXT: %[[REG10:.*]]:fr64 = MOVSDrm_alt %[[REG1]], 1, $noreg, 0, $noreg :: (load 8 from %ir.x) -; CHECK-NEXT: %[[REG6:.*]]:gr64 = MOVSDto64rr killed %[[REG10]] -; CHECK-NEXT: %[[REG7:.*]]:gr64 = MOV64ri -9223372036854775808 -; CHECK-NEXT: %[[REG8:.*]]:gr64 = XOR64rr killed %[[REG6]], killed %[[REG7]], implicit-def $eflags -; CHECK-NEXT: %[[REG9:.*]]:fr64 = MOV64toSDrr killed %[[REG8]] -; CHECK-NEXT: MOVSDmr %[[REG3]], 1, $noreg, 0, $noreg, killed %[[REG9]] :: (store 8 into %ir.y) -; CHECK-NEXT: RETQ - %a = load double, double* %x - %b = fsub double -0.0, %a - store double %b, double* %y - ret void -} diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg.ll b/llvm/test/CodeGen/X86/fast-isel-fneg.ll --- a/llvm/test/CodeGen/X86/fast-isel-fneg.ll +++ b/llvm/test/CodeGen/X86/fast-isel-fneg.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -mtriple=i686-- -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s -define double @doo(double %x) nounwind { -; CHECK-LABEL: doo: +define double @fneg_f64(double %x) nounwind { +; CHECK-LABEL: fneg_f64: ; CHECK: ## %bb.0: ; CHECK-NEXT: movq %xmm0, %rax ; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000 @@ -11,7 +11,7 @@ ; CHECK-NEXT: movq %rcx, %xmm0 ; CHECK-NEXT: retq ; -; SSE2-LABEL: doo: +; SSE2-LABEL: fneg_f64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushl %ebp ; SSE2-NEXT: movl %esp, %ebp @@ -24,19 +24,19 @@ ; SSE2-NEXT: movl %ebp, %esp ; SSE2-NEXT: popl %ebp ; SSE2-NEXT: retl - %y = fsub double -0.0, %x + %y = fneg double %x ret double %y } -define float @foo(float %x) nounwind { -; CHECK-LABEL: foo: +define float @fneg_f32(float %x) nounwind { +; CHECK-LABEL: fneg_f32: ; CHECK: ## %bb.0: ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000 ; CHECK-NEXT: movd %eax, %xmm0 ; CHECK-NEXT: retq ; -; SSE2-LABEL: foo: +; SSE2-LABEL: fneg_f32: ; SSE2: # %bb.0: ; SSE2-NEXT: pushl %eax ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero @@ -45,12 +45,12 @@ ; SSE2-NEXT: flds (%esp) ; SSE2-NEXT: popl %eax ; SSE2-NEXT: retl - %y = fsub float -0.0, %x + %y = fneg float %x ret float %y } -define void @goo(double* %x, double* %y) nounwind { -; CHECK-LABEL: goo: +define void @fneg_f64_mem(double* %x, double* %y) nounwind { +; CHECK-LABEL: fneg_f64_mem: ; CHECK: ## %bb.0: ; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movq %xmm0, %rax @@ -60,7 +60,7 @@ ; CHECK-NEXT: movq %xmm0, (%rsi) ; CHECK-NEXT: retq ; -; SSE2-LABEL: goo: +; SSE2-LABEL: fneg_f64_mem: ; SSE2: # %bb.0: ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx @@ -69,13 +69,13 @@ ; SSE2-NEXT: movsd %xmm0, (%eax) ; SSE2-NEXT: retl %a = load double, double* %x - %b = fsub double -0.0, %a + %b = fneg double %a store double %b, double* %y ret void } -define void @loo(float* %x, float* %y) nounwind { -; CHECK-LABEL: loo: +define void @fneg_f32_mem(float* %x, float* %y) nounwind { +; CHECK-LABEL: fneg_f32_mem: ; CHECK: ## %bb.0: ; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movd %xmm0, %eax @@ -84,7 +84,7 @@ ; CHECK-NEXT: movd %xmm0, (%rsi) ; CHECK-NEXT: retq ; -; SSE2-LABEL: loo: +; SSE2-LABEL: fneg_f32_mem: ; SSE2: # %bb.0: ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx @@ -95,54 +95,7 @@ ; SSE2-NEXT: movd %xmm0, (%eax) ; SSE2-NEXT: retl %a = load float, float* %x - %b = fsub float -0.0, %a + %b = fneg float %a store float %b, float* %y ret void } - -define double @too(double %x) nounwind { -; CHECK-LABEL: too: -; CHECK: ## %bb.0: -; CHECK-NEXT: movq %xmm0, %rax -; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000 -; CHECK-NEXT: xorq %rax, %rcx -; CHECK-NEXT: movq %rcx, %xmm0 -; CHECK-NEXT: retq -; -; SSE2-LABEL: too: -; SSE2: # %bb.0: -; SSE2-NEXT: pushl %ebp -; SSE2-NEXT: movl %esp, %ebp -; SSE2-NEXT: andl $-8, %esp -; SSE2-NEXT: subl $8, %esp -; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero -; SSE2-NEXT: xorps {{\.LCPI.*}}, %xmm0 -; SSE2-NEXT: movlps %xmm0, (%esp) -; SSE2-NEXT: fldl (%esp) -; SSE2-NEXT: movl %ebp, %esp -; SSE2-NEXT: popl %ebp -; SSE2-NEXT: retl - %y = fneg double %x - ret double %y -} - -define float @zoo(float %x) nounwind { -; CHECK-LABEL: zoo: -; CHECK: ## %bb.0: -; CHECK-NEXT: movd %xmm0, %eax -; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000 -; CHECK-NEXT: movd %eax, %xmm0 -; CHECK-NEXT: retq -; -; SSE2-LABEL: zoo: -; SSE2: # %bb.0: -; SSE2-NEXT: pushl %eax -; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; SSE2-NEXT: xorps {{\.LCPI.*}}, %xmm0 -; SSE2-NEXT: movss %xmm0, (%esp) -; SSE2-NEXT: flds (%esp) -; SSE2-NEXT: popl %eax -; SSE2-NEXT: retl - %y = fneg float %x - ret float %y -}