Index: lib/Target/Mips/MicroMipsR6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMipsR6InstrFormats.td
+++ lib/Target/Mips/MicroMipsR6InstrFormats.td
@@ -39,3 +39,18 @@
   let Inst{20-16} = funct;
   let Inst{15-0}  = imm;
 }
+
+class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b000000;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10}    = 0;
+  let Inst{9-0}   = funct;
+}
Index: lib/Target/Mips/MicroMipsR6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsR6InstrInfo.td
+++ lib/Target/Mips/MicroMipsR6InstrInfo.td
@@ -25,6 +25,8 @@
 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101001>;
 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
+class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
+class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 
 //===----------------------------------------------------------------------===//
 //
@@ -90,6 +92,17 @@
   list<Register> Defs = [AT];
 }
 
+class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : MMR6Arch<instr_asm> {
+  dag OutOperandList = (outs GPROpnd:$rd);
+  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
+  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
+  list<dag> Pattern = [];
+}
+
+class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
+class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
@@ -105,4 +118,6 @@
 def JIALC_MMR6 : MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPSR6;
 def JIC_MMR6 : MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPSR6;
 def LWPC_MMR6 : MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPSR6;
+def SELEQZ_MMR6 : MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC, ISA_MICROMIPSR6;
+def SELNEZ_MMR6 : MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC, ISA_MICROMIPSR6;
 }
Index: lib/Target/Mips/Mips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrInfo.td
+++ lib/Target/Mips/Mips32r6InstrInfo.td
@@ -481,7 +481,8 @@
 }
 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
 
-class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
+class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+    : Mips32r6Arch<instr_asm> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
@@ -720,10 +721,10 @@
 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
-def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
+def SELEQZ : MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
-def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
+def SELNEZ : MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
Index: test/MC/Disassembler/Mips/micromips32r6.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips32r6.txt
+++ test/MC/Disassembler/Mips/micromips32r6.txt
@@ -23,3 +23,9 @@
 
 # CHECK: lwpc $2, 268
 0x78 0x48 0x00 0x43
+
+# CHECK: seleqz $2, $3, $4
+0x00 0x83 0x11 0x40
+
+# CHECK: selnez $2, $3, $4
+0x00 0x83 0x11 0x80
Index: test/MC/Mips/micromipsr6/valid.s
===================================================================
--- test/MC/Mips/micromipsr6/valid.s
+++ test/MC/Mips/micromipsr6/valid.s
@@ -9,3 +9,5 @@
   jialc $5, 256            # CHECK: jialc $5, 256       # encoding: [0xa4,0x05,0x01,0x00]
   jic   $5, 256            # CHECK: jic $5, 256         # encoding: [0xa0,0x05,0x01,0x00]
   lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
+  seleqz  $2,$3,$4         # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
+  selnez  $2,$3,$4         # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]