Index: llvm/lib/Transforms/Scalar/SCCP.cpp =================================================================== --- llvm/lib/Transforms/Scalar/SCCP.cpp +++ llvm/lib/Transforms/Scalar/SCCP.cpp @@ -649,17 +649,28 @@ Succs[0] = true; return; } - ValueLatticeElement SCValue = getValueState(SI->getCondition()); - ConstantInt *CI = getConstantInt(SCValue); + const ValueLatticeElement &SCValue = getValueState(SI->getCondition()); + if (ConstantInt *CI = getConstantInt(SCValue)) { + Succs[SI->findCaseValue(CI)->getSuccessorIndex()] = true; + return; + } - if (!CI) { // Overdefined or unknown condition? - // All destinations are executable! - if (!SCValue.isUnknownOrUndef()) - Succs.assign(TI.getNumSuccessors(), true); + if (SCValue.isConstantRange()) { + const ConstantRange &Range = SCValue.getConstantRange(); + for (const auto &Case : SI->cases()) { + const APInt &CaseValue = Case.getCaseValue()->getValue(); + if (Range.contains(CaseValue)) + Succs[Case.getSuccessorIndex()] = true; + } + + // TODO: Determine whether default case is reachable. + Succs[SI->case_default()->getSuccessorIndex()] = true; return; } - Succs[SI->findCaseValue(CI)->getSuccessorIndex()] = true; + // Overdefined or unknown condition? All destinations are executable! + if (!SCValue.isUnknownOrUndef()) + Succs.assign(TI.getNumSuccessors(), true); return; } @@ -1835,8 +1846,19 @@ BasicBlock *SingleSucc = *FeasibleSuccessors.begin(); BranchInst::Create(SingleSucc, BB); TI->eraseFromParent(); + } else if (FeasibleSuccessors.size() > 1) { + SwitchInstProfUpdateWrapper SI(*cast(TI)); + for (auto CI = SI->case_begin(); CI != SI->case_end();) { + if (!FeasibleSuccessors.count(CI->getCaseSuccessor())) { + SI.removeCase(CI); + // Don't increment CI, as we removed a case. + continue; + } + + ++CI; + } } else { - llvm_unreachable("Either all successors are feasible, or exactly one is"); + llvm_unreachable("Must have at least one feasible successor"); } return true; } Index: llvm/test/Transforms/SCCP/switch.ll =================================================================== --- llvm/test/Transforms/SCCP/switch.ll +++ llvm/test/Transforms/SCCP/switch.ll @@ -46,6 +46,7 @@ ret i32 %phi } +; TODO: Determine that the default destination is dead. define i32 @test_local_range(i32 %x) { ; CHECK-LABEL: @test_local_range( ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], 3 @@ -54,7 +55,6 @@ ; CHECK-NEXT: i32 0, label [[SWITCH_0:%.*]] ; CHECK-NEXT: i32 1, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 2, label [[SWITCH_2:%.*]] -; CHECK-NEXT: i32 3, label [[SWITCH_3:%.*]] ; CHECK-NEXT: ] ; CHECK: switch.default: ; CHECK-NEXT: ret i32 -1 @@ -64,8 +64,6 @@ ; CHECK-NEXT: ret i32 1 ; CHECK: switch.2: ; CHECK-NEXT: ret i32 2 -; CHECK: switch.3: -; CHECK-NEXT: ret i32 3 ; %c = icmp ult i32 %x, 3 call void @llvm.assume(i1 %c) @@ -92,6 +90,7 @@ ret i32 3 } +; TODO: Determine that case i3 is dead, even though the edge is shared? define i32 @test_duplicate_successors(i32 %x) { ; CHECK-LABEL: @test_duplicate_successors( ; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], 3 @@ -101,8 +100,6 @@ ; CHECK-NEXT: i32 1, label [[SWITCH_0]] ; CHECK-NEXT: i32 2, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 3, label [[SWITCH_1]] -; CHECK-NEXT: i32 4, label [[SWITCH_2:%.*]] -; CHECK-NEXT: i32 5, label [[SWITCH_2]] ; CHECK-NEXT: ] ; CHECK: switch.default: ; CHECK-NEXT: ret i32 -1 @@ -110,8 +107,6 @@ ; CHECK-NEXT: ret i32 0 ; CHECK: switch.1: ; CHECK-NEXT: ret i32 1 -; CHECK: switch.2: -; CHECK-NEXT: ret i32 2 ; %c = icmp ult i32 %x, 3 call void @llvm.assume(i1 %c) @@ -137,18 +132,17 @@ ret i32 2 } +; Case i32 2 is dead as well, but this cannot be determined based on +; range information. define internal i32 @test_ip_range(i32 %x) { ; CHECK-LABEL: @test_ip_range( ; CHECK-NEXT: switch i32 [[X:%.*]], label [[SWITCH_DEFAULT:%.*]] [ -; CHECK-NEXT: i32 0, label [[SWITCH_0:%.*]] +; CHECK-NEXT: i32 3, label [[SWITCH_3:%.*]] ; CHECK-NEXT: i32 1, label [[SWITCH_1:%.*]] ; CHECK-NEXT: i32 2, label [[SWITCH_2:%.*]] -; CHECK-NEXT: i32 3, label [[SWITCH_3:%.*]] ; CHECK-NEXT: ] ; CHECK: switch.default: ; CHECK-NEXT: ret i32 -1 -; CHECK: switch.0: -; CHECK-NEXT: ret i32 0 ; CHECK: switch.1: ; CHECK-NEXT: ret i32 1 ; CHECK: switch.2: