diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -906,6 +906,7 @@
         setOperationAction(ISD::SRL, MVT::v1i128, Expand);
         setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
+        setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
         setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
       }
       else {
diff --git a/llvm/test/CodeGen/PowerPC/setcc-vector.ll b/llvm/test/CodeGen/PowerPC/setcc-vector.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/setcc-vector.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+
+define <2 x i1> @setcc_v1i128([1 x i128] %a) {
+; CHECK-LABEL: setcc_v1i128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    cmpldi r3, 35708
+; CHECK-NEXT:    cmpdi cr1, r4, 0
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    crnand 4*cr5+lt, 4*cr1+eq, lt
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    mtvsrdd vs34, 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %b = extractvalue [1 x i128] %a, 0
+  %0 = insertelement <2 x i128> undef, i128 %b, i32 0
+  %1 = icmp ult <2 x i128> %0, <i128 35708, i128 1005868>
+  ret <2 x i1> %1
+}