Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -751,13 +751,12 @@ if (DestReg == AMDGPU::SCC) { // Copying 64-bit or 32-bit sources to SCC barely makes sense, // but SelectionDAG emits such copies for i1 sources. - // TODO: Use S_BITCMP0_B32 instead and only consider the 0th bit. if (AMDGPU::SReg_64RegClass.contains(SrcReg)) { SrcReg = RI.getSubReg(SrcReg, AMDGPU::sub0); } assert(AMDGPU::SReg_32RegClass.contains(SrcReg)); - BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32)) + BuildMI(MBB, MI, DL, get(AMDGPU::S_BITCMP1_B32)) .addReg(SrcReg, getKillRegState(KillSrc)) .addImm(0); Index: llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll @@ -37,7 +37,7 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_and_b32 s0, s0, s1 ; GCN-NEXT: s_and_b32 s0, s0, 1 -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, s3 ; GCN-NEXT: ; return to shader part epilog %cc.0 = trunc i32 %a.0 to i1 @@ -53,7 +53,7 @@ ; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_and_b32 s0, s0, 1 -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cbranch_scc0 BB3_2 ; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: v_mov_b32_e32 v0, 0 @@ -81,7 +81,7 @@ ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_and_b32 s0, s0, s1 ; GCN-NEXT: s_and_b32 s0, s0, 1 -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cbranch_scc0 BB4_2 ; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: v_mov_b32_e32 v0, 0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll @@ -138,7 +138,7 @@ ; CHECK-NEXT: s_cselect_b32 s4, 1, 0 ; CHECK-NEXT: s_xor_b32 s4, s4, 1 ; CHECK-NEXT: s_and_b32 s4, s4, 1 -; CHECK-NEXT: s_cmp_lg_u32 s4, 0 +; CHECK-NEXT: s_bitcmp1_b32 s4, 0 ; CHECK-NEXT: s_cbranch_scc0 BB4_6 ; CHECK-NEXT: ; %bb.1: ; %bb2 ; CHECK-NEXT: s_getpc_b64 s[4:5] Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll @@ -12,7 +12,7 @@ ; GCN-NEXT: s_cmp_lg_u32 s1, 0 ; GCN-NEXT: s_cselect_b32 s1, 1, 0 ; GCN-NEXT: s_and_b32 s1, s1, 1 -; GCN-NEXT: s_cmp_lg_u32 s1, 0 +; GCN-NEXT: s_bitcmp1_b32 s1, 0 ; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: v_mov_b32_e32 v0, 0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll @@ -10,7 +10,7 @@ ; GCN-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-NEXT: s_cselect_b32 s2, 1, 0 ; GCN-NEXT: s_and_b32 s2, s2, 1 -; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: v_mov_b32_e32 v0, 0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll @@ -60,7 +60,7 @@ ; CI-NEXT: s_cmp_eq_u32 s1, s0 ; CI-NEXT: s_cselect_b32 s0, 1, 0 ; CI-NEXT: s_and_b32 s0, s0, 1 -; CI-NEXT: s_cmp_lg_u32 s0, 0 +; CI-NEXT: s_bitcmp1_b32 s0, 0 ; CI-NEXT: s_cbranch_scc0 BB1_2 ; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: v_mov_b32_e32 v0, 0 @@ -77,7 +77,7 @@ ; GFX9-NEXT: s_cmp_eq_u32 s1, s0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_and_b32 s0, s0, 1 -; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_bitcmp1_b32 s0, 0 ; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll @@ -60,7 +60,7 @@ ; CI-NEXT: s_cmp_eq_u32 s1, s0 ; CI-NEXT: s_cselect_b32 s0, 1, 0 ; CI-NEXT: s_and_b32 s0, s0, 1 -; CI-NEXT: s_cmp_lg_u32 s0, 0 +; CI-NEXT: s_bitcmp1_b32 s0, 0 ; CI-NEXT: s_cbranch_scc0 BB1_2 ; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: v_mov_b32_e32 v0, 0 @@ -77,7 +77,7 @@ ; GFX9-NEXT: s_cmp_eq_u32 s1, s0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_and_b32 s0, s0, 1 -; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_bitcmp1_b32 s0, 0 ; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll @@ -12,7 +12,7 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_xor_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1 -; GFX9-NEXT: s_cmp_lg_u32 s1, 0 +; GFX9-NEXT: s_bitcmp1_b32 s1, 0 ; GFX9-NEXT: s_cbranch_scc0 BB0_2 ; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6 @@ -30,7 +30,7 @@ ; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: BB0_2: ; %Flow ; GFX9-NEXT: s_and_b32 s0, s0, 1 -; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_bitcmp1_b32 s0, 0 ; GFX9-NEXT: s_cbranch_scc0 BB0_4 ; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b @@ -87,7 +87,7 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_xor_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1 -; GFX9-NEXT: s_cmp_lg_u32 s1, 0 +; GFX9-NEXT: s_bitcmp1_b32 s1, 0 ; GFX9-NEXT: s_cbranch_scc0 BB1_2 ; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: s_getpc_b64 s[2:3] @@ -110,7 +110,7 @@ ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: BB1_2: ; %Flow ; GFX9-NEXT: s_and_b32 s0, s0, 1 -; GFX9-NEXT: s_cmp_lg_u32 s0, 0 +; GFX9-NEXT: s_bitcmp1_b32 s0, 0 ; GFX9-NEXT: s_cbranch_scc0 BB1_4 ; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: s_getpc_b64 s[0:1] Index: llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll @@ -23,7 +23,7 @@ ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cselect_b32 s6, 1, 0 ; GCN-NEXT: s_and_b32 s6, s6, 1 -; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_bitcmp1_b32 s6, 0 ; GCN-NEXT: s_cbranch_scc1 BB0_3 ; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: s_load_dword s6, s[4:5], 0xc @@ -31,7 +31,7 @@ ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cselect_b32 s6, 1, 0 ; GCN-NEXT: s_and_b32 s6, s6, 1 -; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_bitcmp1_b32 s6, 0 ; GCN-NEXT: s_cbranch_scc1 BB0_3 ; GCN-NEXT: ; %bb.2: ; %bb.1 ; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 @@ -104,7 +104,7 @@ ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cselect_b32 s6, 1, 0 ; GCN-NEXT: s_and_b32 s6, s6, 1 -; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_bitcmp1_b32 s6, 0 ; GCN-NEXT: s_cbranch_scc1 BB1_2 ; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -216,12 +216,12 @@ ; CHECK-NEXT: s_add_u32 s0, s2, s6 ; CHECK-NEXT: s_cselect_b32 s1, 1, 0 ; CHECK-NEXT: s_and_b32 s1, s1, 1 -; CHECK-NEXT: s_cmp_lg_u32 s1, 0 +; CHECK-NEXT: s_bitcmp1_b32 s1, 0 ; CHECK-NEXT: s_addc_u32 s1, s3, s6 ; CHECK-NEXT: s_add_u32 s10, s4, s8 ; CHECK-NEXT: s_cselect_b32 s3, 1, 0 ; CHECK-NEXT: s_and_b32 s3, s3, 1 -; CHECK-NEXT: s_cmp_lg_u32 s3, 0 +; CHECK-NEXT: s_bitcmp1_b32 s3, 0 ; CHECK-NEXT: s_mov_b32 s9, s8 ; CHECK-NEXT: s_addc_u32 s11, s5, s8 ; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] @@ -234,7 +234,7 @@ ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: s_cselect_b32 s0, 1, 0 ; CHECK-NEXT: s_and_b32 s0, s0, 1 -; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_bitcmp1_b32 s0, 0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; CHECK-NEXT: v_trunc_f32_e32 v1, v1 @@ -361,7 +361,7 @@ ; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: BB1_2: ; %Flow ; CHECK-NEXT: s_and_b32 s0, s0, 1 -; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_bitcmp1_b32 s0, 0 ; CHECK-NEXT: s_cbranch_scc0 BB1_4 ; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4 @@ -1212,7 +1212,7 @@ ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1224,7 +1224,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -1349,7 +1349,7 @@ ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v7 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1366,7 +1366,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -1935,7 +1935,7 @@ ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1947,7 +1947,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -2072,7 +2072,7 @@ ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc ; GISEL-NEXT: v_add_i32_e32 v1, vcc, 1, v7 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -2089,7 +2089,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -212,12 +212,12 @@ ; CHECK-NEXT: s_add_u32 s8, s2, s6 ; CHECK-NEXT: s_cselect_b32 s7, 1, 0 ; CHECK-NEXT: s_and_b32 s7, s7, 1 -; CHECK-NEXT: s_cmp_lg_u32 s7, 0 +; CHECK-NEXT: s_bitcmp1_b32 s7, 0 ; CHECK-NEXT: s_addc_u32 s9, s3, s6 ; CHECK-NEXT: s_add_u32 s10, s4, s0 ; CHECK-NEXT: s_cselect_b32 s3, 1, 0 ; CHECK-NEXT: s_and_b32 s3, s3, 1 -; CHECK-NEXT: s_cmp_lg_u32 s3, 0 +; CHECK-NEXT: s_bitcmp1_b32 s3, 0 ; CHECK-NEXT: s_mov_b32 s1, s0 ; CHECK-NEXT: s_addc_u32 s11, s5, s0 ; CHECK-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1] @@ -230,7 +230,7 @@ ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: s_cselect_b32 s0, 1, 0 ; CHECK-NEXT: s_and_b32 s0, s0, 1 -; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_bitcmp1_b32 s0, 0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; CHECK-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; CHECK-NEXT: v_trunc_f32_e32 v1, v1 @@ -355,7 +355,7 @@ ; CHECK-NEXT: s_mov_b32 s0, 0 ; CHECK-NEXT: BB1_2: ; %Flow ; CHECK-NEXT: s_and_b32 s0, s0, 1 -; CHECK-NEXT: s_cmp_lg_u32 s0, 0 +; CHECK-NEXT: s_bitcmp1_b32 s0, 0 ; CHECK-NEXT: s_cbranch_scc0 BB1_4 ; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s4 @@ -1190,7 +1190,7 @@ ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1202,7 +1202,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -1326,7 +1326,7 @@ ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s8, v8 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1343,7 +1343,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -1905,7 +1905,7 @@ ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 ; GISEL-NEXT: s_mov_b32 s7, s6 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -1917,7 +1917,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s12, 0, s9 ; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 @@ -2041,7 +2041,7 @@ ; GISEL-NEXT: s_cselect_b32 s5, 1, 0 ; GISEL-NEXT: v_subrev_i32_e32 v4, vcc, s8, v8 ; GISEL-NEXT: s_and_b32 s5, s5, 1 -; GISEL-NEXT: s_cmp_lg_u32 s5, 0 +; GISEL-NEXT: s_bitcmp1_b32 s5, 0 ; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; GISEL-NEXT: s_addc_u32 s5, 0, 0 @@ -2058,7 +2058,7 @@ ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, s7 ; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll @@ -206,7 +206,7 @@ ; CHECK-NEXT: s_and_b32 s4, s4, 1 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; CHECK-NEXT: s_cmp_lg_u32 s4, 0 +; CHECK-NEXT: s_bitcmp1_b32 s4, 0 ; CHECK-NEXT: s_subb_u32 s7, 0, s3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; CHECK-NEXT: v_trunc_f32_e32 v2, v2 @@ -327,7 +327,7 @@ ; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: BB1_2: ; %Flow ; CHECK-NEXT: s_and_b32 s1, s4, 1 -; CHECK-NEXT: s_cmp_lg_u32 s1, 0 +; CHECK-NEXT: s_bitcmp1_b32 s1, 0 ; CHECK-NEXT: s_cbranch_scc0 BB1_4 ; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 @@ -1116,7 +1116,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 @@ -1132,7 +1132,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 ; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 @@ -1777,7 +1777,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 @@ -1793,7 +1793,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 ; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll @@ -203,7 +203,7 @@ ; CHECK-NEXT: s_and_b32 s4, s4, 1 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; CHECK-NEXT: s_cmp_lg_u32 s4, 0 +; CHECK-NEXT: s_bitcmp1_b32 s4, 0 ; CHECK-NEXT: s_subb_u32 s7, 0, s3 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 ; CHECK-NEXT: v_trunc_f32_e32 v2, v2 @@ -323,7 +323,7 @@ ; CHECK-NEXT: s_mov_b32 s4, 0 ; CHECK-NEXT: BB1_2: ; %Flow ; CHECK-NEXT: s_and_b32 s1, s4, 1 -; CHECK-NEXT: s_cmp_lg_u32 s1, 0 +; CHECK-NEXT: s_bitcmp1_b32 s1, 0 ; CHECK-NEXT: s_cbranch_scc0 BB1_4 ; CHECK-NEXT: ; %bb.3: ; CHECK-NEXT: v_cvt_f32_u32_e32 v0, s2 @@ -1100,7 +1100,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 @@ -1116,7 +1116,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 ; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 @@ -1751,7 +1751,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v6 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s9, 0, 0 ; GISEL-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 @@ -1767,7 +1767,7 @@ ; GISEL-NEXT: v_mac_f32_e32 v5, 0xcf800000, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GISEL-NEXT: s_cmp_lg_u32 s4, 0 +; GISEL-NEXT: s_bitcmp1_b32 s4, 0 ; GISEL-NEXT: s_subb_u32 s6, 0, 0 ; GISEL-NEXT: v_mul_lo_u32 v8, s11, v6 ; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll @@ -179,7 +179,7 @@ ; GCN-NEXT: s_add_u32 s2, s2, s4 ; GCN-NEXT: s_cselect_b32 s4, 1, 0 ; GCN-NEXT: s_and_b32 s4, s4, 1 -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_addc_u32 s3, s3, s5 ; GCN-NEXT: ; return to shader part epilog %xor = xor i64 %a, %b Index: llvm/test/CodeGen/AMDGPU/addrspacecast.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/addrspacecast.ll +++ llvm/test/CodeGen/AMDGPU/addrspacecast.ll @@ -150,7 +150,7 @@ ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; CI-DAG: v_cmp_ne_u64_e64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} -; CI-DAG: s_cmp_lg_u32 s[[CMP_LO]], 0 +; CI-DAG: s_bitcmp1_b32 s[[CMP_LO]], 0 ; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 ; HSA-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 ; HSA-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] @@ -169,7 +169,7 @@ ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; CI-DAG: v_cmp_ne_u64_e64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} -; CI-DAG: s_cmp_lg_u32 s[[CMP_LO]], 0 +; CI-DAG: s_bitcmp1_b32 s[[CMP_LO]], 0 ; GFX9-DAG: s_cmp_lg_u64 s{{\[}}[[CMP_LO:[0-9]+]]:[[CMP_HI:[0-9]+]]{{\]}}, 0 ; HSA-DAG: s_cselect_b32 s[[PTR_LO]], s[[PTR_LO]], -1 ; HSA-DAG: v_mov_b32_e32 [[CASTPTR:v[0-9]+]], s[[PTR_LO]] Index: llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -442,7 +442,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 @@ -498,7 +498,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[2:3], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b32 s2, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s2, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s5 @@ -653,7 +653,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 @@ -711,7 +711,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s3 @@ -2162,7 +2162,7 @@ ; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s8, s10, 0 ; GCN-NEXT: s_ashr_i32 s2, s2, 16 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2 @@ -2181,7 +2181,7 @@ ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| ; GCN-NEXT: s_or_b32 s0, s0, 1 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2 -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s0, s0, 0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v3 ; GCN-NEXT: s_sext_i32_i16 s0, s1 @@ -2194,7 +2194,7 @@ ; GCN-NEXT: v_trunc_f32_e32 v4, v4 ; GCN-NEXT: v_mad_f32 v1, -v4, v0, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s0, s0, 0 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: s_ashr_i32 s2, s3, 16 @@ -2211,7 +2211,7 @@ ; GCN-NEXT: v_mad_f32 v4, -v5, v0, v4 ; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v5 ; GCN-NEXT: s_mov_b32 s0, 0xffff @@ -2357,7 +2357,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s8, s10, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s8, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 @@ -2375,7 +2375,7 @@ ; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2 ; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v1| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s8, s10, 0 ; GCN-NEXT: v_add_i32_e32 v1, vcc, s8, v3 ; GCN-NEXT: v_mul_lo_u32 v1, v1, s2 @@ -2393,7 +2393,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v4, v2, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v2| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s0, s0, 0 ; GCN-NEXT: v_add_i32_e32 v1, vcc, s0, v4 ; GCN-NEXT: s_ashr_i32 s0, s3, 16 @@ -2410,7 +2410,7 @@ ; GCN-NEXT: v_mad_f32 v4, -v5, v2, v4 ; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GCN-NEXT: v_cmp_ge_f32_e64 s[2:3], |v4|, |v2| -; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_bitcmp1_b32 s2, 0 ; GCN-NEXT: s_cselect_b32 s2, s9, 0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s2, v5 ; GCN-NEXT: v_mul_lo_u32 v2, v2, s0 @@ -2577,7 +2577,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: v_and_b32_e32 v0, 7, v0 @@ -2636,7 +2636,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s3 @@ -3000,7 +3000,7 @@ ; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s8, s10, 0 ; GCN-NEXT: s_ashr_i32 s0, s0, 16 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 @@ -3019,7 +3019,7 @@ ; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v2|, |v0| ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s0, s0, 0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s0, v3 ; GCN-NEXT: s_sext_i32_i16 s0, s3 @@ -3033,7 +3033,7 @@ ; GCN-NEXT: v_mad_f32 v3, -v4, v0, v3 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v4 @@ -3149,7 +3149,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s6, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s6, v2 ; GCN-NEXT: v_mov_b32_e32 v2, s0 @@ -3187,7 +3187,7 @@ ; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3 ; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v3|, |v4| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s0, s0, 0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v5 ; GCN-NEXT: v_mul_lo_u32 v3, v3, s1 @@ -3572,7 +3572,7 @@ ; GCN-NEXT: v_trunc_f32_e32 v4, v4 ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v3|, |v2| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: s_bfe_i32 s0, s0, 0xf000f @@ -3591,7 +3591,7 @@ ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v2| ; GCN-NEXT: v_cvt_f32_i32_e32 v2, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 15 ; GCN-NEXT: v_add_i32_e32 v4, vcc, s0, v5 @@ -3738,7 +3738,7 @@ ; GCN-NEXT: s_bfe_u32 s13, s0, 0xf000f ; GCN-NEXT: s_or_b32 s1, s1, 1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v3|, |v2| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s1, v4 ; GCN-NEXT: v_mul_lo_u32 v2, v2, s0 @@ -3756,7 +3756,7 @@ ; GCN-NEXT: v_mad_f32 v4, -v5, v3, v4 ; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, |v3| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: v_and_b32_e32 v1, s3, v1 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_bfe_i32 v4, v1, 0, 15 Index: llvm/test/CodeGen/AMDGPU/copy-phys-reg.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/AMDGPU/copy-phys-reg.mir @@ -0,0 +1,62 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s + +--- +name: copy_sgpr32_to_scc +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0 + ; GCN-LABEL: name: copy_sgpr32_to_scc + ; GCN: liveins: $sgpr0 + ; GCN: S_BITCMP1_B32 $sgpr0, 0, implicit-def $scc + ; GCN: S_ENDPGM 0, implicit $scc + $scc = COPY $sgpr0 + S_ENDPGM 0, implicit $scc + +... + +--- +name: copy_sgpr32_to_scc_kill +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0 + ; GCN-LABEL: name: copy_sgpr32_to_scc_kill + ; GCN: liveins: $sgpr0 + ; GCN: S_BITCMP1_B32 killed $sgpr0, 0, implicit-def $scc + ; GCN: S_ENDPGM 0, implicit $scc + $scc = COPY killed $sgpr0 + S_ENDPGM 0, implicit $scc + +... + +--- +name: copy_scc_to_sgpr32 +tracksRegLiveness: true +body: | + bb.0: + liveins: $scc + ; GCN-LABEL: name: copy_scc_to_sgpr32 + ; GCN: liveins: $scc + ; GCN: $sgpr11 = S_CSELECT_B32 1, 0, implicit $scc + ; GCN: S_ENDPGM 0, implicit $sgpr11 + $sgpr11 = COPY $scc + S_ENDPGM 0, implicit $sgpr11 + +... + +--- +name: copy_scc_to_sgpr32_kill +tracksRegLiveness: true +body: | + bb.0: + liveins: $scc + ; GCN-LABEL: name: copy_scc_to_sgpr32_kill + ; GCN: liveins: $scc + ; GCN: $sgpr11 = S_CSELECT_B32 1, 0, implicit $scc + ; GCN: S_ENDPGM 0, implicit $sgpr11 + $sgpr11 = COPY killed $scc + S_ENDPGM 0, implicit $sgpr11 + +... Index: llvm/test/CodeGen/AMDGPU/sdiv64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -512,7 +512,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -542,7 +542,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -620,7 +620,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -648,7 +648,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -684,7 +684,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 @@ -714,7 +714,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 @@ -751,7 +751,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 @@ -781,7 +781,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23 @@ -818,7 +818,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 @@ -848,7 +848,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 @@ -886,7 +886,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s3, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2 @@ -902,7 +902,7 @@ ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24 @@ -933,7 +933,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s3, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s2 @@ -949,7 +949,7 @@ ; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v3|, |v2| -; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s0, v4 ; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24 @@ -1884,7 +1884,7 @@ ; GCN-NEXT: v_mad_f32 v2, -v1, v0, s3 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -1911,7 +1911,7 @@ ; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s3 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v1 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -1943,7 +1943,7 @@ ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-NEXT: s_or_b32 s6, s4, 1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s8 -; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -1969,7 +1969,7 @@ ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, s8 -; GCN-IR-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s4, 0 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v1 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 Index: llvm/test/CodeGen/AMDGPU/srem64.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/srem64.ll +++ llvm/test/CodeGen/AMDGPU/srem64.ll @@ -489,7 +489,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -521,7 +521,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -560,7 +560,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -592,7 +592,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -685,7 +685,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -717,7 +717,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -756,7 +756,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -788,7 +788,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s8, 0 ; GCN-IR-NEXT: s_cselect_b32 s1, s1, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 @@ -827,7 +827,7 @@ ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s8, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s6 @@ -857,7 +857,7 @@ ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s8, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6 @@ -2062,7 +2062,7 @@ ; GCN-NEXT: v_mad_f32 v2, -v1, v0, s6 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v0| -; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_bitcmp1_b32 s6, 0 ; GCN-NEXT: s_cselect_b32 s5, s5, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s5, v1 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 @@ -2089,7 +2089,7 @@ ; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s6 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v2|, |v0| -; GCN-IR-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s6, 0 ; GCN-IR-NEXT: s_cselect_b32 s5, s5, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s5, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 @@ -2121,7 +2121,7 @@ ; GCN-NEXT: v_mad_f32 v0, -v1, s1, v0 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s1 -; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-NEXT: s_cselect_b32 s0, s7, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1 ; GCN-NEXT: s_movk_i32 s0, 0x5b7f @@ -2150,7 +2150,7 @@ ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s1, v0 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s1 -; GCN-IR-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-IR-NEXT: s_bitcmp1_b32 s0, 0 ; GCN-IR-NEXT: s_cselect_b32 s0, s7, 0 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v1 ; GCN-IR-NEXT: s_movk_i32 s0, 0x5b7f Index: llvm/test/CodeGen/AMDGPU/trunc.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/trunc.ll +++ llvm/test/CodeGen/AMDGPU/trunc.ll @@ -98,7 +98,7 @@ ; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c ; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]] ; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}} -; GCN: s_cmp_lg_u32 s[[VLO]], 0 +; GCN: s_bitcmp1_b32 s[[VLO]], 0 ; GCN: s_cselect_b32 {{s[0-9]+}}, 63, -12 define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) { %trunc = trunc i64 %x to i1