Index: llvm/lib/Target/ARM/ARMISelLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.h +++ llvm/lib/Target/ARM/ARMISelLowering.h @@ -229,12 +229,18 @@ VADDLVpu, VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask VADDLVApu, - VMLAVs, - VMLAVu, - VMLALVs, - VMLALVu, - VMLALVAs, - VMLALVAu, + VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply them + VMLAVu, // and add the results together, returning an i32 of their sum + VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask + VMLAVpu, + VMLALVs, // Same as VMLAV but with i64, returning the low and + VMLALVu, // high 32-bit halves of the sum + VMLALVps, // Same as VMLALV[su] with a v4i1 predicate mask + VMLALVpu, + VMLALVAs, // Same as VMLALV but also add an input accumulator + VMLALVAu, // provided as low and high halves + VMLALVAps, // Same as VMLALVA[su] with a v4i1 predicate mask + VMLALVApu, SMULWB, // Signed multiply word by half word, bottom SMULWT, // Signed multiply word by half word, top Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1730,10 +1730,16 @@ case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu"; case ARMISD::VMLAVs: return "ARMISD::VMLAVs"; case ARMISD::VMLAVu: return "ARMISD::VMLAVu"; + case ARMISD::VMLAVps: return "ARMISD::VMLAVps"; + case ARMISD::VMLAVpu: return "ARMISD::VMLAVpu"; case ARMISD::VMLALVs: return "ARMISD::VMLALVs"; case ARMISD::VMLALVu: return "ARMISD::VMLALVu"; + case ARMISD::VMLALVps: return "ARMISD::VMLALVps"; + case ARMISD::VMLALVpu: return "ARMISD::VMLALVpu"; case ARMISD::VMLALVAs: return "ARMISD::VMLALVAs"; case ARMISD::VMLALVAu: return "ARMISD::VMLALVAu"; + case ARMISD::VMLALVAps: return "ARMISD::VMLALVAps"; + case ARMISD::VMLALVApu: return "ARMISD::VMLALVApu"; case ARMISD::UMAAL: return "ARMISD::UMAAL"; case ARMISD::UMLAL: return "ARMISD::UMLAL"; case ARMISD::SMLAL: return "ARMISD::SMLAL"; @@ -12261,6 +12267,14 @@ return M; if (SDValue M = MakeVecReduce(ARMISD::VMLALVu, ARMISD::VMLALVAu, N1, N0)) return M; + if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N0, N1)) + return M; + if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N0, N1)) + return M; + if (SDValue M = MakeVecReduce(ARMISD::VMLALVps, ARMISD::VMLALVAps, N1, N0)) + return M; + if (SDValue M = MakeVecReduce(ARMISD::VMLALVpu, ARMISD::VMLALVApu, N1, N0)) + return M; return SDValue(); } @@ -14760,6 +14774,26 @@ return true; return false; }; + auto IsPredVMLAV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef ExtTypes, + SDValue &A, SDValue &B, SDValue &Mask) { + if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || + !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) + return false; + Mask = N0->getOperand(0); + SDValue Mul = N0->getOperand(1); + if (Mul->getOpcode() != ISD::MUL) + return false; + SDValue ExtA = Mul->getOperand(0); + SDValue ExtB = Mul->getOperand(1); + if (ExtA->getOpcode() != ExtendCode && ExtB->getOpcode() != ExtendCode) + return false; + A = ExtA->getOperand(0); + B = ExtB->getOperand(0); + if (A.getValueType() == B.getValueType() && + llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; })) + return true; + return false; + }; auto Create64bitNode = [&](unsigned Opcode, ArrayRef Ops) { SDValue Node = DAG.getNode(Opcode, dl, {MVT::i32, MVT::i32}, Ops); return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Node, @@ -14794,6 +14828,15 @@ return Create64bitNode(ARMISD::VMLALVs, {A, B}); if (IsVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B)) return Create64bitNode(ARMISD::VMLALVu, {A, B}); + + if (IsPredVMLAV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B, Mask)) + return DAG.getNode(ARMISD::VMLAVps, dl, ResVT, A, B, Mask); + if (IsPredVMLAV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B, Mask)) + return DAG.getNode(ARMISD::VMLAVpu, dl, ResVT, A, B, Mask); + if (IsPredVMLAV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B, Mask)) + return Create64bitNode(ARMISD::VMLALVps, {A, B, Mask}); + if (IsPredVMLAV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v4i32}, A, B, Mask)) + return Create64bitNode(ARMISD::VMLALVpu, {A, B, Mask}); return SDValue(); } Index: llvm/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrMVE.td +++ llvm/lib/Target/ARM/ARMInstrMVE.td @@ -1131,12 +1131,28 @@ SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>, SDTCisVec<4>, SDTCisVec<5> ]>; +def SDTVecReduce2P : SDTypeProfile<1, 3, [ // VMLAV + SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3> +]>; +def SDTVecReduce2LP : SDTypeProfile<2, 3, [ // VMLALV + SDTCisInt<0>, SDTCisInt<1>, SDTCisVec<2>, SDTCisVec<3>, SDTCisVec<4> +]>; +def SDTVecReduce2LAP : SDTypeProfile<2, 5, [ // VMLALVA + SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>, + SDTCisVec<4>, SDTCisVec<5>, SDTCisVec<6> +]>; def ARMVMLAVs : SDNode<"ARMISD::VMLAVs", SDTVecReduce2>; def ARMVMLAVu : SDNode<"ARMISD::VMLAVu", SDTVecReduce2>; def ARMVMLALVs : SDNode<"ARMISD::VMLALVs", SDTVecReduce2L>; def ARMVMLALVu : SDNode<"ARMISD::VMLALVu", SDTVecReduce2L>; -def ARMVMLALVAs : SDNode<"ARMISD::VMLALVAs", SDTVecReduce2LA>; -def ARMVMLALVAu : SDNode<"ARMISD::VMLALVAu", SDTVecReduce2LA>; +def ARMVMLALVAs : SDNode<"ARMISD::VMLALVAs", SDTVecReduce2LA>; +def ARMVMLALVAu : SDNode<"ARMISD::VMLALVAu", SDTVecReduce2LA>; +def ARMVMLAVps : SDNode<"ARMISD::VMLAVps", SDTVecReduce2P>; +def ARMVMLAVpu : SDNode<"ARMISD::VMLAVpu", SDTVecReduce2P>; +def ARMVMLALVps : SDNode<"ARMISD::VMLALVps", SDTVecReduce2LP>; +def ARMVMLALVpu : SDNode<"ARMISD::VMLALVpu", SDTVecReduce2LP>; +def ARMVMLALVAps : SDNode<"ARMISD::VMLALVAps", SDTVecReduce2LAP>; +def ARMVMLALVApu : SDNode<"ARMISD::VMLALVApu", SDTVecReduce2LAP>; let Predicates = [HasMVEInt] in { def : Pat<(i32 (vecreduce_add (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)))), @@ -1155,22 +1171,68 @@ (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; def : Pat<(i32 (add (i32 (vecreduce_add (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)))), - (i32 tGPREven:$src3))), + (i32 tGPREven:$src3))), (i32 (MVE_VMLADAVau32 $src3, $src1, $src2))>; def : Pat<(i32 (add (i32 (vecreduce_add (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)))), - (i32 tGPREven:$src3))), + (i32 tGPREven:$src3))), (i32 (MVE_VMLADAVau16 $src3, $src1, $src2))>; def : Pat<(i32 (add (ARMVMLAVs (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), tGPREven:$Rd)), (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>; def : Pat<(i32 (add (ARMVMLAVu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), tGPREven:$Rd)), (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)))>; def : Pat<(i32 (add (i32 (vecreduce_add (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)))), - (i32 tGPREven:$src3))), + (i32 tGPREven:$src3))), (i32 (MVE_VMLADAVau8 $src3, $src1, $src2))>; def : Pat<(i32 (add (ARMVMLAVs (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)), (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; def : Pat<(i32 (add (ARMVMLAVu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)), tGPREven:$Rd)), (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2)))>; + + // Predicated + def : Pat<(i32 (vecreduce_add (vselect (v4i1 VCCR:$pred), + (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)), + (v4i32 MVEimmAllZerosV)))), + (i32 (MVE_VMLADAVu32 $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (vecreduce_add (vselect (v8i1 VCCR:$pred), + (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)), + (v8i16 MVEimmAllZerosV)))), + (i32 (MVE_VMLADAVu16 $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))), + (i32 (MVE_VMLADAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred))), + (i32 (MVE_VMLADAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (vecreduce_add (vselect (v16i1 VCCR:$pred), + (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)), + (v16i8 MVEimmAllZerosV)))), + (i32 (MVE_VMLADAVu8 $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))), + (i32 (MVE_VMLADAVs8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred))), + (i32 (MVE_VMLADAVu8 (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; + + def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v4i1 VCCR:$pred), + (mul (v4i32 MQPR:$src1), (v4i32 MQPR:$src2)), + (v4i32 MVEimmAllZerosV)))), + (i32 tGPREven:$src3))), + (i32 (MVE_VMLADAVau32 $src3, $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v8i1 VCCR:$pred), + (mul (v8i16 MQPR:$src1), (v8i16 MQPR:$src2)), + (v8i16 MVEimmAllZerosV)))), + (i32 tGPREven:$src3))), + (i32 (MVE_VMLADAVau16 $src3, $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (add (ARMVMLAVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)), + (i32 (MVE_VMLADAVas16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (add (ARMVMLAVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), tGPREven:$Rd)), + (i32 (MVE_VMLADAVau16 tGPREven:$Rd, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (add (i32 (vecreduce_add (vselect (v16i1 VCCR:$pred), + (mul (v16i8 MQPR:$src1), (v16i8 MQPR:$src2)), + (v16i8 MVEimmAllZerosV)))), + (i32 tGPREven:$src3))), + (i32 (MVE_VMLADAVau8 $src3, $src1, $src2, ARMVCCThen, $pred))>; + def : Pat<(i32 (add (ARMVMLAVps (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)), + (i32 (MVE_VMLADAVas8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; + def : Pat<(i32 (add (ARMVMLAVpu (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), (v16i1 VCCR:$pred)), tGPREven:$Rd)), + (i32 (MVE_VMLADAVau8 tGPREven:$Rd, (v16i8 MQPR:$val1), (v16i8 MQPR:$val2), ARMVCCThen, $pred))>; } // vmlav aliases vmladav @@ -1290,6 +1352,25 @@ (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>; def : Pat<(ARMVMLALVAu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2)), (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2))>; + + // Predicated + def : Pat<(ARMVMLALVps (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), + (MVE_VMLALDAVs32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVpu (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), + (MVE_VMLALDAVu32 (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVps (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), + (MVE_VMLALDAVs16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVpu (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), + (MVE_VMLALDAVu16 (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; + + def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), + (MVE_VMLALDAVas32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), (v4i1 VCCR:$pred)), + (MVE_VMLALDAVau32 tGPREven:$Rda, tGPROdd:$Rdb, (v4i32 MQPR:$val1), (v4i32 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVAps tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), + (MVE_VMLALDAVas16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; + def : Pat<(ARMVMLALVApu tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), (v8i1 VCCR:$pred)), + (MVE_VMLALDAVau16 tGPREven:$Rda, tGPROdd:$Rdb, (v8i16 MQPR:$val1), (v8i16 MQPR:$val2), ARMVCCThen, $pred)>; } // vmlalv aliases vmlaldav Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll +++ llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll @@ -4,9 +4,8 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i32: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i32 q0, q0, q1 ; CHECK-NEXT: vpt.i32 eq, q2, zr -; CHECK-NEXT: vaddvt.u32 r0, q0 +; CHECK-NEXT: vmlavt.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -19,53 +18,8 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i64_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.f32 s12, s4 -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: vmov.f32 s16, s0 -; CHECK-NEXT: vmov.f32 s14, s5 -; CHECK-NEXT: vmov.f32 s18, s1 -; CHECK-NEXT: vmullb.u32 q5, q4, q3 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vand q2, q5, q2 -; CHECK-NEXT: vmov r3, s10 -; CHECK-NEXT: vmov r1, s8 -; CHECK-NEXT: vmov r12, s11 -; CHECK-NEXT: vmov r2, s9 -; CHECK-NEXT: vmov.f32 s8, s6 -; CHECK-NEXT: vmov.f32 s10, s7 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vmullb.u32 q0, q1, q2 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r0, r0, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r1 -; CHECK-NEXT: adc.w r1, r2, r3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlalvt.u32 r0, r1, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -80,62 +34,8 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i64_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.f32 s16, s4 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.f32 s20, s0 -; CHECK-NEXT: vmov.f32 s18, s5 -; CHECK-NEXT: vmov.f32 s22, s1 -; CHECK-NEXT: vmov r0, s16 -; CHECK-NEXT: vmov r1, s20 -; CHECK-NEXT: smull r0, r1, r1, r0 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov r0, s18 -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov r1, s22 -; CHECK-NEXT: smull r0, r1, r1, r0 -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vand q2, q3, q2 -; CHECK-NEXT: vmov r3, s10 -; CHECK-NEXT: vmov r1, s8 -; CHECK-NEXT: vmov r12, s11 -; CHECK-NEXT: vmov r2, s9 -; CHECK-NEXT: vmov.f32 s8, s6 -; CHECK-NEXT: vmov.f32 s10, s7 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vmullb.s32 q0, q1, q2 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r0, r0, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r1 -; CHECK-NEXT: adc.w r1, r2, r3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlalvt.s32 r0, r1, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -222,71 +122,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: vmov.u16 r0, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[0] -; CHECK-NEXT: vmovlb.u16 q4, q3 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q2[4] -; CHECK-NEXT: vmovlb.u16 q5, q3 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q3, q5, q4 -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[5] -; CHECK-NEXT: vmov.32 q4[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[6] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[7] -; CHECK-NEXT: vmov.32 q4[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[4] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[5] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmullb.u16 q0, q1, q2 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vaddv.u32 r0, q3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavt.u16 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -301,71 +138,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: vmov.u16 r0, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[0] -; CHECK-NEXT: vmovlb.s16 q4, q3 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q2[4] -; CHECK-NEXT: vmovlb.s16 q5, q3 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q3, q5, q4 -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[5] -; CHECK-NEXT: vmov.32 q4[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[6] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[7] -; CHECK-NEXT: vmov.32 q4[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[4] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[5] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmullb.s16 q0, q1, q2 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vaddv.u32 r0, q3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavt.s16 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -380,10 +154,11 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.u16 q0, q0, q1 -; CHECK-NEXT: vmovlb.u16 q1, q2 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvt.u32 r0, q0 +; CHECK-NEXT: vmovlb.u16 q1, q1 +; CHECK-NEXT: vmovlb.u16 q0, q0 +; CHECK-NEXT: vmovlb.u16 q2, q2 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavt.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -398,10 +173,11 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.s16 q0, q0, q1 -; CHECK-NEXT: vmovlb.u16 q1, q2 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvt.u32 r0, q0 +; CHECK-NEXT: vmovlb.s16 q1, q1 +; CHECK-NEXT: vmovlb.s16 q0, q0 +; CHECK-NEXT: vmovlb.u16 q2, q2 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavt.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -416,9 +192,8 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i16 q0, q0, q1 ; CHECK-NEXT: vpt.i16 eq, q2, zr -; CHECK-NEXT: vaddvt.u16 r0, q0 +; CHECK-NEXT: vmlavt.u16 r0, q0, q1 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -432,183 +207,9 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_zext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i64_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r7, lr} -; CHECK-NEXT: push {r7, lr} -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.u16 r2, q0[0] -; CHECK-NEXT: vpsel q3, q4, q3 -; CHECK-NEXT: vmov.32 q6[0], r2 -; CHECK-NEXT: vmov.u16 r0, q3[0] -; CHECK-NEXT: vmov.u16 r2, q0[1] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q3[1] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q3[2] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q3[3] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.32 q6[2], r2 -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.i64 q2, #0xffff -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: vand q6, q6, q2 -; CHECK-NEXT: vmov r2, s24 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.32 q4[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: vmov.32 q5[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q5[2], r1 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vmov r1, s20 -; CHECK-NEXT: umull r1, r2, r2, r1 -; CHECK-NEXT: vmov.32 q7[0], r1 -; CHECK-NEXT: vmov r1, s22 -; CHECK-NEXT: vmov.32 q7[1], r2 -; CHECK-NEXT: vmov r2, s26 -; CHECK-NEXT: umull r1, r2, r2, r1 -; CHECK-NEXT: vmov.32 q7[2], r1 -; CHECK-NEXT: vmov.32 q7[3], r2 -; CHECK-NEXT: vand q4, q7, q4 -; CHECK-NEXT: vmov r1, s18 -; CHECK-NEXT: vmov r2, s16 -; CHECK-NEXT: vmov r12, s19 -; CHECK-NEXT: vmov r3, s17 -; CHECK-NEXT: adds r1, r1, r2 -; CHECK-NEXT: adc.w r2, r3, r12 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q4[0], r3 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q4[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[2] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.32 q6[0], r3 -; CHECK-NEXT: vmov.32 q4[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.u16 r3, q0[3] -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vmov.32 q6[2], r3 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vand q6, q6, q2 -; CHECK-NEXT: vmov r0, s20 -; CHECK-NEXT: vmov r3, s24 -; CHECK-NEXT: umull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q7[0], r0 -; CHECK-NEXT: vmov r0, s22 -; CHECK-NEXT: vmov.32 q7[1], r3 -; CHECK-NEXT: vmov r3, s26 -; CHECK-NEXT: umull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q7[2], r0 -; CHECK-NEXT: vmov.32 q7[3], r3 -; CHECK-NEXT: vand q4, q7, q4 -; CHECK-NEXT: vmov r3, s16 -; CHECK-NEXT: vmov r0, s17 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s19 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s18 -; CHECK-NEXT: adds.w r12, r1, r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: adc.w r1, r2, r3 -; CHECK-NEXT: vmov.u16 r2, q3[4] -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: vmov.u16 r2, q3[5] -; CHECK-NEXT: vmov.32 q4[1], r2 -; CHECK-NEXT: vmov.u16 r2, q3[6] -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vmov.u16 r2, q3[7] -; CHECK-NEXT: vmov.32 q4[3], r2 -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vcmp.i32 ne, q4, zr -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vmov r0, s20 -; CHECK-NEXT: and r3, lr, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q3[0], r3 -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q3[2], r3 -; CHECK-NEXT: vmov.32 q3[3], r3 -; CHECK-NEXT: vmov.u16 r3, q1[4] -; CHECK-NEXT: vmov.32 q4[0], r3 -; CHECK-NEXT: vmov.u16 r3, q1[5] -; CHECK-NEXT: vmov.32 q4[2], r3 -; CHECK-NEXT: vand q4, q4, q2 -; CHECK-NEXT: vmov r3, s16 -; CHECK-NEXT: umull r0, r3, r0, r3 -; CHECK-NEXT: vmov.32 q6[0], r0 -; CHECK-NEXT: vmov r0, s18 -; CHECK-NEXT: vmov.32 q6[1], r3 -; CHECK-NEXT: vmov r3, s22 -; CHECK-NEXT: umull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q6[2], r0 -; CHECK-NEXT: vmov.32 q6[3], r3 -; CHECK-NEXT: vand q3, q6, q3 -; CHECK-NEXT: vmov r3, s12 -; CHECK-NEXT: vmov r0, s13 -; CHECK-NEXT: vmov r2, s14 -; CHECK-NEXT: adds.w r3, r3, r12 -; CHECK-NEXT: adcs r1, r0 -; CHECK-NEXT: vmov r0, s15 -; CHECK-NEXT: adds r3, r3, r2 -; CHECK-NEXT: vmov.u16 r2, q0[6] -; CHECK-NEXT: adcs r1, r0 -; CHECK-NEXT: ubfx r0, lr, #8, #1 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: ubfx r0, lr, #12, #1 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vand q1, q4, q2 -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: vmov.u16 r2, q0[7] -; CHECK-NEXT: vmov r0, s4 -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vand q0, q4, q2 -; CHECK-NEXT: vmov r2, s0 -; CHECK-NEXT: umull r0, r2, r2, r0 -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov r0, s6 -; CHECK-NEXT: vmov.32 q2[1], r2 -; CHECK-NEXT: vmov r2, s2 -; CHECK-NEXT: umull r0, r2, r2, r0 -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.32 q2[3], r2 -; CHECK-NEXT: vand q0, q2, q3 -; CHECK-NEXT: vmov r2, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r2, r2, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r1, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r2 -; CHECK-NEXT: adcs r1, r3 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: pop {r7, pc} +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlalvt.u16 r0, r1, q0, q1 +; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer %xx = zext <8 x i16> %x to <8 x i64> @@ -622,155 +223,8 @@ define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_sext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i64_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9} -; CHECK-NEXT: vpush {d8, d9} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.u16 r2, q0[0] -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: vmov.u16 r0, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: sxth r1, r1 -; CHECK-NEXT: smull r1, r2, r2, r1 -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q4[1], r2 -; CHECK-NEXT: vmov.u16 r2, q0[1] -; CHECK-NEXT: sxth r1, r1 -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: smull r1, r2, r2, r1 -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.32 q4[3], r2 -; CHECK-NEXT: vand q3, q4, q3 -; CHECK-NEXT: vmov r1, s14 -; CHECK-NEXT: vmov r2, s12 -; CHECK-NEXT: vmov r12, s15 -; CHECK-NEXT: vmov r3, s13 -; CHECK-NEXT: adds r1, r1, r2 -; CHECK-NEXT: adc.w r2, r3, r12 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q3[0], r3 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: smull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.32 q4[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[3] -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.32 q4[3], r3 -; CHECK-NEXT: vand q3, q4, q3 -; CHECK-NEXT: vmov r3, s12 -; CHECK-NEXT: vmov r0, s13 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s15 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s14 -; CHECK-NEXT: adds.w r12, r1, r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: adc.w r1, r2, r3 -; CHECK-NEXT: vmov.u16 r2, q2[4] -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov.u16 r2, q2[5] -; CHECK-NEXT: vmov.32 q3[1], r2 -; CHECK-NEXT: vmov.u16 r2, q2[6] -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmov.u16 r2, q2[7] -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[0], r3 -; CHECK-NEXT: vmov.32 q2[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[2], r3 -; CHECK-NEXT: vmov.32 q2[3], r3 -; CHECK-NEXT: vmov.u16 r3, q1[4] -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r0, r3, r0, r3 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[5] -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r0, r3, r3, r0 -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.32 q3[3], r3 -; CHECK-NEXT: vand q2, q3, q2 -; CHECK-NEXT: vmov r3, s8 -; CHECK-NEXT: vmov r0, s9 -; CHECK-NEXT: adds.w r3, r3, r12 -; CHECK-NEXT: adc.w r12, r1, r0 -; CHECK-NEXT: vmov r1, s10 -; CHECK-NEXT: vmov r0, s11 -; CHECK-NEXT: adds r3, r3, r1 -; CHECK-NEXT: adc.w r1, r12, r0 -; CHECK-NEXT: ubfx r0, r2, #8, #1 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: ubfx r0, r2, #12, #1 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.u16 r2, q0[6] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: smull r0, r2, r2, r0 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q3[1], r2 -; CHECK-NEXT: vmov.u16 r2, q0[7] -; CHECK-NEXT: sxth r0, r0 -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: smull r0, r2, r2, r0 -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: vand q0, q3, q2 -; CHECK-NEXT: vmov r2, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r2, r2, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r1, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r2 -; CHECK-NEXT: adcs r1, r3 -; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlalvt.s16 r0, r1, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -888,20 +342,104 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #64 -; CHECK-NEXT: sub sp, #64 -; CHECK-NEXT: vmov q3, q2 -; CHECK-NEXT: vmov q4, q0 -; CHECK-NEXT: vcmp.i8 eq, q3, zr +; CHECK-NEXT: vpt.i8 eq, q2, zr +; CHECK-NEXT: vmlavt.u8 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <16 x i8> %b, zeroinitializer + %xx = zext <16 x i8> %x to <16 x i32> + %yy = zext <16 x i8> %y to <16 x i32> + %m = mul <16 x i32> %xx, %yy + %s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) + ret i32 %z +} + +define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { +; CHECK-LABEL: add_v16i8_v16i32_sext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vpt.i8 eq, q2, zr +; CHECK-NEXT: vmlavt.s8 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <16 x i8> %b, zeroinitializer + %xx = sext <16 x i8> %x to <16 x i32> + %yy = sext <16 x i8> %y to <16 x i32> + %m = mul <16 x i32> %xx, %yy + %s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) + ret i32 %z +} + +define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { +; CHECK-LABEL: add_v4i8_v4i32_zext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov.i32 q3, #0xff +; CHECK-NEXT: vand q1, q1, q3 +; CHECK-NEXT: vand q0, q0, q3 +; CHECK-NEXT: vand q2, q2, q3 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavt.u32 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <4 x i8> %b, zeroinitializer + %xx = zext <4 x i8> %x to <4 x i32> + %yy = zext <4 x i8> %y to <4 x i32> + %m = mul <4 x i32> %xx, %yy + %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) + ret i32 %z +} + +define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { +; CHECK-LABEL: add_v4i8_v4i32_sext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmovlb.s8 q1, q1 +; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmov.i32 q3, #0xff +; CHECK-NEXT: vmovlb.s16 q1, q1 +; CHECK-NEXT: vand q2, q2, q3 +; CHECK-NEXT: vmovlb.s16 q0, q0 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavt.u32 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <4 x i8> %b, zeroinitializer + %xx = sext <4 x i8> %x to <4 x i32> + %yy = sext <4 x i8> %y to <4 x i32> + %m = mul <4 x i32> %xx, %yy + %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) + ret i32 %z +} + +define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { +; CHECK-LABEL: add_v16i8_v16i16_zext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .vsave {d8, d9, d10, d11} +; CHECK-NEXT: vpush {d8, d9, d10, d11} +; CHECK-NEXT: vcmp.i8 eq, q2, zr +; CHECK-NEXT: vmov.i8 q2, #0x0 ; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vmov q2, q1 -; CHECK-NEXT: vpsel q1, q3, q0 -; CHECK-NEXT: vmov q5, q3 +; CHECK-NEXT: vpsel q2, q3, q2 +; CHECK-NEXT: vmov.u8 r0, q2[0] +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q2[1] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q2[2] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q2[3] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q2[4] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q2[5] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q2[6] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q2[7] +; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.u8 r0, q1[0] -; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill +; CHECK-NEXT: vcmp.i16 ne, q3, zr ; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vmov.16 q3[1], r0 @@ -917,411 +455,94 @@ ; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.u8 r0, q1[7] ; CHECK-NEXT: vmov.16 q3[7], r0 -; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill -; CHECK-NEXT: vcmp.i16 ne, q3, zr -; CHECK-NEXT: vmov.i32 q3, #0xff -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill -; CHECK-NEXT: vmov.u16 r0, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q4[4] -; CHECK-NEXT: vmov.32 q6[0], r0 -; CHECK-NEXT: vmov.u8 r0, q4[5] -; CHECK-NEXT: vmov.32 q6[1], r0 -; CHECK-NEXT: vmov.u8 r0, q4[6] -; CHECK-NEXT: vmov.32 q6[2], r0 -; CHECK-NEXT: vmov.u8 r0, q4[7] -; CHECK-NEXT: vmov.32 q6[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[8] -; CHECK-NEXT: vand q7, q0, q3 -; CHECK-NEXT: vmov.16 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[9] -; CHECK-NEXT: vand q3, q6, q3 -; CHECK-NEXT: vmov.16 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[10] -; CHECK-NEXT: vmov.16 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[11] -; CHECK-NEXT: vmov.16 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[12] -; CHECK-NEXT: vmov.16 q0[4], r0 -; CHECK-NEXT: vmov.u8 r0, q1[13] -; CHECK-NEXT: vmov.16 q0[5], r0 -; CHECK-NEXT: vmov.u8 r0, q1[14] -; CHECK-NEXT: vmov.16 q0[6], r0 -; CHECK-NEXT: vmov.u8 r0, q1[15] -; CHECK-NEXT: vmov.i32 q6, #0x0 -; CHECK-NEXT: vmov.16 q0[7], r0 -; CHECK-NEXT: vstrw.32 q6, [sp, #48] @ 16-byte Spill +; CHECK-NEXT: vmov.u8 r0, q0[0] +; CHECK-NEXT: vmovlb.u8 q4, q3 +; CHECK-NEXT: vmov.16 q3[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[1] +; CHECK-NEXT: vmov.16 q3[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[2] +; CHECK-NEXT: vmov.16 q3[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[3] +; CHECK-NEXT: vmov.16 q3[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[4] +; CHECK-NEXT: vmov.16 q3[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[5] +; CHECK-NEXT: vmov.16 q3[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[6] +; CHECK-NEXT: vmov.16 q3[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[7] +; CHECK-NEXT: vmov.16 q3[7], r0 +; CHECK-NEXT: vmov.u8 r0, q2[8] +; CHECK-NEXT: vmovlb.u8 q5, q3 +; CHECK-NEXT: vmov.i32 q3, #0x0 ; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q6, q3, q7 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload -; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload -; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload -; CHECK-NEXT: vpsel q0, q1, q0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 +; CHECK-NEXT: vmult.i16 q3, q5, q4 +; CHECK-NEXT: vmov.16 q4[0], r0 +; CHECK-NEXT: vmov.u8 r0, q2[9] +; CHECK-NEXT: vmov.16 q4[1], r0 +; CHECK-NEXT: vmov.u8 r0, q2[10] +; CHECK-NEXT: vmov.16 q4[2], r0 +; CHECK-NEXT: vmov.u8 r0, q2[11] +; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.u8 r0, q2[12] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r0 +; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.u8 r0, q2[13] -; CHECK-NEXT: vmov.32 q1[1], r0 +; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.u8 r0, q2[14] -; CHECK-NEXT: vmov.32 q1[2], r0 +; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vmov.u8 r0, q2[15] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q4[12] -; CHECK-NEXT: vmov.32 q7[0], r0 -; CHECK-NEXT: vmov.u8 r0, q4[13] -; CHECK-NEXT: vmov.32 q7[1], r0 -; CHECK-NEXT: vmov.u8 r0, q4[14] -; CHECK-NEXT: vmov.32 q7[2], r0 -; CHECK-NEXT: vmov.u8 r0, q4[15] -; CHECK-NEXT: vmov.32 q7[3], r0 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vand q7, q7, q3 -; CHECK-NEXT: vmov.u16 r0, q5[0] -; CHECK-NEXT: vmul.i32 q1, q7, q1 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q6, q6, q1 -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[1] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[2] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[3] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[0] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[1] -; CHECK-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[2] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[3] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q4[0] -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vmov.u8 r0, q4[1] -; CHECK-NEXT: vmov.32 q5[1], r0 -; CHECK-NEXT: vmov.u8 r0, q4[2] -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vmov.u8 r0, q4[3] -; CHECK-NEXT: vmov.32 q5[3], r0 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vmov.u16 r0, q0[0] -; CHECK-NEXT: vand q5, q5, q3 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q7, q5, q1 -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[1] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[2] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[3] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[8] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[9] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[10] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[11] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q4[8] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q4[9] -; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q4[10] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q4[11] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vmul.i32 q0, q1, q0 -; CHECK-NEXT: vmov q1, q7 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q7, q0 -; CHECK-NEXT: vadd.i32 q0, q1, q6 -; CHECK-NEXT: vaddv.u32 r0, q0 -; CHECK-NEXT: add sp, #64 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <16 x i8> %b, zeroinitializer - %xx = zext <16 x i8> %x to <16 x i32> - %yy = zext <16 x i8> %y to <16 x i32> - %m = mul <16 x i32> %xx, %yy - %s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) - ret i32 %z -} - -define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { -; CHECK-LABEL: add_v16i8_v16i32_sext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #32 -; CHECK-NEXT: sub sp, #32 -; CHECK-NEXT: vmov q3, q0 -; CHECK-NEXT: vcmp.i8 eq, q2, zr -; CHECK-NEXT: vmov.i8 q2, #0xff -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vpsel q7, q2, q0 -; CHECK-NEXT: vmov q4, q2 -; CHECK-NEXT: vmov.u8 r0, q7[0] -; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill +; CHECK-NEXT: vmov.16 q4[7], r0 +; CHECK-NEXT: vmov.u8 r0, q1[8] ; CHECK-NEXT: vmov.16 q2[0], r0 -; CHECK-NEXT: vmov.u8 r0, q7[1] +; CHECK-NEXT: vmov.u8 r0, q1[9] ; CHECK-NEXT: vmov.16 q2[1], r0 -; CHECK-NEXT: vmov.u8 r0, q7[2] +; CHECK-NEXT: vmov.u8 r0, q1[10] ; CHECK-NEXT: vmov.16 q2[2], r0 -; CHECK-NEXT: vmov.u8 r0, q7[3] +; CHECK-NEXT: vmov.u8 r0, q1[11] ; CHECK-NEXT: vmov.16 q2[3], r0 -; CHECK-NEXT: vmov.u8 r0, q7[4] -; CHECK-NEXT: vmov.16 q2[4], r0 -; CHECK-NEXT: vmov.u8 r0, q7[5] -; CHECK-NEXT: vmov.16 q2[5], r0 -; CHECK-NEXT: vmov.u8 r0, q7[6] -; CHECK-NEXT: vmov.16 q2[6], r0 -; CHECK-NEXT: vmov.u8 r0, q7[7] -; CHECK-NEXT: vmov.16 q2[7], r0 -; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill -; CHECK-NEXT: vcmp.i16 ne, q2, zr -; CHECK-NEXT: vpsel q4, q4, q0 -; CHECK-NEXT: vmov.u16 r0, q4[4] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q4[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q4[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q4[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q3[4] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u8 r0, q3[5] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u8 r0, q3[6] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u8 r0, q3[7] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q2, q2 -; CHECK-NEXT: vmovlb.s16 q5, q0 -; CHECK-NEXT: vmovlb.s16 q0, q2 -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmov q6, q2 -; CHECK-NEXT: vmov.u8 r0, q7[8] -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q6, q0, q5 -; CHECK-NEXT: vmov.16 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q7[9] -; CHECK-NEXT: vldrw.u32 q5, [sp] @ 16-byte Reload -; CHECK-NEXT: vmov.16 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q7[10] -; CHECK-NEXT: vmov.16 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q7[11] -; CHECK-NEXT: vmov.16 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q7[12] -; CHECK-NEXT: vmov.16 q0[4], r0 -; CHECK-NEXT: vmov.u8 r0, q7[13] -; CHECK-NEXT: vmov.16 q0[5], r0 -; CHECK-NEXT: vmov.u8 r0, q7[14] -; CHECK-NEXT: vmov.16 q0[6], r0 -; CHECK-NEXT: vmov.u8 r0, q7[15] -; CHECK-NEXT: vmov.16 q0[7], r0 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vmov.u16 r0, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r0 ; CHECK-NEXT: vmov.u8 r0, q1[12] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 +; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vmov.u8 r0, q1[13] -; CHECK-NEXT: vmov.32 q0[1], r0 +; CHECK-NEXT: vmov.16 q2[5], r0 ; CHECK-NEXT: vmov.u8 r0, q1[14] -; CHECK-NEXT: vmov.32 q0[2], r0 +; CHECK-NEXT: vmov.16 q2[6], r0 ; CHECK-NEXT: vmov.u8 r0, q1[15] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q3[12] -; CHECK-NEXT: vmov.32 q7[0], r0 -; CHECK-NEXT: vmov.u8 r0, q3[13] -; CHECK-NEXT: vmov.32 q7[1], r0 -; CHECK-NEXT: vmov.u8 r0, q3[14] -; CHECK-NEXT: vmov.32 q7[2], r0 -; CHECK-NEXT: vmov.u8 r0, q3[15] -; CHECK-NEXT: vmov.32 q7[3], r0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q7, q7 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmovlb.s16 q7, q7 -; CHECK-NEXT: vmov.u16 r0, q4[0] -; CHECK-NEXT: vmul.i32 q0, q7, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q6, q6, q0 -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q4[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q4[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q4[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q3[0] -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u8 r0, q3[1] -; CHECK-NEXT: vmov.32 q4[1], r0 -; CHECK-NEXT: vmov.u8 r0, q3[2] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.u8 r0, q3[3] -; CHECK-NEXT: vmov.32 q4[3], r0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q4, q4 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmov.u16 r0, q5[0] -; CHECK-NEXT: vmovlb.s16 q4, q4 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q4, q0 -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[8] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[9] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[10] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[11] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q3[8] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q3[9] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q3[10] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q3[11] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vmul.i32 q0, q1, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vadd.i32 q0, q2, q6 -; CHECK-NEXT: vaddv.u32 r0, q0 -; CHECK-NEXT: add sp, #32 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vmov.16 q2[7], r0 +; CHECK-NEXT: vmov.u8 r0, q0[8] +; CHECK-NEXT: vmov.16 q1[0], r0 +; CHECK-NEXT: vmov.u8 r0, q0[9] +; CHECK-NEXT: vmov.16 q1[1], r0 +; CHECK-NEXT: vmov.u8 r0, q0[10] +; CHECK-NEXT: vmov.16 q1[2], r0 +; CHECK-NEXT: vmov.u8 r0, q0[11] +; CHECK-NEXT: vmov.16 q1[3], r0 +; CHECK-NEXT: vmov.u8 r0, q0[12] +; CHECK-NEXT: vmov.16 q1[4], r0 +; CHECK-NEXT: vmov.u8 r0, q0[13] +; CHECK-NEXT: vmov.16 q1[5], r0 +; CHECK-NEXT: vmov.u8 r0, q0[14] +; CHECK-NEXT: vmov.16 q1[6], r0 +; CHECK-NEXT: vmov.u8 r0, q0[15] +; CHECK-NEXT: vmov.16 q1[7], r0 +; CHECK-NEXT: vmullb.u8 q0, q1, q2 +; CHECK-NEXT: vpt.i16 ne, q4, zr +; CHECK-NEXT: vaddt.i16 q3, q3, q0 +; CHECK-NEXT: vaddv.u16 r0, q3 +; CHECK-NEXT: uxth r0, r0 +; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer - %xx = sext <16 x i8> %x to <16 x i32> - %yy = sext <16 x i8> %y to <16 x i32> - %m = mul <16 x i32> %xx, %yy - %s = select <16 x i1> %c, <16 x i32> %m, <16 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %s) - ret i32 %z -} - -define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_zext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { -; CHECK-LABEL: add_v4i8_v4i32_zext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0xff -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vmul.i32 q0, q0, q1 -; CHECK-NEXT: vand q1, q2, q3 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvt.u32 r0, q0 -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <4 x i8> %b, zeroinitializer - %xx = zext <4 x i8> %x to <4 x i32> - %yy = zext <4 x i8> %y to <4 x i32> - %m = mul <4 x i32> %xx, %yy - %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) - ret i32 %z -} - -define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { -; CHECK-LABEL: add_v4i8_v4i32_sext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmul.i32 q0, q0, q1 -; CHECK-NEXT: vmov.i32 q1, #0xff -; CHECK-NEXT: vand q1, q2, q1 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvt.u32 r0, q0 -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <4 x i8> %b, zeroinitializer - %xx = sext <4 x i8> %x to <4 x i32> - %yy = sext <4 x i8> %y to <4 x i32> - %m = mul <4 x i32> %xx, %yy - %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) - ret i32 %z + %xx = zext <16 x i8> %x to <16 x i16> + %yy = zext <16 x i8> %y to <16 x i16> + %m = mul <16 x i16> %xx, %yy + %s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer + %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) + ret i16 %z } -define arm_aapcs_vfpcc zeroext i16 @add_v16i8_v16i16_zext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { -; CHECK-LABEL: add_v16i8_v16i16_zext: +define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { +; CHECK-LABEL: add_v16i8_v16i16_sext: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11} @@ -1363,135 +584,7 @@ ; CHECK-NEXT: vmov.u8 r0, q1[7] ; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.u8 r0, q0[0] -; CHECK-NEXT: vmovlb.u8 q4, q3 -; CHECK-NEXT: vmov.16 q3[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[1] -; CHECK-NEXT: vmov.16 q3[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[2] -; CHECK-NEXT: vmov.16 q3[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[3] -; CHECK-NEXT: vmov.16 q3[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[4] -; CHECK-NEXT: vmov.16 q3[4], r0 -; CHECK-NEXT: vmov.u8 r0, q0[5] -; CHECK-NEXT: vmov.16 q3[5], r0 -; CHECK-NEXT: vmov.u8 r0, q0[6] -; CHECK-NEXT: vmov.16 q3[6], r0 -; CHECK-NEXT: vmov.u8 r0, q0[7] -; CHECK-NEXT: vmov.16 q3[7], r0 -; CHECK-NEXT: vmov.u8 r0, q2[8] -; CHECK-NEXT: vmovlb.u8 q5, q3 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i16 q3, q5, q4 -; CHECK-NEXT: vmov.16 q4[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[9] -; CHECK-NEXT: vmov.16 q4[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[10] -; CHECK-NEXT: vmov.16 q4[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[11] -; CHECK-NEXT: vmov.16 q4[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[12] -; CHECK-NEXT: vmov.16 q4[4], r0 -; CHECK-NEXT: vmov.u8 r0, q2[13] -; CHECK-NEXT: vmov.16 q4[5], r0 -; CHECK-NEXT: vmov.u8 r0, q2[14] -; CHECK-NEXT: vmov.16 q4[6], r0 -; CHECK-NEXT: vmov.u8 r0, q2[15] -; CHECK-NEXT: vmov.16 q4[7], r0 -; CHECK-NEXT: vmov.u8 r0, q1[8] -; CHECK-NEXT: vmov.16 q2[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[9] -; CHECK-NEXT: vmov.16 q2[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[10] -; CHECK-NEXT: vmov.16 q2[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[11] -; CHECK-NEXT: vmov.16 q2[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[12] -; CHECK-NEXT: vmov.16 q2[4], r0 -; CHECK-NEXT: vmov.u8 r0, q1[13] -; CHECK-NEXT: vmov.16 q2[5], r0 -; CHECK-NEXT: vmov.u8 r0, q1[14] -; CHECK-NEXT: vmov.16 q2[6], r0 -; CHECK-NEXT: vmov.u8 r0, q1[15] -; CHECK-NEXT: vmov.16 q2[7], r0 -; CHECK-NEXT: vmov.u8 r0, q0[8] -; CHECK-NEXT: vmov.16 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[9] -; CHECK-NEXT: vmov.16 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[10] -; CHECK-NEXT: vmov.16 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[11] -; CHECK-NEXT: vmov.16 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[12] -; CHECK-NEXT: vmov.16 q1[4], r0 -; CHECK-NEXT: vmov.u8 r0, q0[13] -; CHECK-NEXT: vmov.16 q1[5], r0 -; CHECK-NEXT: vmov.u8 r0, q0[14] -; CHECK-NEXT: vmov.16 q1[6], r0 -; CHECK-NEXT: vmov.u8 r0, q0[15] -; CHECK-NEXT: vmov.16 q1[7], r0 -; CHECK-NEXT: vmullb.u8 q0, q1, q2 -; CHECK-NEXT: vpt.i16 ne, q4, zr -; CHECK-NEXT: vaddt.i16 q3, q3, q0 -; CHECK-NEXT: vaddv.u16 r0, q3 -; CHECK-NEXT: uxth r0, r0 -; CHECK-NEXT: vpop {d8, d9, d10, d11} -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <16 x i8> %b, zeroinitializer - %xx = zext <16 x i8> %x to <16 x i16> - %yy = zext <16 x i8> %y to <16 x i16> - %m = mul <16 x i16> %xx, %yy - %s = select <16 x i1> %c, <16 x i16> %m, <16 x i16> zeroinitializer - %z = call i16 @llvm.experimental.vector.reduce.add.v16i16(<16 x i16> %s) - ret i16 %z -} - -define arm_aapcs_vfpcc signext i16 @add_v16i8_v16i16_sext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { -; CHECK-LABEL: add_v16i8_v16i16_sext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vcmp.i8 eq, q2, zr -; CHECK-NEXT: vmov.i8 q2, #0x0 -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vpsel q2, q3, q2 -; CHECK-NEXT: vmov.u8 r0, q2[0] -; CHECK-NEXT: vmov.16 q3[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[1] -; CHECK-NEXT: vmov.16 q3[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[2] -; CHECK-NEXT: vmov.16 q3[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[3] -; CHECK-NEXT: vmov.16 q3[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[4] -; CHECK-NEXT: vmov.16 q3[4], r0 -; CHECK-NEXT: vmov.u8 r0, q2[5] -; CHECK-NEXT: vmov.16 q3[5], r0 -; CHECK-NEXT: vmov.u8 r0, q2[6] -; CHECK-NEXT: vmov.16 q3[6], r0 -; CHECK-NEXT: vmov.u8 r0, q2[7] -; CHECK-NEXT: vmov.16 q3[7], r0 -; CHECK-NEXT: vmov.u8 r0, q1[0] -; CHECK-NEXT: vcmp.i16 ne, q3, zr -; CHECK-NEXT: vmov.16 q3[0], r0 -; CHECK-NEXT: vmov.u8 r0, q1[1] -; CHECK-NEXT: vmov.16 q3[1], r0 -; CHECK-NEXT: vmov.u8 r0, q1[2] -; CHECK-NEXT: vmov.16 q3[2], r0 -; CHECK-NEXT: vmov.u8 r0, q1[3] -; CHECK-NEXT: vmov.16 q3[3], r0 -; CHECK-NEXT: vmov.u8 r0, q1[4] -; CHECK-NEXT: vmov.16 q3[4], r0 -; CHECK-NEXT: vmov.u8 r0, q1[5] -; CHECK-NEXT: vmov.16 q3[5], r0 -; CHECK-NEXT: vmov.u8 r0, q1[6] -; CHECK-NEXT: vmov.16 q3[6], r0 -; CHECK-NEXT: vmov.u8 r0, q1[7] -; CHECK-NEXT: vmov.16 q3[7], r0 -; CHECK-NEXT: vmov.u8 r0, q0[0] -; CHECK-NEXT: vmovlb.s8 q4, q3 +; CHECK-NEXT: vmovlb.s8 q4, q3 ; CHECK-NEXT: vmov.16 q3[0], r0 ; CHECK-NEXT: vmov.u8 r0, q0[1] ; CHECK-NEXT: vmov.16 q3[1], r0 @@ -1579,10 +672,11 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.u8 q0, q0, q1 -; CHECK-NEXT: vmovlb.u8 q1, q2 -; CHECK-NEXT: vpt.i16 eq, q1, zr -; CHECK-NEXT: vaddvt.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vmovlb.u8 q0, q0 +; CHECK-NEXT: vmovlb.u8 q2, q2 +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavt.u16 r0, q0, q1 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1598,10 +692,11 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.s8 q0, q0, q1 -; CHECK-NEXT: vmovlb.u8 q1, q2 -; CHECK-NEXT: vpt.i16 eq, q1, zr -; CHECK-NEXT: vaddvt.u16 r0, q0 +; CHECK-NEXT: vmovlb.s8 q1, q1 +; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmovlb.u8 q2, q2 +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavt.u16 r0, q0, q1 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1617,9 +712,8 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i8: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i8 q0, q0, q1 ; CHECK-NEXT: vpt.i8 eq, q2, zr -; CHECK-NEXT: vaddvt.u8 r0, q0 +; CHECK-NEXT: vmlavt.u8 r0, q0, q1 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: @@ -2544,9 +1638,8 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i32 %a) { ; CHECK-LABEL: add_v4i32_v4i32_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i32 q0, q0, q1 ; CHECK-NEXT: vpt.i32 eq, q2, zr -; CHECK-NEXT: vaddvat.u32 r0, q0 +; CHECK-NEXT: vmlavat.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -2560,58 +1653,9 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i64 %a) { ; CHECK-LABEL: add_v4i32_v4i64_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r7, lr} -; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.f32 s12, s4 -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: vmov.f32 s16, s0 -; CHECK-NEXT: vmov.f32 s14, s5 -; CHECK-NEXT: vmov.f32 s18, s1 -; CHECK-NEXT: vmullb.u32 q5, q4, q3 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[0], r3 -; CHECK-NEXT: vmov.32 q2[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[2], r3 -; CHECK-NEXT: vmov.32 q2[3], r3 -; CHECK-NEXT: vand q2, q5, q2 -; CHECK-NEXT: vmov r3, s10 -; CHECK-NEXT: vmov r4, s8 -; CHECK-NEXT: vmov r12, s11 -; CHECK-NEXT: vmov lr, s9 -; CHECK-NEXT: vmov.f32 s8, s6 -; CHECK-NEXT: vmov.f32 s10, s7 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vmullb.u32 q0, q1, q2 -; CHECK-NEXT: adds r5, r4, r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r2, r2, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r4, lr, r12 -; CHECK-NEXT: vmov.32 q1[2], r2 -; CHECK-NEXT: vmov.32 q1[3], r2 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: adds r3, r3, r5 -; CHECK-NEXT: vmov r5, s3 -; CHECK-NEXT: adcs r2, r4 -; CHECK-NEXT: vmov r4, s2 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adcs r2, r5 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: vpop {d8, d9, d10, d11} -; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlalvat.u32 r0, r1, q0, q1 +; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer %xx = zext <4 x i32> %x to <4 x i64> @@ -2626,67 +1670,9 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i64 %a) { ; CHECK-LABEL: add_v4i32_v4i64_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r7, lr} -; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.f32 s16, s4 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.f32 s20, s0 -; CHECK-NEXT: vmov.f32 s18, s5 -; CHECK-NEXT: vmov.f32 s22, s1 -; CHECK-NEXT: vmov r2, s16 -; CHECK-NEXT: vmov r3, s20 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov r2, s18 -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: vmov r3, s22 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: vmov.32 q3[3], r3 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[0], r3 -; CHECK-NEXT: vmov.32 q2[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q2[2], r3 -; CHECK-NEXT: vmov.32 q2[3], r3 -; CHECK-NEXT: vand q2, q3, q2 -; CHECK-NEXT: vmov r3, s10 -; CHECK-NEXT: vmov r4, s8 -; CHECK-NEXT: vmov r12, s11 -; CHECK-NEXT: vmov lr, s9 -; CHECK-NEXT: vmov.f32 s8, s6 -; CHECK-NEXT: vmov.f32 s10, s7 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vmullb.s32 q0, q1, q2 -; CHECK-NEXT: adds r5, r4, r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r2, r2, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r4, lr, r12 -; CHECK-NEXT: vmov.32 q1[2], r2 -; CHECK-NEXT: vmov.32 q1[3], r2 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: adds r3, r3, r5 -; CHECK-NEXT: vmov r5, s3 -; CHECK-NEXT: adcs r2, r4 -; CHECK-NEXT: vmov r4, s2 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adcs r2, r5 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: vpop {d8, d9, d10, d11} -; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlalvat.s32 r0, r1, q0, q1 +; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer %xx = sext <4 x i32> %x to <4 x i64> @@ -2783,71 +1769,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v8i16_v8i32_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: vmov.u16 r1, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[0] -; CHECK-NEXT: vmovlb.u16 q4, q3 -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q2[4] -; CHECK-NEXT: vmovlb.u16 q5, q3 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q3, q5, q4 -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[5] -; CHECK-NEXT: vmov.32 q4[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[6] -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[7] -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[4] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[5] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[6] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[7] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmullb.u16 q0, q1, q2 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vaddva.u32 r0, q3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavat.u16 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -2863,488 +1786,99 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v8i16_v8i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11} -; CHECK-NEXT: vpush {d8, d9, d10, d11} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: vmov.u16 r1, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[0] -; CHECK-NEXT: vmovlb.s16 q4, q3 -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[3] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q2[4] -; CHECK-NEXT: vmovlb.s16 q5, q3 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q3, q5, q4 -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[5] -; CHECK-NEXT: vmov.32 q4[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[6] -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[7] -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[4] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[5] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[6] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[7] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmullb.s16 q0, q1, q2 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vaddva.u32 r0, q3 -; CHECK-NEXT: vpop {d8, d9, d10, d11} -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <8 x i16> %b, zeroinitializer - %xx = sext <8 x i16> %x to <8 x i32> - %yy = sext <8 x i16> %y to <8 x i32> - %m = mul <8 x i32> %xx, %yy - %s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) - %r = add i32 %z, %a - ret i32 %r -} - -define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { -; CHECK-LABEL: add_v4i16_v4i32_acc_zext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.u16 q0, q0, q1 -; CHECK-NEXT: vmovlb.u16 q1, q2 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvat.u32 r0, q0 +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavat.s16 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <8 x i16> %b, zeroinitializer + %xx = sext <8 x i16> %x to <8 x i32> + %yy = sext <8 x i16> %y to <8 x i32> + %m = mul <8 x i32> %xx, %yy + %s = select <8 x i1> %c, <8 x i32> %m, <8 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %s) + %r = add i32 %z, %a + ret i32 %r +} + +define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { +; CHECK-LABEL: add_v4i16_v4i32_acc_zext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmovlb.u16 q1, q1 +; CHECK-NEXT: vmovlb.u16 q0, q0 +; CHECK-NEXT: vmovlb.u16 q2, q2 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavat.u32 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <4 x i16> %b, zeroinitializer + %xx = zext <4 x i16> %x to <4 x i32> + %yy = zext <4 x i16> %y to <4 x i32> + %m = mul <4 x i32> %xx, %yy + %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) + %r = add i32 %z, %a + ret i32 %r +} + +define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { +; CHECK-LABEL: add_v4i16_v4i32_acc_sext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmovlb.s16 q1, q1 +; CHECK-NEXT: vmovlb.s16 q0, q0 +; CHECK-NEXT: vmovlb.u16 q2, q2 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavat.u32 r0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <4 x i16> %b, zeroinitializer + %xx = sext <4 x i16> %x to <4 x i32> + %yy = sext <4 x i16> %y to <4 x i32> + %m = mul <4 x i32> %xx, %yy + %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer + %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) + %r = add i32 %z, %a + ret i32 %r +} + +define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) { +; CHECK-LABEL: add_v8i16_v8i16_acc: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavat.u16 r0, q0, q1 +; CHECK-NEXT: uxth r0, r0 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <8 x i16> %b, zeroinitializer + %m = mul <8 x i16> %x, %y + %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer + %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) + %r = add i16 %z, %a + ret i16 %r +} + +define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_zext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) { +; CHECK-LABEL: add_v8i16_v8i64_acc_zext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlalvat.u16 r0, r1, q0, q1 +; CHECK-NEXT: bx lr +entry: + %c = icmp eq <8 x i16> %b, zeroinitializer + %xx = zext <8 x i16> %x to <8 x i64> + %yy = zext <8 x i16> %y to <8 x i64> + %m = mul <8 x i64> %xx, %yy + %s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer + %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) + %r = add i64 %z, %a + ret i64 %r +} + +define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) { +; CHECK-LABEL: add_v8i16_v8i64_acc_sext: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlalvat.s16 r0, r1, q0, q1 ; CHECK-NEXT: bx lr -entry: - %c = icmp eq <4 x i16> %b, zeroinitializer - %xx = zext <4 x i16> %x to <4 x i32> - %yy = zext <4 x i16> %y to <4 x i32> - %m = mul <4 x i32> %xx, %yy - %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) - %r = add i32 %z, %a - ret i32 %r -} - -define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { -; CHECK-LABEL: add_v4i16_v4i32_acc_sext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.s16 q0, q0, q1 -; CHECK-NEXT: vmovlb.u16 q1, q2 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvat.u32 r0, q0 -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <4 x i16> %b, zeroinitializer - %xx = sext <4 x i16> %x to <4 x i32> - %yy = sext <4 x i16> %y to <4 x i32> - %m = mul <4 x i32> %xx, %yy - %s = select <4 x i1> %c, <4 x i32> %m, <4 x i32> zeroinitializer - %z = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %s) - %r = add i32 %z, %a - ret i32 %r -} - -define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) { -; CHECK-LABEL: add_v8i16_v8i16_acc: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i16 q0, q0, q1 -; CHECK-NEXT: vpt.i16 eq, q2, zr -; CHECK-NEXT: vaddvat.u16 r0, q0 -; CHECK-NEXT: uxth r0, r0 -; CHECK-NEXT: bx lr -entry: - %c = icmp eq <8 x i16> %b, zeroinitializer - %m = mul <8 x i16> %x, %y - %s = select <8 x i1> %c, <8 x i16> %m, <8 x i16> zeroinitializer - %z = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %s) - %r = add i16 %z, %a - ret i16 %r -} - -define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_zext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) { -; CHECK-LABEL: add_v8i16_v8i64_acc_zext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r6, lr} -; CHECK-NEXT: push {r4, r5, r6, lr} -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q3, q4, q3 -; CHECK-NEXT: vmov.u16 r2, q3[0] -; CHECK-NEXT: vmov.32 q2[0], r2 -; CHECK-NEXT: vmov.u16 r2, q3[1] -; CHECK-NEXT: vmov.32 q2[1], r2 -; CHECK-NEXT: vmov.u16 r2, q3[2] -; CHECK-NEXT: vmov.32 q2[2], r2 -; CHECK-NEXT: vmov.u16 r2, q3[3] -; CHECK-NEXT: vmov.32 q2[3], r2 -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.i64 q2, #0xffff -; CHECK-NEXT: vmrs lr, p0 -; CHECK-NEXT: and r3, lr, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q4[0], r3 -; CHECK-NEXT: vmov.32 q4[1], r3 -; CHECK-NEXT: ubfx r3, lr, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q4[2], r3 -; CHECK-NEXT: vmov.32 q4[3], r3 -; CHECK-NEXT: vmov.u16 r3, q1[0] -; CHECK-NEXT: vmov.32 q5[0], r3 -; CHECK-NEXT: vmov.u16 r3, q1[1] -; CHECK-NEXT: vmov.32 q5[2], r3 -; CHECK-NEXT: vmov.u16 r3, q0[0] -; CHECK-NEXT: vmov.32 q6[0], r3 -; CHECK-NEXT: vmov.u16 r3, q0[1] -; CHECK-NEXT: vmov.32 q6[2], r3 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vand q6, q6, q2 -; CHECK-NEXT: vmov r12, s20 -; CHECK-NEXT: vmov r3, s24 -; CHECK-NEXT: umull r3, r2, r3, r12 -; CHECK-NEXT: vmov.32 q7[0], r3 -; CHECK-NEXT: vmov r3, s26 -; CHECK-NEXT: vmov.32 q7[1], r2 -; CHECK-NEXT: vmov r2, s22 -; CHECK-NEXT: umull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q7[2], r2 -; CHECK-NEXT: vmov.32 q7[3], r3 -; CHECK-NEXT: vand q4, q7, q4 -; CHECK-NEXT: vmov r4, s18 -; CHECK-NEXT: vmov r2, s16 -; CHECK-NEXT: vmov r12, s19 -; CHECK-NEXT: vmov r3, s17 -; CHECK-NEXT: adds r4, r4, r2 -; CHECK-NEXT: ubfx r2, lr, #8, #1 -; CHECK-NEXT: rsb.w r2, r2, #0 -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: adc.w r12, r12, r3 -; CHECK-NEXT: vmov.32 q4[1], r2 -; CHECK-NEXT: ubfx r2, lr, #12, #1 -; CHECK-NEXT: rsbs r2, r2, #0 -; CHECK-NEXT: vmov.u16 r3, q0[2] -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vmov.32 q6[0], r3 -; CHECK-NEXT: vmov.32 q4[3], r2 -; CHECK-NEXT: vmov.u16 r2, q1[2] -; CHECK-NEXT: vmov.32 q5[0], r2 -; CHECK-NEXT: vmov.u16 r2, q1[3] -; CHECK-NEXT: vmov.u16 r3, q0[3] -; CHECK-NEXT: vmov.32 q5[2], r2 -; CHECK-NEXT: vmov.32 q6[2], r3 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vand q6, q6, q2 -; CHECK-NEXT: vmov r2, s20 -; CHECK-NEXT: vmov r3, s24 -; CHECK-NEXT: umull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q7[0], r2 -; CHECK-NEXT: vmov r2, s22 -; CHECK-NEXT: vmov.32 q7[1], r3 -; CHECK-NEXT: vmov r3, s26 -; CHECK-NEXT: umull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q7[2], r2 -; CHECK-NEXT: vmov.32 q7[3], r3 -; CHECK-NEXT: vand q4, q7, q4 -; CHECK-NEXT: vmov r3, s16 -; CHECK-NEXT: vmov r2, s17 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: vmov r4, s19 -; CHECK-NEXT: adc.w lr, r12, r2 -; CHECK-NEXT: vmov r2, s18 -; CHECK-NEXT: adds.w r12, r3, r2 -; CHECK-NEXT: vmov.u16 r2, q3[4] -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: vmov.u16 r2, q3[5] -; CHECK-NEXT: vmov.32 q4[1], r2 -; CHECK-NEXT: vmov.u16 r2, q3[6] -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vmov.u16 r2, q3[7] -; CHECK-NEXT: vmov.32 q4[3], r2 -; CHECK-NEXT: adc.w lr, lr, r4 -; CHECK-NEXT: vcmp.i32 ne, q4, zr -; CHECK-NEXT: vmov.u16 r3, q0[4] -; CHECK-NEXT: vmrs r6, p0 -; CHECK-NEXT: vmov.32 q5[0], r3 -; CHECK-NEXT: vmov.u16 r3, q0[5] -; CHECK-NEXT: vmov.32 q5[2], r3 -; CHECK-NEXT: vand q5, q5, q2 -; CHECK-NEXT: vmov r3, s20 -; CHECK-NEXT: and r4, r6, #1 -; CHECK-NEXT: rsbs r4, r4, #0 -; CHECK-NEXT: vmov.32 q3[0], r4 -; CHECK-NEXT: vmov.32 q3[1], r4 -; CHECK-NEXT: ubfx r4, r6, #4, #1 -; CHECK-NEXT: rsbs r4, r4, #0 -; CHECK-NEXT: vmov.32 q3[2], r4 -; CHECK-NEXT: vmov.32 q3[3], r4 -; CHECK-NEXT: vmov.u16 r4, q1[4] -; CHECK-NEXT: vmov.32 q4[0], r4 -; CHECK-NEXT: vmov.u16 r4, q1[5] -; CHECK-NEXT: vmov.32 q4[2], r4 -; CHECK-NEXT: vand q4, q4, q2 -; CHECK-NEXT: vmov r4, s16 -; CHECK-NEXT: umull r3, r4, r3, r4 -; CHECK-NEXT: vmov.32 q6[0], r3 -; CHECK-NEXT: vmov r3, s18 -; CHECK-NEXT: vmov.32 q6[1], r4 -; CHECK-NEXT: vmov r4, s22 -; CHECK-NEXT: umull r3, r4, r4, r3 -; CHECK-NEXT: vmov.32 q6[2], r3 -; CHECK-NEXT: vmov.32 q6[3], r4 -; CHECK-NEXT: vand q3, q6, q3 -; CHECK-NEXT: vmov r4, s12 -; CHECK-NEXT: vmov r3, s13 -; CHECK-NEXT: vmov r5, s14 -; CHECK-NEXT: vmov r2, s15 -; CHECK-NEXT: adds.w r4, r4, r12 -; CHECK-NEXT: adc.w r3, r3, lr -; CHECK-NEXT: adds r4, r4, r5 -; CHECK-NEXT: adc.w r12, r3, r2 -; CHECK-NEXT: ubfx r2, r6, #8, #1 -; CHECK-NEXT: rsbs r2, r2, #0 -; CHECK-NEXT: vmov.u16 r3, q0[6] -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov.32 q3[1], r2 -; CHECK-NEXT: ubfx r2, r6, #12, #1 -; CHECK-NEXT: rsbs r2, r2, #0 -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: vmov.u16 r2, q1[6] -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: vmov.u16 r2, q1[7] -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vand q1, q4, q2 -; CHECK-NEXT: vmov.32 q4[0], r3 -; CHECK-NEXT: vmov.u16 r3, q0[7] -; CHECK-NEXT: vmov r2, s4 -; CHECK-NEXT: vmov.32 q4[2], r3 -; CHECK-NEXT: vand q0, q4, q2 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: umull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q2[0], r2 -; CHECK-NEXT: vmov r2, s6 -; CHECK-NEXT: vmov.32 q2[1], r3 -; CHECK-NEXT: vmov r3, s2 -; CHECK-NEXT: umull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q2[2], r2 -; CHECK-NEXT: vmov.32 q2[3], r3 -; CHECK-NEXT: vand q0, q2, q3 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: vmov r5, s2 -; CHECK-NEXT: vmov r6, s3 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: adds r3, r3, r5 -; CHECK-NEXT: adcs r2, r6 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: pop {r4, r5, r6, pc} -entry: - %c = icmp eq <8 x i16> %b, zeroinitializer - %xx = zext <8 x i16> %x to <8 x i64> - %yy = zext <8 x i16> %y to <8 x i64> - %m = mul <8 x i64> %xx, %yy - %s = select <8 x i1> %c, <8 x i64> %m, <8 x i64> zeroinitializer - %z = call i64 @llvm.experimental.vector.reduce.add.v8i64(<8 x i64> %s) - %r = add i64 %z, %a - ret i64 %r -} - -define arm_aapcs_vfpcc i64 @add_v8i16_v8i64_acc_sext(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i64 %a) { -; CHECK-LABEL: add_v8i16_v8i64_acc_sext: -; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r7, lr} -; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: .vsave {d8, d9} -; CHECK-NEXT: vpush {d8, d9} -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q4, #0xff -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vpsel q2, q4, q3 -; CHECK-NEXT: vmov.u16 r2, q2[0] -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov.u16 r2, q2[1] -; CHECK-NEXT: vmov.32 q3[1], r2 -; CHECK-NEXT: vmov.u16 r2, q2[2] -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmov.u16 r2, q2[3] -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q3[0], r3 -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q3[2], r3 -; CHECK-NEXT: vmov.32 q3[3], r3 -; CHECK-NEXT: vmov.u16 r3, q1[0] -; CHECK-NEXT: sxth.w r12, r3 -; CHECK-NEXT: vmov.u16 r3, q0[0] -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r3, r12, r3, r12 -; CHECK-NEXT: vmov.32 q4[0], r3 -; CHECK-NEXT: vmov.u16 r3, q1[1] -; CHECK-NEXT: vmov.32 q4[1], r12 -; CHECK-NEXT: sxth.w r12, r3 -; CHECK-NEXT: vmov.u16 r3, q0[1] -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r3, r12, r3, r12 -; CHECK-NEXT: vmov.32 q4[2], r3 -; CHECK-NEXT: vmov.32 q4[3], r12 -; CHECK-NEXT: vand q3, q4, q3 -; CHECK-NEXT: vmov r3, s14 -; CHECK-NEXT: vmov r4, s12 -; CHECK-NEXT: vmov r12, s15 -; CHECK-NEXT: vmov r5, s13 -; CHECK-NEXT: adds.w lr, r4, r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q3[0], r3 -; CHECK-NEXT: rsb.w r2, r2, #0 -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: vmov.u16 r2, q1[2] -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: adc.w r12, r12, r5 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q4[0], r2 -; CHECK-NEXT: vmov.u16 r2, q1[3] -; CHECK-NEXT: vmov.32 q4[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[3] -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q4[2], r2 -; CHECK-NEXT: vmov.32 q4[3], r3 -; CHECK-NEXT: vand q3, q4, q3 -; CHECK-NEXT: vmov r3, s12 -; CHECK-NEXT: vmov r2, s13 -; CHECK-NEXT: vmov r4, s14 -; CHECK-NEXT: vmov r5, s15 -; CHECK-NEXT: adds.w r3, r3, lr -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: adds.w r12, r3, r4 -; CHECK-NEXT: vmov.u16 r4, q0[4] -; CHECK-NEXT: adc.w r3, r2, r5 -; CHECK-NEXT: vmov.u16 r2, q2[4] -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov.u16 r2, q2[5] -; CHECK-NEXT: vmov.32 q3[1], r2 -; CHECK-NEXT: vmov.u16 r2, q2[6] -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmov.u16 r2, q2[7] -; CHECK-NEXT: vmov.32 q3[3], r2 -; CHECK-NEXT: sxth r4, r4 -; CHECK-NEXT: vcmp.i32 ne, q3, zr -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r5, r2, #1 -; CHECK-NEXT: rsbs r5, r5, #0 -; CHECK-NEXT: vmov.32 q2[0], r5 -; CHECK-NEXT: vmov.32 q2[1], r5 -; CHECK-NEXT: ubfx r5, r2, #4, #1 -; CHECK-NEXT: rsbs r5, r5, #0 -; CHECK-NEXT: vmov.32 q2[2], r5 -; CHECK-NEXT: vmov.32 q2[3], r5 -; CHECK-NEXT: vmov.u16 r5, q1[4] -; CHECK-NEXT: sxth r5, r5 -; CHECK-NEXT: smull r5, r4, r4, r5 -; CHECK-NEXT: vmov.32 q3[0], r5 -; CHECK-NEXT: vmov.u16 r5, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r4 -; CHECK-NEXT: vmov.u16 r4, q0[5] -; CHECK-NEXT: sxth r5, r5 -; CHECK-NEXT: sxth r4, r4 -; CHECK-NEXT: smull r5, r4, r4, r5 -; CHECK-NEXT: vmov.32 q3[2], r5 -; CHECK-NEXT: vmov.32 q3[3], r4 -; CHECK-NEXT: vand q2, q3, q2 -; CHECK-NEXT: vmov r4, s8 -; CHECK-NEXT: vmov r5, s9 -; CHECK-NEXT: adds.w r12, r12, r4 -; CHECK-NEXT: vmov r4, s10 -; CHECK-NEXT: adcs r5, r3 -; CHECK-NEXT: vmov r3, s11 -; CHECK-NEXT: adds.w r4, r4, r12 -; CHECK-NEXT: adc.w r12, r5, r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q2[0], r3 -; CHECK-NEXT: rsbs r2, r2, #0 -; CHECK-NEXT: vmov.32 q2[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[6] -; CHECK-NEXT: vmov.32 q2[2], r2 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: vmov.32 q2[3], r2 -; CHECK-NEXT: vmov.u16 r2, q1[6] -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q3[0], r2 -; CHECK-NEXT: vmov.u16 r2, q1[7] -; CHECK-NEXT: vmov.32 q3[1], r3 -; CHECK-NEXT: vmov.u16 r3, q0[7] -; CHECK-NEXT: sxth r2, r2 -; CHECK-NEXT: sxth r3, r3 -; CHECK-NEXT: smull r2, r3, r3, r2 -; CHECK-NEXT: vmov.32 q3[2], r2 -; CHECK-NEXT: vmov.32 q3[3], r3 -; CHECK-NEXT: vand q0, q3, q2 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: vmov r5, s3 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: vmov r4, s2 -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adcs r2, r5 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: vpop {d8, d9} -; CHECK-NEXT: pop {r4, r5, r7, pc} entry: %c = icmp eq <8 x i16> %b, zeroinitializer %xx = sext <8 x i16> %x to <8 x i64> @@ -3472,187 +2006,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v16i8_v16i32_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #64 -; CHECK-NEXT: sub sp, #64 -; CHECK-NEXT: vmov q3, q2 -; CHECK-NEXT: vmov q4, q0 -; CHECK-NEXT: vcmp.i8 eq, q3, zr -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vmov q2, q1 -; CHECK-NEXT: vpsel q1, q3, q0 -; CHECK-NEXT: vmov q5, q3 -; CHECK-NEXT: vmov.u8 r1, q1[0] -; CHECK-NEXT: vstrw.32 q3, [sp, #16] @ 16-byte Spill -; CHECK-NEXT: vmov.16 q3[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[1] -; CHECK-NEXT: vmov.16 q3[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[2] -; CHECK-NEXT: vmov.16 q3[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[3] -; CHECK-NEXT: vmov.16 q3[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[4] -; CHECK-NEXT: vmov.16 q3[4], r1 -; CHECK-NEXT: vmov.u8 r1, q1[5] -; CHECK-NEXT: vmov.16 q3[5], r1 -; CHECK-NEXT: vmov.u8 r1, q1[6] -; CHECK-NEXT: vmov.16 q3[6], r1 -; CHECK-NEXT: vmov.u8 r1, q1[7] -; CHECK-NEXT: vmov.16 q3[7], r1 -; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill -; CHECK-NEXT: vcmp.i16 ne, q3, zr -; CHECK-NEXT: vmov.i32 q3, #0xff -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill -; CHECK-NEXT: vmov.u16 r1, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q4[4] -; CHECK-NEXT: vmov.32 q6[0], r1 -; CHECK-NEXT: vmov.u8 r1, q4[5] -; CHECK-NEXT: vmov.32 q6[1], r1 -; CHECK-NEXT: vmov.u8 r1, q4[6] -; CHECK-NEXT: vmov.32 q6[2], r1 -; CHECK-NEXT: vmov.u8 r1, q4[7] -; CHECK-NEXT: vmov.32 q6[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[8] -; CHECK-NEXT: vand q7, q0, q3 -; CHECK-NEXT: vmov.16 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[9] -; CHECK-NEXT: vand q3, q6, q3 -; CHECK-NEXT: vmov.16 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[10] -; CHECK-NEXT: vmov.16 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[11] -; CHECK-NEXT: vmov.16 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[12] -; CHECK-NEXT: vmov.16 q0[4], r1 -; CHECK-NEXT: vmov.u8 r1, q1[13] -; CHECK-NEXT: vmov.16 q0[5], r1 -; CHECK-NEXT: vmov.u8 r1, q1[14] -; CHECK-NEXT: vmov.16 q0[6], r1 -; CHECK-NEXT: vmov.u8 r1, q1[15] -; CHECK-NEXT: vmov.i32 q6, #0x0 -; CHECK-NEXT: vmov.16 q0[7], r1 -; CHECK-NEXT: vstrw.32 q6, [sp, #48] @ 16-byte Spill -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q6, q3, q7 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload -; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload -; CHECK-NEXT: vldrw.u32 q3, [sp] @ 16-byte Reload -; CHECK-NEXT: vpsel q0, q1, q0 -; CHECK-NEXT: vmov.u16 r1, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[12] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[13] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[14] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[15] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q4[12] -; CHECK-NEXT: vmov.32 q7[0], r1 -; CHECK-NEXT: vmov.u8 r1, q4[13] -; CHECK-NEXT: vmov.32 q7[1], r1 -; CHECK-NEXT: vmov.u8 r1, q4[14] -; CHECK-NEXT: vmov.32 q7[2], r1 -; CHECK-NEXT: vmov.u8 r1, q4[15] -; CHECK-NEXT: vmov.32 q7[3], r1 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vand q7, q7, q3 -; CHECK-NEXT: vmov.u16 r1, q5[0] -; CHECK-NEXT: vmul.i32 q1, q7, q1 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q6, q6, q1 -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[1] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[2] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[3] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[0] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[1] -; CHECK-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[2] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[3] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q4[0] -; CHECK-NEXT: vmov.32 q5[0], r1 -; CHECK-NEXT: vmov.u8 r1, q4[1] -; CHECK-NEXT: vmov.32 q5[1], r1 -; CHECK-NEXT: vmov.u8 r1, q4[2] -; CHECK-NEXT: vmov.32 q5[2], r1 -; CHECK-NEXT: vmov.u8 r1, q4[3] -; CHECK-NEXT: vmov.32 q5[3], r1 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vmov.u16 r1, q0[0] -; CHECK-NEXT: vand q5, q5, q3 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q7, q5, q1 -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[1] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[2] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[3] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[8] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[9] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[10] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[11] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q4[8] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q4[9] -; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q4[10] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q4[11] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vmul.i32 q0, q1, q0 -; CHECK-NEXT: vmov q1, q7 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q7, q0 -; CHECK-NEXT: vadd.i32 q0, q1, q6 -; CHECK-NEXT: vaddva.u32 r0, q0 -; CHECK-NEXT: add sp, #64 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q2, zr +; CHECK-NEXT: vmlavat.u8 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -3668,188 +2023,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v16i8_v16i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #32 -; CHECK-NEXT: sub sp, #32 -; CHECK-NEXT: vmov q3, q0 -; CHECK-NEXT: vcmp.i8 eq, q2, zr -; CHECK-NEXT: vmov.i8 q2, #0xff -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vpsel q7, q2, q0 -; CHECK-NEXT: vmov q4, q2 -; CHECK-NEXT: vmov.u8 r1, q7[0] -; CHECK-NEXT: vstrw.32 q2, [sp] @ 16-byte Spill -; CHECK-NEXT: vmov.16 q2[0], r1 -; CHECK-NEXT: vmov.u8 r1, q7[1] -; CHECK-NEXT: vmov.16 q2[1], r1 -; CHECK-NEXT: vmov.u8 r1, q7[2] -; CHECK-NEXT: vmov.16 q2[2], r1 -; CHECK-NEXT: vmov.u8 r1, q7[3] -; CHECK-NEXT: vmov.16 q2[3], r1 -; CHECK-NEXT: vmov.u8 r1, q7[4] -; CHECK-NEXT: vmov.16 q2[4], r1 -; CHECK-NEXT: vmov.u8 r1, q7[5] -; CHECK-NEXT: vmov.16 q2[5], r1 -; CHECK-NEXT: vmov.u8 r1, q7[6] -; CHECK-NEXT: vmov.16 q2[6], r1 -; CHECK-NEXT: vmov.u8 r1, q7[7] -; CHECK-NEXT: vmov.16 q2[7], r1 -; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill -; CHECK-NEXT: vcmp.i16 ne, q2, zr -; CHECK-NEXT: vpsel q4, q4, q0 -; CHECK-NEXT: vmov.u16 r1, q4[4] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q4[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q4[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q4[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q3[4] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u8 r1, q3[5] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u8 r1, q3[6] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u8 r1, q3[7] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q2, q2 -; CHECK-NEXT: vmovlb.s16 q5, q0 -; CHECK-NEXT: vmovlb.s16 q0, q2 -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmov q6, q2 -; CHECK-NEXT: vmov.u8 r1, q7[8] -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q6, q0, q5 -; CHECK-NEXT: vmov.16 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q7[9] -; CHECK-NEXT: vldrw.u32 q5, [sp] @ 16-byte Reload -; CHECK-NEXT: vmov.16 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q7[10] -; CHECK-NEXT: vmov.16 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q7[11] -; CHECK-NEXT: vmov.16 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q7[12] -; CHECK-NEXT: vmov.16 q0[4], r1 -; CHECK-NEXT: vmov.u8 r1, q7[13] -; CHECK-NEXT: vmov.16 q0[5], r1 -; CHECK-NEXT: vmov.u8 r1, q7[14] -; CHECK-NEXT: vmov.16 q0[6], r1 -; CHECK-NEXT: vmov.u8 r1, q7[15] -; CHECK-NEXT: vmov.16 q0[7], r1 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vmov.u16 r1, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[12] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[13] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[14] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[15] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q3[12] -; CHECK-NEXT: vmov.32 q7[0], r1 -; CHECK-NEXT: vmov.u8 r1, q3[13] -; CHECK-NEXT: vmov.32 q7[1], r1 -; CHECK-NEXT: vmov.u8 r1, q3[14] -; CHECK-NEXT: vmov.32 q7[2], r1 -; CHECK-NEXT: vmov.u8 r1, q3[15] -; CHECK-NEXT: vmov.32 q7[3], r1 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q7, q7 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmovlb.s16 q7, q7 -; CHECK-NEXT: vmov.u16 r1, q4[0] -; CHECK-NEXT: vmul.i32 q0, q7, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q6, q6, q0 -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q4[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q4[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q4[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[0] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q3[0] -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.u8 r1, q3[1] -; CHECK-NEXT: vmov.32 q4[1], r1 -; CHECK-NEXT: vmov.u8 r1, q3[2] -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.u8 r1, q3[3] -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q4, q4 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmov.u16 r1, q5[0] -; CHECK-NEXT: vmovlb.s16 q4, q4 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q4, q0 -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q1[8] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q1[9] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q1[10] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q1[11] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q3[8] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q3[9] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q3[10] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q3[11] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vmul.i32 q0, q1, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vadd.i32 q0, q2, q6 -; CHECK-NEXT: vaddva.u32 r0, q0 -; CHECK-NEXT: add sp, #32 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q2, zr +; CHECK-NEXT: vmlavat.s8 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -3868,10 +2043,9 @@ ; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vmul.i32 q0, q0, q1 -; CHECK-NEXT: vand q1, q2, q3 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvat.u32 r0, q0 +; CHECK-NEXT: vand q2, q2, q3 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavat.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -3889,13 +2063,12 @@ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmovlb.s8 q1, q1 ; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vmovlb.s16 q1, q1 +; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vmul.i32 q0, q0, q1 -; CHECK-NEXT: vmov.i32 q1, #0xff -; CHECK-NEXT: vand q1, q2, q1 -; CHECK-NEXT: vpt.i32 eq, q1, zr -; CHECK-NEXT: vaddvat.u32 r0, q0 +; CHECK-NEXT: vpt.i32 eq, q2, zr +; CHECK-NEXT: vmlavat.u32 r0, q0, q1 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -4169,10 +2342,11 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.u8 q0, q0, q1 -; CHECK-NEXT: vmovlb.u8 q1, q2 -; CHECK-NEXT: vpt.i16 eq, q1, zr -; CHECK-NEXT: vaddvat.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vmovlb.u8 q0, q0 +; CHECK-NEXT: vmovlb.u8 q2, q2 +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavat.u16 r0, q0, q1 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -4189,10 +2363,11 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmullb.s8 q0, q0, q1 -; CHECK-NEXT: vmovlb.u8 q1, q2 -; CHECK-NEXT: vpt.i16 eq, q1, zr -; CHECK-NEXT: vaddvat.u16 r0, q0 +; CHECK-NEXT: vmovlb.s8 q1, q1 +; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmovlb.u8 q2, q2 +; CHECK-NEXT: vpt.i16 eq, q2, zr +; CHECK-NEXT: vmlavat.u16 r0, q0, q1 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -4209,9 +2384,8 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i8 %a) { ; CHECK-LABEL: add_v16i8_v16i8_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmul.i8 q0, q0, q1 ; CHECK-NEXT: vpt.i8 eq, q2, zr -; CHECK-NEXT: vaddvat.u8 r0, q0 +; CHECK-NEXT: vmlavat.u8 r0, q0, q1 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: