Index: llvm/lib/Target/ARM/ARMISelLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.h +++ llvm/lib/Target/ARM/ARMISelLowering.h @@ -219,14 +219,16 @@ // MVE reductions VADDVs, // sign- or zero-extend the elements of a vector to i32, VADDVu, // add them all together, and return an i32 of their sum + VADDVps, // Same as VADDV[su] but with a v4i1 predicate mask + VADDVpu, VADDLVs, // sign- or zero-extend elements to i64 and sum, returning VADDLVu, // the low and high 32-bit halves of the sum - VADDLVAs, // same as VADDLV[su] but also add an input accumulator + VADDLVAs, // Same as VADDLV[su] but also add an input accumulator VADDLVAu, // provided as low and high halves - VADDLVps, // same as VADDLVs but with a v4i1 predicate mask - VADDLVpu, // same as VADDLVu but with a v4i1 predicate mask - VADDLVAps, // same as VADDLVps but with a v4i1 predicate mask - VADDLVApu, // same as VADDLVpu but with a v4i1 predicate mask + VADDLVps, // Same as VADDLV[su] but with a v4i1 predicate mask + VADDLVpu, + VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask + VADDLVApu, VMLAVs, VMLAVu, VMLALVs, Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1718,6 +1718,8 @@ case ARMISD::VMULLu: return "ARMISD::VMULLu"; case ARMISD::VADDVs: return "ARMISD::VADDVs"; case ARMISD::VADDVu: return "ARMISD::VADDVu"; + case ARMISD::VADDVps: return "ARMISD::VADDVps"; + case ARMISD::VADDVpu: return "ARMISD::VADDVpu"; case ARMISD::VADDLVs: return "ARMISD::VADDLVs"; case ARMISD::VADDLVu: return "ARMISD::VADDLVu"; case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs"; @@ -14729,6 +14731,20 @@ return A; return SDValue(); }; + auto IsPredVADDV = [&](MVT RetTy, unsigned ExtendCode, + ArrayRef ExtTypes, SDValue &Mask) { + if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || + !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) + return SDValue(); + Mask = N0->getOperand(0); + SDValue Ext = N0->getOperand(1); + if (Ext->getOpcode() != ExtendCode) + return SDValue(); + SDValue A = Ext->getOperand(0); + if (llvm::any_of(ExtTypes, [&A](MVT Ty) { return A.getValueType() == Ty; })) + return A; + return SDValue(); + }; auto IsVMLAV = [&](MVT RetTy, unsigned ExtendCode, ArrayRef ExtTypes, SDValue &A, SDValue &B) { if (ResVT != RetTy || N0->getOpcode() != ISD::MUL) @@ -14759,6 +14775,16 @@ if (SDValue A = IsVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32})) return Create64bitNode(ARMISD::VADDLVu, {A}); + SDValue Mask; + if (SDValue A = IsPredVADDV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask)) + return DAG.getNode(ARMISD::VADDVps, dl, ResVT, A, Mask); + if (SDValue A = IsPredVADDV(MVT::i32, ISD::ZERO_EXTEND, {MVT::v8i16, MVT::v16i8}, Mask)) + return DAG.getNode(ARMISD::VADDVpu, dl, ResVT, A, Mask); + if (SDValue A = IsPredVADDV(MVT::i64, ISD::SIGN_EXTEND, {MVT::v4i32}, Mask)) + return Create64bitNode(ARMISD::VADDLVps, {A, Mask}); + if (SDValue A = IsPredVADDV(MVT::i64, ISD::ZERO_EXTEND, {MVT::v4i32}, Mask)) + return Create64bitNode(ARMISD::VADDLVpu, {A, Mask}); + SDValue A, B; if (IsVMLAV(MVT::i32, ISD::SIGN_EXTEND, {MVT::v8i16, MVT::v16i8}, A, B)) return DAG.getNode(ARMISD::VMLAVs, dl, ResVT, A, B); Index: llvm/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrMVE.td +++ llvm/lib/Target/ARM/ARMInstrMVE.td @@ -710,8 +710,13 @@ let validForTailPredication = 1; } +def SDTVecReduceP : SDTypeProfile<1, 2, [ // VADDLVp + SDTCisInt<0>, SDTCisVec<1>, SDTCisVec<2> +]>; def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>; def ARMVADDVu : SDNode<"ARMISD::VADDVu", SDTVecReduce>; +def ARMVADDVps : SDNode<"ARMISD::VADDVps", SDTVecReduceP>; +def ARMVADDVpu : SDNode<"ARMISD::VADDVpu", SDTVecReduceP>; multiclass MVE_VADDV_A { def acc : MVE_VADDV<"vaddva", VTI.Suffix, @@ -728,20 +733,39 @@ if VTI.Unsigned then { def : Pat<(i32 (vecreduce_add (VTI.Vec MQPR:$vec))), (i32 (InstN $vec))>; + def : Pat<(i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred), + (VTI.Vec MQPR:$vec), + (VTI.Vec MVEimmAllZerosV))))), + (i32 (InstN $vec, ARMVCCThen, $pred))>; def : Pat<(i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), (i32 (InstN $vec))>; + def : Pat<(i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), + (i32 (InstN $vec, ARMVCCThen, $pred))>; def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec MQPR:$vec))), (i32 tGPREven:$acc))), (i32 (InstA $acc, $vec))>; + def : Pat<(i32 (add (i32 (vecreduce_add (VTI.Vec (vselect (VTI.Pred VCCR:$pred), + (VTI.Vec MQPR:$vec), + (VTI.Vec MVEimmAllZerosV))))), + (i32 tGPREven:$acc))), + (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; def : Pat<(i32 (add (i32 (ARMVADDVu (VTI.Vec MQPR:$vec))), (i32 tGPREven:$acc))), (i32 (InstA $acc, $vec))>; + def : Pat<(i32 (add (i32 (ARMVADDVpu (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), + (i32 tGPREven:$acc))), + (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; } else { def : Pat<(i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), (i32 (InstN $vec))>; def : Pat<(i32 (add (i32 (ARMVADDVs (VTI.Vec MQPR:$vec))), (i32 tGPREven:$acc))), (i32 (InstA $acc, $vec))>; + def : Pat<(i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), + (i32 (InstN $vec, ARMVCCThen, $pred))>; + def : Pat<(i32 (add (i32 (ARMVADDVps (VTI.Vec MQPR:$vec), (VTI.Pred VCCR:$pred))), + (i32 tGPREven:$acc))), + (i32 (InstA $acc, $vec, ARMVCCThen, $pred))>; } def : Pat<(i32 (int_arm_mve_addv_predicated (VTI.Vec MQPR:$vec), Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll +++ llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll @@ -4,10 +4,8 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i32: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q0 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -19,47 +17,8 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_zext(<4 x i32> %x, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i64_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.f32 s12, s0 -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: vmov.f32 s14, s1 -; CHECK-NEXT: vmov.i64 q2, #0xffffffff -; CHECK-NEXT: vand q3, q3, q2 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vand q1, q3, q1 -; CHECK-NEXT: vmov r3, s6 -; CHECK-NEXT: vmov r1, s4 -; CHECK-NEXT: vmov r12, s7 -; CHECK-NEXT: vmov r2, s5 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vand q0, q1, q2 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r0, r0, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r1 -; CHECK-NEXT: adc.w r1, r2, r3 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddlvt.u32 r0, r1, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -72,60 +31,8 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_sext(<4 x i32> %x, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i64_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.f32 s12, s0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.f32 s14, s1 -; CHECK-NEXT: vmov r0, s12 -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: asrs r0, r0, #31 -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov r0, s14 -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: asrs r0, r0, #31 -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmrs r0, p0 -; CHECK-NEXT: and r1, r0, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: ubfx r1, r0, #4, #1 -; CHECK-NEXT: rsbs r1, r1, #0 -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vand q1, q2, q1 -; CHECK-NEXT: vmov r1, s6 -; CHECK-NEXT: vmov r2, s4 -; CHECK-NEXT: vmov r12, s7 -; CHECK-NEXT: vmov r3, s5 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: adds r1, r1, r2 -; CHECK-NEXT: adc.w r2, r3, r12 -; CHECK-NEXT: vmov r3, s4 -; CHECK-NEXT: vmov.32 q0[0], r3 -; CHECK-NEXT: asrs r3, r3, #31 -; CHECK-NEXT: vmov.32 q0[1], r3 -; CHECK-NEXT: vmov r3, s6 -; CHECK-NEXT: vmov.32 q0[2], r3 -; CHECK-NEXT: asrs r3, r3, #31 -; CHECK-NEXT: vmov.32 q0[3], r3 -; CHECK-NEXT: ubfx r3, r0, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: ubfx r0, r0, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: adds r1, r1, r3 -; CHECK-NEXT: vmov r3, s3 -; CHECK-NEXT: adcs r2, r0 -; CHECK-NEXT: vmov r0, s2 -; CHECK-NEXT: adds r0, r0, r1 -; CHECK-NEXT: adc.w r1, r2, r3 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddlvt.s32 r0, r1, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -214,54 +121,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_zext(<8 x i16> %x, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9} -; CHECK-NEXT: vpush {d8, d9} -; CHECK-NEXT: vmov.i8 q2, #0x0 -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q4, #0xffff -; CHECK-NEXT: vpsel q1, q3, q2 -; CHECK-NEXT: vmov.u16 r0, q1[0] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[1] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[0] -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[3] -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmov.u16 r0, q1[4] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q2, q3, q4 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmovlb.u16 q0, q1 -; CHECK-NEXT: vpt.i32 ne, q3, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vaddv.u32 r0, q2 -; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -274,50 +135,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_sext(<8 x i16> %x, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q2, #0x0 -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vpsel q1, q3, q2 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vmov.u16 r0, q1[0] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[1] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[2] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[3] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[0] -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[1] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[2] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[3] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vmov.u16 r0, q1[4] -; CHECK-NEXT: vmovlb.s16 q2, q2 -; CHECK-NEXT: vpsel q2, q2, q3 -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u16 r0, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u16 r0, q1[6] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u16 r0, q1[7] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmov.u16 r0, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmovlb.s16 q0, q1 -; CHECK-NEXT: vpt.i32 ne, q3, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vaddv.u32 r0, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.s16 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -330,13 +149,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_zext: ; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmovlb.u16 q0, q0 ; CHECK-NEXT: vmovlb.u16 q1, q1 -; CHECK-NEXT: vmov.i32 q2, #0xffff -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q2 -; CHECK-NEXT: vaddv.u32 r0, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -349,12 +165,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q0 +; CHECK-NEXT: vmovlb.u16 q1, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -367,10 +181,8 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q0 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -732,138 +544,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_zext(<16 x i8> %x, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #16 -; CHECK-NEXT: sub sp, #16 -; CHECK-NEXT: vmov q2, q0 -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i8 q5, #0xff -; CHECK-NEXT: vpsel q7, q5, q0 -; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill -; CHECK-NEXT: vmov.u8 r0, q7[0] -; CHECK-NEXT: vmov.i32 q6, #0xff -; CHECK-NEXT: vmov.16 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q7[1] -; CHECK-NEXT: vmov.16 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q7[2] -; CHECK-NEXT: vmov.16 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q7[3] -; CHECK-NEXT: vmov.16 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q7[4] -; CHECK-NEXT: vmov.16 q1[4], r0 -; CHECK-NEXT: vmov.u8 r0, q7[5] -; CHECK-NEXT: vmov.16 q1[5], r0 -; CHECK-NEXT: vmov.u8 r0, q7[6] -; CHECK-NEXT: vmov.16 q1[6], r0 -; CHECK-NEXT: vmov.u8 r0, q7[7] -; CHECK-NEXT: vmov.16 q1[7], r0 -; CHECK-NEXT: vcmp.i16 ne, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q4, q5, q0 -; CHECK-NEXT: vmov q3, q1 -; CHECK-NEXT: vmov.u16 r0, q4[4] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q4[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q4[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q4[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q7[8] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q3, q0, q6 -; CHECK-NEXT: vmov.16 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q7[9] -; CHECK-NEXT: vmov.16 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q7[10] -; CHECK-NEXT: vmov.16 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q7[11] -; CHECK-NEXT: vmov.16 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q7[12] -; CHECK-NEXT: vmov.16 q0[4], r0 -; CHECK-NEXT: vmov.u8 r0, q7[13] -; CHECK-NEXT: vmov.16 q0[5], r0 -; CHECK-NEXT: vmov.u8 r0, q7[14] -; CHECK-NEXT: vmov.16 q0[6], r0 -; CHECK-NEXT: vmov.u8 r0, q7[15] -; CHECK-NEXT: vmov.16 q0[7], r0 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vmov.u16 r0, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[12] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[13] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[14] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[15] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u16 r0, q4[0] -; CHECK-NEXT: vand q0, q0, q6 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q4[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q4[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q4[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[0] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u16 r0, q5[0] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q6 -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u16 r0, q5[1] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u16 r0, q5[2] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u16 r0, q5[3] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vmov.u8 r0, q2[8] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r0 -; CHECK-NEXT: vmov.u8 r0, q2[9] -; CHECK-NEXT: vmov.32 q0[1], r0 -; CHECK-NEXT: vmov.u8 r0, q2[10] -; CHECK-NEXT: vmov.32 q0[2], r0 -; CHECK-NEXT: vmov.u8 r0, q2[11] -; CHECK-NEXT: vmov.32 q0[3], r0 -; CHECK-NEXT: vand q0, q0, q6 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q1, q0 -; CHECK-NEXT: vadd.i32 q0, q1, q3 -; CHECK-NEXT: vaddv.u32 r0, q0 -; CHECK-NEXT: add sp, #16 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvt.u8 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -876,133 +558,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_sext(<16 x i8> %x, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q5, #0xff -; CHECK-NEXT: vmov.i32 q4, #0x0 -; CHECK-NEXT: vpsel q6, q5, q3 -; CHECK-NEXT: vmov.u8 r0, q6[0] -; CHECK-NEXT: vmov.16 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q6[1] -; CHECK-NEXT: vmov.16 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q6[2] -; CHECK-NEXT: vmov.16 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q6[3] -; CHECK-NEXT: vmov.16 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q6[4] -; CHECK-NEXT: vmov.16 q1[4], r0 -; CHECK-NEXT: vmov.u8 r0, q6[5] -; CHECK-NEXT: vmov.16 q1[5], r0 -; CHECK-NEXT: vmov.u8 r0, q6[6] -; CHECK-NEXT: vmov.16 q1[6], r0 -; CHECK-NEXT: vmov.u8 r0, q6[7] -; CHECK-NEXT: vmov.16 q1[7], r0 -; CHECK-NEXT: vcmp.i16 ne, q1, zr -; CHECK-NEXT: vpsel q2, q5, q3 -; CHECK-NEXT: vmov.u16 r0, q2[4] -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[4] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r0 -; CHECK-NEXT: vmov.u8 r0, q6[8] -; CHECK-NEXT: vmov.16 q7[0], r0 -; CHECK-NEXT: vmov.u8 r0, q6[9] -; CHECK-NEXT: vmov.16 q7[1], r0 -; CHECK-NEXT: vmov.u8 r0, q6[10] -; CHECK-NEXT: vmov.16 q7[2], r0 -; CHECK-NEXT: vmov.u8 r0, q6[11] -; CHECK-NEXT: vmov.16 q7[3], r0 -; CHECK-NEXT: vmov.u8 r0, q6[12] -; CHECK-NEXT: vmov.16 q7[4], r0 -; CHECK-NEXT: vmov.u8 r0, q6[13] -; CHECK-NEXT: vmov.16 q7[5], r0 -; CHECK-NEXT: vmov.u8 r0, q6[14] -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vmov.16 q7[6], r0 -; CHECK-NEXT: vmov.u8 r0, q6[15] -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vmov.16 q7[7], r0 -; CHECK-NEXT: vpsel q1, q1, q4 -; CHECK-NEXT: vcmp.i16 ne, q7, zr -; CHECK-NEXT: vpsel q3, q5, q3 -; CHECK-NEXT: vmov.u16 r0, q3[4] -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vmov.u16 r0, q3[5] -; CHECK-NEXT: vmov.32 q5[1], r0 -; CHECK-NEXT: vmov.u16 r0, q3[6] -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vmov.u16 r0, q3[7] -; CHECK-NEXT: vmov.32 q5[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[12] -; CHECK-NEXT: vcmp.i32 ne, q5, zr -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[13] -; CHECK-NEXT: vmov.32 q5[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[14] -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[15] -; CHECK-NEXT: vmov.32 q5[3], r0 -; CHECK-NEXT: vmov.u16 r0, q2[0] -; CHECK-NEXT: vmovlb.s8 q5, q5 -; CHECK-NEXT: vmovlb.s16 q5, q5 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q1, q5 -; CHECK-NEXT: vmov.32 q5[0], r0 -; CHECK-NEXT: vmov.u16 r0, q2[1] -; CHECK-NEXT: vmov.32 q5[1], r0 -; CHECK-NEXT: vmov.u16 r0, q2[2] -; CHECK-NEXT: vmov.32 q5[2], r0 -; CHECK-NEXT: vmov.u16 r0, q2[3] -; CHECK-NEXT: vmov.32 q5[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[0] -; CHECK-NEXT: vmov.32 q2[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[1] -; CHECK-NEXT: vmov.32 q2[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[2] -; CHECK-NEXT: vmov.32 q2[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[3] -; CHECK-NEXT: vmov.32 q2[3], r0 -; CHECK-NEXT: vcmp.i32 ne, q5, zr -; CHECK-NEXT: vmovlb.s8 q2, q2 -; CHECK-NEXT: vmov.u16 r0, q3[0] -; CHECK-NEXT: vmovlb.s16 q2, q2 -; CHECK-NEXT: vpsel q2, q2, q4 -; CHECK-NEXT: vmov.32 q4[0], r0 -; CHECK-NEXT: vmov.u16 r0, q3[1] -; CHECK-NEXT: vmov.32 q4[1], r0 -; CHECK-NEXT: vmov.u16 r0, q3[2] -; CHECK-NEXT: vmov.32 q4[2], r0 -; CHECK-NEXT: vmov.u16 r0, q3[3] -; CHECK-NEXT: vmov.32 q4[3], r0 -; CHECK-NEXT: vmov.u8 r0, q0[8] -; CHECK-NEXT: vmov.32 q3[0], r0 -; CHECK-NEXT: vmov.u8 r0, q0[9] -; CHECK-NEXT: vmov.32 q3[1], r0 -; CHECK-NEXT: vmov.u8 r0, q0[10] -; CHECK-NEXT: vmov.32 q3[2], r0 -; CHECK-NEXT: vmov.u8 r0, q0[11] -; CHECK-NEXT: vmov.32 q3[3], r0 -; CHECK-NEXT: vmovlb.s8 q0, q3 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vadd.i32 q0, q2, q1 -; CHECK-NEXT: vaddv.u32 r0, q0 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvt.s8 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -1016,12 +573,10 @@ ; CHECK-LABEL: add_v4i8_v4i32_zext: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i32 q2, #0xff +; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q1, q1, q2 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q2 -; CHECK-NEXT: vaddv.u32 r0, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -1034,14 +589,12 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %b) { ; CHECK-LABEL: add_v4i8_v4i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q0 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -1232,12 +785,10 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q0, q0 -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1251,12 +802,10 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1270,10 +819,8 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i8: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddv.u8 r0, q0 +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvt.u8 r0, q0 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1980,10 +1527,8 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %b, i32 %a) { ; CHECK-LABEL: add_v4i32_v4i32_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q0 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -1996,52 +1541,9 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_zext(<4 x i32> %x, <4 x i32> %b, i64 %a) { ; CHECK-LABEL: add_v4i32_v4i64_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r7, lr} -; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.f32 s12, s0 -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: vmov.f32 s14, s1 -; CHECK-NEXT: vmov.i64 q2, #0xffffffff -; CHECK-NEXT: vand q3, q3, q2 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q1[2], r3 -; CHECK-NEXT: vmov.32 q1[3], r3 -; CHECK-NEXT: vand q1, q3, q1 -; CHECK-NEXT: vmov r3, s6 -; CHECK-NEXT: vmov r4, s4 -; CHECK-NEXT: vmov r12, s7 -; CHECK-NEXT: vmov lr, s5 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: vand q0, q1, q2 -; CHECK-NEXT: adds r5, r4, r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsb.w r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsb.w r2, r2, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: adc.w r4, lr, r12 -; CHECK-NEXT: vmov.32 q1[2], r2 -; CHECK-NEXT: vmov.32 q1[3], r2 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: adds r3, r3, r5 -; CHECK-NEXT: vmov r5, s3 -; CHECK-NEXT: adcs r2, r4 -; CHECK-NEXT: vmov r4, s2 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adcs r2, r5 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddlvat.u32 r0, r1, q0 +; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer %xx = zext <4 x i32> %x to <4 x i64> @@ -2054,65 +1556,9 @@ define arm_aapcs_vfpcc i64 @add_v4i32_v4i64_acc_sext(<4 x i32> %x, <4 x i32> %b, i64 %a) { ; CHECK-LABEL: add_v4i32_v4i64_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r7, lr} -; CHECK-NEXT: push {r4, r5, r7, lr} -; CHECK-NEXT: vmov.f32 s12, s0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.f32 s14, s1 -; CHECK-NEXT: vmov r2, s12 -; CHECK-NEXT: vmov.32 q2[0], r2 -; CHECK-NEXT: asrs r2, r2, #31 -; CHECK-NEXT: vmov.32 q2[1], r2 -; CHECK-NEXT: vmov r2, s14 -; CHECK-NEXT: vmov.32 q2[2], r2 -; CHECK-NEXT: asrs r2, r2, #31 -; CHECK-NEXT: vmov.32 q2[3], r2 -; CHECK-NEXT: vmrs r2, p0 -; CHECK-NEXT: and r3, r2, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: ubfx r3, r2, #4, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: vmov.32 q1[2], r3 -; CHECK-NEXT: vmov.32 q1[3], r3 -; CHECK-NEXT: vand q1, q2, q1 -; CHECK-NEXT: vmov r3, s6 -; CHECK-NEXT: vmov r4, s4 -; CHECK-NEXT: vmov r12, s7 -; CHECK-NEXT: vmov r5, s5 -; CHECK-NEXT: vmov.f32 s4, s2 -; CHECK-NEXT: vmov.f32 s6, s3 -; CHECK-NEXT: adds.w lr, r4, r3 -; CHECK-NEXT: vmov r3, s4 -; CHECK-NEXT: vmov.32 q0[0], r3 -; CHECK-NEXT: adc.w r12, r12, r5 -; CHECK-NEXT: asrs r3, r3, #31 -; CHECK-NEXT: vmov.32 q0[1], r3 -; CHECK-NEXT: vmov r3, s6 -; CHECK-NEXT: vmov.32 q0[2], r3 -; CHECK-NEXT: asrs r3, r3, #31 -; CHECK-NEXT: vmov.32 q0[3], r3 -; CHECK-NEXT: ubfx r3, r2, #8, #1 -; CHECK-NEXT: rsbs r3, r3, #0 -; CHECK-NEXT: ubfx r2, r2, #12, #1 -; CHECK-NEXT: vmov.32 q1[0], r3 -; CHECK-NEXT: rsbs r2, r2, #0 -; CHECK-NEXT: vmov.32 q1[1], r3 -; CHECK-NEXT: vmov.32 q1[2], r2 -; CHECK-NEXT: vmov.32 q1[3], r2 -; CHECK-NEXT: vand q0, q0, q1 -; CHECK-NEXT: vmov r3, s0 -; CHECK-NEXT: vmov r2, s1 -; CHECK-NEXT: vmov r4, s2 -; CHECK-NEXT: vmov r5, s3 -; CHECK-NEXT: adds.w r3, r3, lr -; CHECK-NEXT: adc.w r2, r2, r12 -; CHECK-NEXT: adds r3, r3, r4 -; CHECK-NEXT: adcs r2, r5 -; CHECK-NEXT: adds r0, r0, r3 -; CHECK-NEXT: adcs r1, r2 -; CHECK-NEXT: pop {r4, r5, r7, pc} +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddlvat.s32 r0, r1, q0 +; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer %xx = sext <4 x i32> %x to <4 x i64> @@ -2211,54 +1657,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_zext(<8 x i16> %x, <8 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v8i16_v8i32_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9} -; CHECK-NEXT: vpush {d8, d9} -; CHECK-NEXT: vmov.i8 q2, #0x0 -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q4, #0xffff -; CHECK-NEXT: vpsel q1, q3, q2 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[2] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[3] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[0] -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[1] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[2] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[3] -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmov.u16 r1, q1[4] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q2, q3, q4 -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[6] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[7] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmovlb.u16 q0, q1 -; CHECK-NEXT: vpt.i32 ne, q3, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vaddva.u32 r0, q2 -; CHECK-NEXT: vpop {d8, d9} +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -2272,50 +1672,8 @@ define arm_aapcs_vfpcc i32 @add_v8i16_v8i32_acc_sext(<8 x i16> %x, <8 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v8i16_v8i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i8 q2, #0x0 -; CHECK-NEXT: vmov.i8 q3, #0xff -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vpsel q1, q3, q2 -; CHECK-NEXT: vmov.i32 q3, #0x0 -; CHECK-NEXT: vmov.u16 r1, q1[0] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[1] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[2] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[3] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[0] -; CHECK-NEXT: vcmp.i32 ne, q2, zr -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[1] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[2] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[3] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vmov.u16 r1, q1[4] -; CHECK-NEXT: vmovlb.s16 q2, q2 -; CHECK-NEXT: vpsel q2, q2, q3 -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u16 r1, q1[5] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u16 r1, q1[6] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u16 r1, q1[7] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmov.u16 r1, q0[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmovlb.s16 q0, q1 -; CHECK-NEXT: vpt.i32 ne, q3, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vaddva.u32 r0, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.s16 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <8 x i16> %b, zeroinitializer @@ -2329,13 +1687,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v4i16_v4i32_acc_zext: ; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmovlb.u16 q0, q0 ; CHECK-NEXT: vmovlb.u16 q1, q1 -; CHECK-NEXT: vmov.i32 q2, #0xffff -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q2 -; CHECK-NEXT: vaddva.u32 r0, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -2349,12 +1704,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v4i16_v4i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q0 +; CHECK-NEXT: vmovlb.u16 q1, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -2368,10 +1721,8 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %b, i16 %a) { ; CHECK-LABEL: add_v8i16_v8i16_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q0 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -2752,138 +2103,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_zext(<16 x i8> %x, <16 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v16i8_v16i32_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: .pad #16 -; CHECK-NEXT: sub sp, #16 -; CHECK-NEXT: vmov q2, q0 -; CHECK-NEXT: vmov.i8 q0, #0x0 -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i8 q5, #0xff -; CHECK-NEXT: vpsel q7, q5, q0 -; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill -; CHECK-NEXT: vmov.u8 r1, q7[0] -; CHECK-NEXT: vmov.i32 q6, #0xff -; CHECK-NEXT: vmov.16 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q7[1] -; CHECK-NEXT: vmov.16 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q7[2] -; CHECK-NEXT: vmov.16 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q7[3] -; CHECK-NEXT: vmov.16 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q7[4] -; CHECK-NEXT: vmov.16 q1[4], r1 -; CHECK-NEXT: vmov.u8 r1, q7[5] -; CHECK-NEXT: vmov.16 q1[5], r1 -; CHECK-NEXT: vmov.u8 r1, q7[6] -; CHECK-NEXT: vmov.16 q1[6], r1 -; CHECK-NEXT: vmov.u8 r1, q7[7] -; CHECK-NEXT: vmov.16 q1[7], r1 -; CHECK-NEXT: vcmp.i16 ne, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q4, q5, q0 -; CHECK-NEXT: vmov q3, q1 -; CHECK-NEXT: vmov.u16 r1, q4[4] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q4[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q4[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q4[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[4] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q7[8] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q3, q0, q6 -; CHECK-NEXT: vmov.16 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q7[9] -; CHECK-NEXT: vmov.16 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q7[10] -; CHECK-NEXT: vmov.16 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q7[11] -; CHECK-NEXT: vmov.16 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q7[12] -; CHECK-NEXT: vmov.16 q0[4], r1 -; CHECK-NEXT: vmov.u8 r1, q7[13] -; CHECK-NEXT: vmov.16 q0[5], r1 -; CHECK-NEXT: vmov.u8 r1, q7[14] -; CHECK-NEXT: vmov.16 q0[6], r1 -; CHECK-NEXT: vmov.u8 r1, q7[15] -; CHECK-NEXT: vmov.16 q0[7], r1 -; CHECK-NEXT: vcmp.i16 ne, q0, zr -; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload -; CHECK-NEXT: vpsel q5, q5, q0 -; CHECK-NEXT: vmov.u16 r1, q5[4] -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[5] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[6] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[7] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[12] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[13] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[14] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[15] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u16 r1, q4[0] -; CHECK-NEXT: vand q0, q0, q6 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q3, q3, q0 -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q4[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q4[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q4[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[0] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u16 r1, q5[0] -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q6 -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u16 r1, q5[1] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u16 r1, q5[2] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u16 r1, q5[3] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vmov.u8 r1, q2[8] -; CHECK-NEXT: vcmp.i32 ne, q0, zr -; CHECK-NEXT: vmov.32 q0[0], r1 -; CHECK-NEXT: vmov.u8 r1, q2[9] -; CHECK-NEXT: vmov.32 q0[1], r1 -; CHECK-NEXT: vmov.u8 r1, q2[10] -; CHECK-NEXT: vmov.32 q0[2], r1 -; CHECK-NEXT: vmov.u8 r1, q2[11] -; CHECK-NEXT: vmov.32 q0[3], r1 -; CHECK-NEXT: vand q0, q0, q6 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q1, q0 -; CHECK-NEXT: vadd.i32 q0, q1, q3 -; CHECK-NEXT: vaddva.u32 r0, q0 -; CHECK-NEXT: add sp, #16 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvat.u8 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -2897,133 +2118,8 @@ define arm_aapcs_vfpcc i32 @add_v16i8_v16i32_acc_sext(<16 x i8> %x, <16 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v16i8_v16i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i8 q3, #0x0 -; CHECK-NEXT: vmov.i8 q5, #0xff -; CHECK-NEXT: vmov.i32 q4, #0x0 -; CHECK-NEXT: vpsel q6, q5, q3 -; CHECK-NEXT: vmov.u8 r1, q6[0] -; CHECK-NEXT: vmov.16 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q6[1] -; CHECK-NEXT: vmov.16 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q6[2] -; CHECK-NEXT: vmov.16 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q6[3] -; CHECK-NEXT: vmov.16 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q6[4] -; CHECK-NEXT: vmov.16 q1[4], r1 -; CHECK-NEXT: vmov.u8 r1, q6[5] -; CHECK-NEXT: vmov.16 q1[5], r1 -; CHECK-NEXT: vmov.u8 r1, q6[6] -; CHECK-NEXT: vmov.16 q1[6], r1 -; CHECK-NEXT: vmov.u8 r1, q6[7] -; CHECK-NEXT: vmov.16 q1[7], r1 -; CHECK-NEXT: vcmp.i16 ne, q1, zr -; CHECK-NEXT: vpsel q2, q5, q3 -; CHECK-NEXT: vmov.u16 r1, q2[4] -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q0[4] -; CHECK-NEXT: vcmp.i32 ne, q1, zr -; CHECK-NEXT: vmov.32 q1[0], r1 -; CHECK-NEXT: vmov.u8 r1, q0[5] -; CHECK-NEXT: vmov.32 q1[1], r1 -; CHECK-NEXT: vmov.u8 r1, q0[6] -; CHECK-NEXT: vmov.32 q1[2], r1 -; CHECK-NEXT: vmov.u8 r1, q0[7] -; CHECK-NEXT: vmov.32 q1[3], r1 -; CHECK-NEXT: vmov.u8 r1, q6[8] -; CHECK-NEXT: vmov.16 q7[0], r1 -; CHECK-NEXT: vmov.u8 r1, q6[9] -; CHECK-NEXT: vmov.16 q7[1], r1 -; CHECK-NEXT: vmov.u8 r1, q6[10] -; CHECK-NEXT: vmov.16 q7[2], r1 -; CHECK-NEXT: vmov.u8 r1, q6[11] -; CHECK-NEXT: vmov.16 q7[3], r1 -; CHECK-NEXT: vmov.u8 r1, q6[12] -; CHECK-NEXT: vmov.16 q7[4], r1 -; CHECK-NEXT: vmov.u8 r1, q6[13] -; CHECK-NEXT: vmov.16 q7[5], r1 -; CHECK-NEXT: vmov.u8 r1, q6[14] -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vmov.16 q7[6], r1 -; CHECK-NEXT: vmov.u8 r1, q6[15] -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vmov.16 q7[7], r1 -; CHECK-NEXT: vpsel q1, q1, q4 -; CHECK-NEXT: vcmp.i16 ne, q7, zr -; CHECK-NEXT: vpsel q3, q5, q3 -; CHECK-NEXT: vmov.u16 r1, q3[4] -; CHECK-NEXT: vmov.32 q5[0], r1 -; CHECK-NEXT: vmov.u16 r1, q3[5] -; CHECK-NEXT: vmov.32 q5[1], r1 -; CHECK-NEXT: vmov.u16 r1, q3[6] -; CHECK-NEXT: vmov.32 q5[2], r1 -; CHECK-NEXT: vmov.u16 r1, q3[7] -; CHECK-NEXT: vmov.32 q5[3], r1 -; CHECK-NEXT: vmov.u8 r1, q0[12] -; CHECK-NEXT: vcmp.i32 ne, q5, zr -; CHECK-NEXT: vmov.32 q5[0], r1 -; CHECK-NEXT: vmov.u8 r1, q0[13] -; CHECK-NEXT: vmov.32 q5[1], r1 -; CHECK-NEXT: vmov.u8 r1, q0[14] -; CHECK-NEXT: vmov.32 q5[2], r1 -; CHECK-NEXT: vmov.u8 r1, q0[15] -; CHECK-NEXT: vmov.32 q5[3], r1 -; CHECK-NEXT: vmov.u16 r1, q2[0] -; CHECK-NEXT: vmovlb.s8 q5, q5 -; CHECK-NEXT: vmovlb.s16 q5, q5 -; CHECK-NEXT: vpst -; CHECK-NEXT: vaddt.i32 q1, q1, q5 -; CHECK-NEXT: vmov.32 q5[0], r1 -; CHECK-NEXT: vmov.u16 r1, q2[1] -; CHECK-NEXT: vmov.32 q5[1], r1 -; CHECK-NEXT: vmov.u16 r1, q2[2] -; CHECK-NEXT: vmov.32 q5[2], r1 -; CHECK-NEXT: vmov.u16 r1, q2[3] -; CHECK-NEXT: vmov.32 q5[3], r1 -; CHECK-NEXT: vmov.u8 r1, q0[0] -; CHECK-NEXT: vmov.32 q2[0], r1 -; CHECK-NEXT: vmov.u8 r1, q0[1] -; CHECK-NEXT: vmov.32 q2[1], r1 -; CHECK-NEXT: vmov.u8 r1, q0[2] -; CHECK-NEXT: vmov.32 q2[2], r1 -; CHECK-NEXT: vmov.u8 r1, q0[3] -; CHECK-NEXT: vmov.32 q2[3], r1 -; CHECK-NEXT: vcmp.i32 ne, q5, zr -; CHECK-NEXT: vmovlb.s8 q2, q2 -; CHECK-NEXT: vmov.u16 r1, q3[0] -; CHECK-NEXT: vmovlb.s16 q2, q2 -; CHECK-NEXT: vpsel q2, q2, q4 -; CHECK-NEXT: vmov.32 q4[0], r1 -; CHECK-NEXT: vmov.u16 r1, q3[1] -; CHECK-NEXT: vmov.32 q4[1], r1 -; CHECK-NEXT: vmov.u16 r1, q3[2] -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.u16 r1, q3[3] -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.u8 r1, q0[8] -; CHECK-NEXT: vmov.32 q3[0], r1 -; CHECK-NEXT: vmov.u8 r1, q0[9] -; CHECK-NEXT: vmov.32 q3[1], r1 -; CHECK-NEXT: vmov.u8 r1, q0[10] -; CHECK-NEXT: vmov.32 q3[2], r1 -; CHECK-NEXT: vmov.u8 r1, q0[11] -; CHECK-NEXT: vmov.32 q3[3], r1 -; CHECK-NEXT: vmovlb.s8 q0, q3 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpt.i32 ne, q4, zr -; CHECK-NEXT: vaddt.i32 q2, q2, q0 -; CHECK-NEXT: vadd.i32 q0, q2, q1 -; CHECK-NEXT: vaddva.u32 r0, q0 -; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvat.s8 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <16 x i8> %b, zeroinitializer @@ -3038,12 +2134,10 @@ ; CHECK-LABEL: add_v4i8_v4i32_acc_zext: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i32 q2, #0xff +; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q1, q1, q2 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vandt q1, q0, q2 -; CHECK-NEXT: vaddva.u32 r0, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -3057,14 +2151,12 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v4i8_v4i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vmovlb.s8 q0, q0 +; CHECK-NEXT: vmov.i32 q2, #0xff ; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q0 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -3258,12 +2350,10 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.u8 q0, q0 -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -3278,12 +2368,10 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q1, q1 ; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vcmp.i16 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q0 +; CHECK-NEXT: vmovlb.u8 q1, q1 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -3298,10 +2386,8 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %b, i8 %a) { ; CHECK-LABEL: add_v16i8_v16i8_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vcmp.i8 eq, q1, zr -; CHECK-NEXT: vmov.i32 q1, #0x0 -; CHECK-NEXT: vpsel q0, q0, q1 -; CHECK-NEXT: vaddva.u8 r0, q0 +; CHECK-NEXT: vpt.i8 eq, q1, zr +; CHECK-NEXT: vaddvat.u8 r0, q0 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: Index: llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll +++ llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll @@ -4,10 +4,9 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b) { ; CHECK-LABEL: add_v4i32_v4i32: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i32 q0, q0, q1 ; CHECK-NEXT: vpt.i32 eq, q2, zr -; CHECK-NEXT: vmult.i32 q3, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q3 +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -381,14 +380,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q2, q2 -; CHECK-NEXT: vmovlb.u16 q1, q1 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.u16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q2 +; CHECK-NEXT: vmullb.u16 q0, q0, q1 +; CHECK-NEXT: vmovlb.u16 q1, q2 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -403,14 +398,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b) { ; CHECK-LABEL: add_v4i16_v4i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q2, q2 -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q2 +; CHECK-NEXT: vmullb.s16 q0, q0, q1 +; CHECK-NEXT: vmovlb.u16 q1, q2 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -425,10 +416,9 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b) { ; CHECK-LABEL: add_v8i16_v8i16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i16 q0, q0, q1 ; CHECK-NEXT: vpt.i16 eq, q2, zr -; CHECK-NEXT: vmult.i16 q3, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q3 +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1290,14 +1280,12 @@ ; CHECK-LABEL: add_v4i8_v4i32_zext: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i32 q3, #0xff -; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q2 +; CHECK-NEXT: vmul.i32 q0, q0, q1 +; CHECK-NEXT: vand q1, q2, q3 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -1312,17 +1300,15 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b) { ; CHECK-LABEL: add_v4i8_v4i32_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddv.u32 r0, q2 +; CHECK-NEXT: vmul.i32 q0, q0, q1 +; CHECK-NEXT: vmov.i32 q1, #0xff +; CHECK-NEXT: vand q1, q2, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvt.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -1593,14 +1579,10 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q2, q2 -; CHECK-NEXT: vmovlb.u8 q1, q1 -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.u8 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i16 q2, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q2 +; CHECK-NEXT: vmullb.u8 q0, q0, q1 +; CHECK-NEXT: vmovlb.u8 q1, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1616,14 +1598,10 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b) { ; CHECK-LABEL: add_v8i8_v8i16_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q2, q2 -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i16 q2, q0, q1 -; CHECK-NEXT: vaddv.u16 r0, q2 +; CHECK-NEXT: vmullb.s8 q0, q0, q1 +; CHECK-NEXT: vmovlb.u8 q1, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvt.u16 r0, q0 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -1639,10 +1617,9 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b) { ; CHECK-LABEL: add_v16i8_v16i8: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i8 q0, q0, q1 ; CHECK-NEXT: vpt.i8 eq, q2, zr -; CHECK-NEXT: vmult.i8 q3, q0, q1 -; CHECK-NEXT: vaddv.u8 r0, q3 +; CHECK-NEXT: vaddvt.u8 r0, q0 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: @@ -2567,10 +2544,9 @@ define arm_aapcs_vfpcc i32 @add_v4i32_v4i32_acc(<4 x i32> %x, <4 x i32> %y, <4 x i32> %b, i32 %a) { ; CHECK-LABEL: add_v4i32_v4i32_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i32 q0, q0, q1 ; CHECK-NEXT: vpt.i32 eq, q2, zr -; CHECK-NEXT: vmult.i32 q3, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q3 +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i32> %b, zeroinitializer @@ -2967,14 +2943,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_zext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v4i16_v4i32_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q2, q2 -; CHECK-NEXT: vmovlb.u16 q1, q1 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.u16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q2 +; CHECK-NEXT: vmullb.u16 q0, q0, q1 +; CHECK-NEXT: vmovlb.u16 q1, q2 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -2990,14 +2962,10 @@ define arm_aapcs_vfpcc i32 @add_v4i16_v4i32_acc_sext(<4 x i16> %x, <4 x i16> %y, <4 x i16> %b, i32 %a) { ; CHECK-LABEL: add_v4i16_v4i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u16 q2, q2 -; CHECK-NEXT: vmovlb.s16 q1, q1 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q2 +; CHECK-NEXT: vmullb.s16 q0, q0, q1 +; CHECK-NEXT: vmovlb.u16 q1, q2 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i16> %b, zeroinitializer @@ -3013,10 +2981,9 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i16_v8i16_acc(<8 x i16> %x, <8 x i16> %y, <8 x i16> %b, i16 %a) { ; CHECK-LABEL: add_v8i16_v8i16_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i16 q0, q0, q1 ; CHECK-NEXT: vpt.i16 eq, q2, zr -; CHECK-NEXT: vmult.i16 q3, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q3 +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -3899,14 +3866,12 @@ ; CHECK-LABEL: add_v4i8_v4i32_acc_zext: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: vmov.i32 q3, #0xff -; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q1, q1, q3 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vand q0, q0, q3 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q2 +; CHECK-NEXT: vmul.i32 q0, q0, q1 +; CHECK-NEXT: vand q1, q2, q3 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -3922,17 +3887,15 @@ define arm_aapcs_vfpcc i32 @add_v4i8_v4i32_acc_sext(<4 x i8> %x, <4 x i8> %y, <4 x i8> %b, i32 %a) { ; CHECK-LABEL: add_v4i8_v4i32_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0xff ; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vcmp.i32 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 ; CHECK-NEXT: vmovlb.s16 q1, q1 ; CHECK-NEXT: vmovlb.s16 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i32 q2, q0, q1 -; CHECK-NEXT: vaddva.u32 r0, q2 +; CHECK-NEXT: vmul.i32 q0, q0, q1 +; CHECK-NEXT: vmov.i32 q1, #0xff +; CHECK-NEXT: vand q1, q2, q1 +; CHECK-NEXT: vpt.i32 eq, q1, zr +; CHECK-NEXT: vaddvat.u32 r0, q0 ; CHECK-NEXT: bx lr entry: %c = icmp eq <4 x i8> %b, zeroinitializer @@ -4206,14 +4169,10 @@ define arm_aapcs_vfpcc zeroext i16 @add_v8i8_v8i16_acc_zext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q2, q2 -; CHECK-NEXT: vmovlb.u8 q1, q1 -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.u8 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i16 q2, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q2 +; CHECK-NEXT: vmullb.u8 q0, q0, q1 +; CHECK-NEXT: vmovlb.u8 q1, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: uxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -4230,14 +4189,10 @@ define arm_aapcs_vfpcc signext i16 @add_v8i8_v8i16_acc_sext(<8 x i8> %x, <8 x i8> %y, <8 x i8> %b, i16 %a) { ; CHECK-LABEL: add_v8i8_v8i16_acc_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovlb.u8 q2, q2 -; CHECK-NEXT: vmovlb.s8 q1, q1 -; CHECK-NEXT: vcmp.i16 eq, q2, zr -; CHECK-NEXT: vmov.i32 q2, #0x0 -; CHECK-NEXT: vmovlb.s8 q0, q0 -; CHECK-NEXT: vpst -; CHECK-NEXT: vmult.i16 q2, q0, q1 -; CHECK-NEXT: vaddva.u16 r0, q2 +; CHECK-NEXT: vmullb.s8 q0, q0, q1 +; CHECK-NEXT: vmovlb.u8 q1, q2 +; CHECK-NEXT: vpt.i16 eq, q1, zr +; CHECK-NEXT: vaddvat.u16 r0, q0 ; CHECK-NEXT: sxth r0, r0 ; CHECK-NEXT: bx lr entry: @@ -4254,10 +4209,9 @@ define arm_aapcs_vfpcc zeroext i8 @add_v16i8_v16i8_acc(<16 x i8> %x, <16 x i8> %y, <16 x i8> %b, i8 %a) { ; CHECK-LABEL: add_v16i8_v16i8_acc: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmov.i32 q3, #0x0 +; CHECK-NEXT: vmul.i8 q0, q0, q1 ; CHECK-NEXT: vpt.i8 eq, q2, zr -; CHECK-NEXT: vmult.i8 q3, q0, q1 -; CHECK-NEXT: vaddva.u8 r0, q3 +; CHECK-NEXT: vaddvat.u8 r0, q0 ; CHECK-NEXT: uxtb r0, r0 ; CHECK-NEXT: bx lr entry: