Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- /dev/null +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -0,0 +1,50 @@ +//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes microMIPSr6 instructions. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// +// Instruction Encodings +// +//===----------------------------------------------------------------------===// + +class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>; +class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + +class BC_MMR6_DESC_BASE + : BRANCH_DESC_BASE, MMR6Arch { + dag InOperandList = (ins opnd:$offset); + dag OutOperandList = (outs); + string AsmString = !strconcat(instr_asm, "\t$offset"); + bit isBarrier = 1; +} + +class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> { + bit isCall = 1; + list Defs = [RA]; +} +class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>; + +//===----------------------------------------------------------------------===// +// +// Instruction Definitions +// +//===----------------------------------------------------------------------===// + +def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6; +def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6; Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -289,7 +289,8 @@ bit hasDelaySlot = 0; } -class BC_DESC_BASE : BRANCH_DESC_BASE { +class BC_DESC_BASE : BRANCH_DESC_BASE, + MipsR6Arch { dag InOperandList = (ins opnd:$offset); dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$offset"); @@ -648,12 +649,12 @@ def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6; def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; -def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6; +def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6; def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6; def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; -def BC : BC_ENC, BC_DESC, ISA_MIPS32R6; +def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1909,3 +1909,7 @@ include "MicroMipsInstrFormats.td" include "MicroMipsInstrInfo.td" include "MicroMipsInstrFPU.td" + +// Micromips r6 +include "MicroMips32r6InstrFormats.td" +include "MicroMips32r6InstrInfo.td" Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips32r6/valid.s @@ -0,0 +1,5 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips32r6 | FileCheck %s + + .set noat + balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]