Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -180,8 +180,11 @@
       (Opcode != Mips::SLL_MM) && !Binary)
     llvm_unreachable("unimplemented opcode in EncodeInstruction()");
 
-  if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
-    int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
+  if ((STI.getFeatureBits() & Mips::FeatureMicroMips) ||
+      (STI.getFeatureBits() & Mips::FeatureMicroMipsR6)) {
+    int NewOpcode = (STI.getFeatureBits() & Mips::FeatureMicroMips) ?
+                    Mips::Std2MicroMips(Opcode, Mips::Arch_micromips) :
+                    Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
     if (NewOpcode != -1) {
       if (Fixups.size() > N)
         Fixups.pop_back();
Index: lib/Target/Mips/MicroMipsR6InstrFormats.td
===================================================================
--- /dev/null
+++ lib/Target/Mips/MicroMipsR6InstrFormats.td
@@ -0,0 +1,17 @@
+//=- MicroMipsR6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes microMIPSr6 instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class MMR6Arch<string opstr> {
+  string Arch = "micromipsr6";
+  string BaseOpcode = opstr;
+}
Index: lib/Target/Mips/Mips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrFormats.td
+++ lib/Target/Mips/Mips32r6InstrFormats.td
@@ -11,6 +11,25 @@
 //
 //===----------------------------------------------------------------------===//
 
+class MMR6Rel;
+
+def MipsR62MicroMipsR6 : InstrMapping {
+  let FilterClass = "MMR6Rel";
+  // Instructions with the same BaseOpcode and isNVStore values form a row.
+  let RowFields = ["BaseOpcode"];
+  // Instructions with the same predicate sense form a column.
+  let ColFields = ["Arch"];
+  // The key column is the unpredicated instructions.
+  let KeyCol = ["mips32r6"];
+  // Value columns are PredSense=true and PredSense=false
+  let ValueCols = [["mips32r6"], ["micromipsr6"]];
+}
+
+class Mips32r6Arch<string opstr> {
+  string Arch = "mips32r6";
+  string BaseOpcode = opstr;
+}
+
 class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
                    PredicateControl {
   let DecoderNamespace = "Mips32r6_64r6";