Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -38,6 +38,7 @@
   bool IsLittleEndian;
 
   bool isMicroMips(const MCSubtargetInfo &STI) const;
+  bool isMicroMipsR6(const MCSubtargetInfo &STI) const;
 
 public:
   MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -115,6 +115,10 @@
   return STI.getFeatureBits() & Mips::FeatureMicroMips;
 }
 
+bool MipsMCCodeEmitter::isMicroMipsR6(const MCSubtargetInfo &STI) const {
+  return STI.getFeatureBits() & Mips::FeatureMicroMipsR6;
+}
+
 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
   OS << (char)C;
 }
@@ -126,7 +130,8 @@
   // Little-endian byte ordering:
   //   mips32r2:   4 | 3 | 2 | 1
   //   microMIPS:  2 | 1 | 4 | 3
-  if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
+  if (IsLittleEndian && Size == 4 &&
+      (isMicroMips(STI) || isMicroMipsR6(STI))) {
     EmitInstruction(Val >> 16, 2, STI, OS);
     EmitInstruction(Val, 2, STI, OS);
   } else {
Index: lib/Target/Mips/Mips.td
===================================================================
--- lib/Target/Mips/Mips.td
+++ lib/Target/Mips/Mips.td
@@ -155,6 +155,9 @@
 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
                                          "microMips mode">;
 
+def FeatureMicroMipsR6 : SubtargetFeature<"micromipsr6", "InMicroMipsR6Mode",
+                                          "true", "microMIPSr6 mode">;
+
 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
                                 "true", "Octeon cnMIPS Support",
                                 [FeatureMips64r2]>;
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -182,6 +182,8 @@
                       AssemblerPredicate<"FeatureMips64r6">;
 def NotMips64r6  :    Predicate<"!Subtarget->hasMips64r6()">,
                       AssemblerPredicate<"!FeatureMips64r6">;
+def HasMicroMipsR6 :  Predicate<"Subtarget->inMicroMipsR6Mode()">,
+                      AssemblerPredicate<"FeatureMicroMipsR6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
@@ -249,6 +251,7 @@
 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
+class ISA_MICROMIPSR6 { list<Predicate> InsnPredicates = [HasMicroMipsR6]; }
 
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
Index: lib/Target/Mips/MipsSubtarget.h
===================================================================
--- lib/Target/Mips/MipsSubtarget.h
+++ lib/Target/Mips/MipsSubtarget.h
@@ -113,6 +113,9 @@
   // InMicroMips -- can process MicroMips instructions
   bool InMicroMipsMode;
 
+  // InMicroMipsR6 -- can process MicroMips r6 instructions
+  bool InMicroMipsR6Mode;
+
   // HasDSP, HasDSPR2 -- supports DSP ASE.
   bool HasDSP, HasDSPR2;
 
@@ -225,6 +228,7 @@
     return inMips16Mode() && InMips16HardFloat;
   }
   bool inMicroMipsMode() const { return InMicroMipsMode; }
+  bool inMicroMipsR6Mode() const { return InMicroMipsR6Mode; }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasMSA() const { return HasMSA; }
Index: lib/Target/Mips/MipsSubtarget.cpp
===================================================================
--- lib/Target/Mips/MipsSubtarget.cpp
+++ lib/Target/Mips/MipsSubtarget.cpp
@@ -68,8 +68,9 @@
       IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasMips3_32(false),
       HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false),
       HasMips5_32r2(false), InMips16Mode(false),
-      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
-      HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
+      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false),
+      InMicroMipsR6Mode(false), HasDSP(false), HasDSPR2(false),
+      AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
       HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(*TM.getDataLayout()),
       InstrInfo(
           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),