Index: llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -580,6 +580,10 @@ case Intrinsic::fma: // TODO: fmuladd // There's a small benefit to using vector ops in the legalized code. case Intrinsic::round: + case Intrinsic::uadd_sat: + case Intrinsic::usub_sat: + case Intrinsic::sadd_sat: + case Intrinsic::ssub_sat: return true; default: return false; Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -486,6 +486,19 @@ if (Subtarget->hasBFE()) setHasExtractBitsInsn(true); + // Clamp modifier on add/sub + if (Subtarget->hasIntClamp()) { + setOperationAction(ISD::UADDSAT, MVT::i32, Legal); + setOperationAction(ISD::USUBSAT, MVT::i32, Legal); + } + + if (Subtarget->hasNoCarryAddSubSat()) { + setOperationAction(ISD::SADDSAT, MVT::i16, Legal); + setOperationAction(ISD::SSUBSAT, MVT::i16, Legal); + setOperationAction(ISD::SADDSAT, MVT::i32, Legal); + setOperationAction(ISD::SSUBSAT, MVT::i32, Legal); + } + setOperationAction(ISD::FMINNUM, MVT::f32, Custom); setOperationAction(ISD::FMAXNUM, MVT::f32, Custom); setOperationAction(ISD::FMINNUM, MVT::f64, Custom); @@ -538,6 +551,8 @@ setOperationAction(ISD::UDIV, MVT::i16, Promote); setOperationAction(ISD::SREM, MVT::i16, Promote); setOperationAction(ISD::UREM, MVT::i16, Promote); + setOperationAction(ISD::UADDSAT, MVT::i16, Legal); + setOperationAction(ISD::USUBSAT, MVT::i16, Legal); setOperationAction(ISD::BITREVERSE, MVT::i16, Promote); @@ -702,6 +717,11 @@ setOperationAction(ISD::SMAX, MVT::v2i16, Legal); setOperationAction(ISD::UMAX, MVT::v2i16, Legal); + setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal); + setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal); + setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal); + setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal); + setOperationAction(ISD::FADD, MVT::v2f16, Legal); setOperationAction(ISD::FMUL, MVT::v2f16, Legal); setOperationAction(ISD::FMA, MVT::v2f16, Legal); @@ -729,6 +749,11 @@ setOperationAction(ISD::UMIN, MVT::v4i16, Custom); setOperationAction(ISD::UMAX, MVT::v4i16, Custom); + setOperationAction(ISD::UADDSAT, MVT::v4i16, Custom); + setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom); + setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom); + setOperationAction(ISD::SSUBSAT, MVT::v4i16, Custom); + setOperationAction(ISD::FADD, MVT::v4f16, Custom); setOperationAction(ISD::FMUL, MVT::v4f16, Custom); setOperationAction(ISD::FMA, MVT::v4f16, Custom); @@ -4457,6 +4482,10 @@ case ISD::FMUL: case ISD::FMINNUM_IEEE: case ISD::FMAXNUM_IEEE: + case ISD::UADDSAT: + case ISD::USUBSAT: + case ISD::SADDSAT: + case ISD::SSUBSAT: return splitBinaryVectorOp(Op, DAG); case ISD::SMULO: case ISD::UMULO: Index: llvm/test/CodeGen/AMDGPU/saddo.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/saddo.ll +++ llvm/test/CodeGen/AMDGPU/saddo.ll @@ -136,17 +136,16 @@ ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s4 -; GFX9-NEXT: v_cmp_lt_i32_e64 s[2:3], s1, 0 -; GFX9-NEXT: s_add_i32 s1, s0, s1 -; GFX9-NEXT: v_mov_b32_e32 v4, s0 -; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, s1, v4 ; GFX9-NEXT: v_mov_b32_e32 v4, s1 +; GFX9-NEXT: v_add_i32 v4, s0, v4 clamp +; GFX9-NEXT: s_add_i32 s0, s0, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: s_xor_b64 s[0:1], s[2:3], vcc -; GFX9-NEXT: global_store_dword v[0:1], v4, off +; GFX9-NEXT: v_mov_b32_e32 v5, s0 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, s0, v4 +; GFX9-NEXT: global_store_dword v[0:1], v5, off ; GFX9-NEXT: v_mov_b32_e32 v2, s6 ; GFX9-NEXT: v_mov_b32_e32 v3, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: global_store_byte v[2:3], v0, off ; GFX9-NEXT: s_endpgm %sadd = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) nounwind @@ -229,12 +228,11 @@ ; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_u32_e32 v6, v4, v5 -; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v5 -; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], v6, v4 -; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[0:1] -; GFX9-NEXT: global_store_dword v[0:1], v6, off -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX9-NEXT: v_add_i32 v6, v4, v5 clamp +; GFX9-NEXT: v_add_u32_e32 v4, v4, v5 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v4, v6 +; GFX9-NEXT: global_store_dword v[0:1], v4, off +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: global_store_byte v[2:3], v0, off ; GFX9-NEXT: s_endpgm %a = load i32, i32 addrspace(1)* %aptr, align 4 @@ -501,17 +499,15 @@ ; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_u32_e32 v9, v5, v7 -; GFX9-NEXT: v_add_u32_e32 v8, v4, v6 -; GFX9-NEXT: v_cmp_gt_i32_e64 s[0:1], 0, v7 -; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v9, v5 -; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v6 -; GFX9-NEXT: v_cmp_lt_i32_e64 s[2:3], v8, v4 -; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5] -; GFX9-NEXT: global_store_dwordx2 v[0:1], v[8:9], off -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] -; GFX9-NEXT: s_xor_b64 s[0:1], vcc, s[2:3] -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX9-NEXT: v_add_i32 v8, v4, v6 clamp +; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 +; GFX9-NEXT: v_add_i32 v6, v5, v7 clamp +; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v5, v6 +; GFX9-NEXT: global_store_dwordx2 v[0:1], v[4:5], off +; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v4, v8 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; GFX9-NEXT: s_endpgm %a = load <2 x i32>, <2 x i32> addrspace(1)* %aptr, align 4 Index: llvm/test/CodeGen/AMDGPU/saddsat.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AMDGPU/saddsat.ll @@ -0,0 +1,439 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) { +; GFX6-LABEL: v_saddsat_i8: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0 +; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_i8: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0 +; GFX8-NEXT: v_max_i16_e32 v0, 0xffffff80, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs) + ret i8 %result +} + +define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) { +; GFX6-LABEL: v_saddsat_i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 +; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1 +; GFX8-NEXT: v_add_u16_e32 v1, v0, v1 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) + ret i16 %result +} + +define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) { +; GFX6-LABEL: v_saddsat_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 +; GFX6-NEXT: v_add_i32_e64 v1, s[4:5], v0, v1 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v0, v1 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) + ret i32 %result +} + +define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { +; GFX6-LABEL: v_saddsat_v2i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_v2i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX8-NEXT: v_add_u16_e32 v4, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v5, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v6, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v4 +; GFX8-NEXT: v_cndmask_b32_e32 v7, v5, v6, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1 +; GFX8-NEXT: v_add_u16_e32 v1, v0, v1 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_v2i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) + ret <2 x i16> %result +} + +define <3 x i16> @v_saddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { +; GFX6-LABEL: v_saddsat_v3i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v5 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v1 +; GFX6-NEXT: v_alignbit_b32 v1, v1, v0, 16 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_v3i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_add_u16_e32 v6, v5, v4 +; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 +; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3 +; GFX8-NEXT: v_add_u16_e32 v3, v1, v3 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2 +; GFX8-NEXT: v_add_u16_e32 v2, v0, v2 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_v3i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp +; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) + ret <3 x i16> %result +} + +define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { +; GFX6-LABEL: v_saddsat_v4i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: s_mov_b32 s6, 0xffff +; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s6, v0 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v7 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: v_min_i32_e32 v2, s4, v2 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v2, s5, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v2, s6, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_v4i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_add_u16_e32 v6, v5, v4 +; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 +; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2 +; GFX8-NEXT: v_add_u16_e32 v2, v0, v2 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX8-NEXT: v_add_u16_e32 v5, v4, v2 +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3 +; GFX8-NEXT: v_add_u16_e32 v3, v1, v3 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) + %cast = bitcast <4 x i16> %result to <2 x float> + ret <2 x float> %cast +} + +define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { +; GFX6-LABEL: v_saddsat_v2i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2 +; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v5, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3 +; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_v2i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2 +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v5, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3 +; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) + ret <2 x i32> %result +} + +define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) { +; GFX6-LABEL: v_saddsat_i64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v0, v2 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc +; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] +; GFX6-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_saddsat_i64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e32 v4, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] +; GFX8-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_saddsat_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3] +; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs) + ret i64 %result +} + +declare i8 @llvm.sadd.sat.i8(i8, i8) #0 +declare i16 @llvm.sadd.sat.i16(i16, i16) #0 +declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>) #0 +declare <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16>, <3 x i16>) #0 +declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>) #0 +declare i32 @llvm.sadd.sat.i32(i32, i32) #0 +declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>) #0 +declare i64 @llvm.sadd.sat.i64(i64, i64) #0 Index: llvm/test/CodeGen/AMDGPU/ssubsat.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AMDGPU/ssubsat.ll @@ -0,0 +1,1004 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) { +; GFX6-LABEL: v_ssubsat_i8: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0 +; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_i8: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0 +; GFX8-NEXT: v_max_i16_e32 v0, 0xffffff80, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) + ret i8 %result +} + +define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) { +; GFX6-LABEL: v_ssubsat_i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0 +; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 +; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v2, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) + ret i16 %result +} + +define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) { +; GFX6-LABEL: v_ssubsat_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 +; GFX6-NEXT: v_sub_i32_e64 v1, s[4:5], v0, v1 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v1 +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v0, v1 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) + ret i32 %result +} + +define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { +; GFX6-LABEL: v_ssubsat_v2i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v2i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX8-NEXT: v_sub_u16_e32 v4, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v5, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v6, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v4 +; GFX8-NEXT: v_cndmask_b32_e32 v7, v5, v6, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v1 +; GFX8-NEXT: v_sub_u16_e32 v1, v0, v1 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v1 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v5, v6, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v2i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) + ret <2 x i16> %result +} + +define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { +; GFX6-LABEL: v_ssubsat_v3i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: s_mov_b32 s6, 0xffff +; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s6, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v2, v5 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_and_b32_e32 v2, s6, v1 +; GFX6-NEXT: v_alignbit_b32 v1, v1, v0, 16 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v3i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 +; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 +; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 +; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 +; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v3i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) + ret <3 x i16> %result +} + +define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { +; GFX6-LABEL: v_ssubsat_v4i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16 +; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16 +; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: s_movk_i32 s4, 0x7fff +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: s_movk_i32 s5, 0x8000 +; GFX6-NEXT: v_min_i32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v0, s5, v0 +; GFX6-NEXT: s_mov_b32 s6, 0xffff +; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16 +; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16 +; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s6, v0 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v3, v7 +; GFX6-NEXT: v_min_i32_e32 v1, s4, v1 +; GFX6-NEXT: v_min_i32_e32 v2, s4, v2 +; GFX6-NEXT: v_max_i32_e32 v1, s5, v1 +; GFX6-NEXT: v_max_i32_e32 v2, s5, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v2, s6, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v4i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0 +; GFX8-NEXT: v_sub_u16_e32 v6, v5, v4 +; GFX8-NEXT: v_mov_b32_e32 v7, 0xffff8000 +; GFX8-NEXT: v_mov_b32_e32 v8, 0x7fff +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v6 +; GFX8-NEXT: v_cndmask_b32_e32 v9, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v4 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v9, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v2 +; GFX8-NEXT: v_sub_u16_e32 v2, v0, v2 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX8-NEXT: v_sub_u16_e32 v5, v4, v2 +; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v5 +; GFX8-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], 0, v2 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc +; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, 0, v3 +; GFX8-NEXT: v_sub_u16_e32 v3, v1, v3 +; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1 +; GFX8-NEXT: v_cmp_gt_i16_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v7, v8, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) + %cast = bitcast <4 x i16> %result to <2 x float> + ret <2 x float> %cast +} + +define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { +; GFX6-LABEL: v_ssubsat_v2i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 +; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v0, v2 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v5, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX6-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v2i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v2 +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v0, v2 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v4, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v5, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v4, v5, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v1, v3 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v2 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v5, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) + ret <2 x i32> %result +} + +define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { +; GFX6-LABEL: v_ssubsat_v3i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 +; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v3 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v6, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v7, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v4 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v6, v7, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX6-NEXT: v_sub_i32_e64 v3, s[4:5], v2, v5 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX6-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v3i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v3 +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v0, v3 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v6, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v7, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v6, v7, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v1, v4 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v6, v7, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v2, v5 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v3 +; GFX8-NEXT: v_cndmask_b32_e64 v2, v6, v7, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v3i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) + ret <3 x i32> %result +} + +define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { +; GFX6-LABEL: v_ssubsat_v4i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 +; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v0, v4 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v9, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v8, v9, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v1, v5 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v8, v9, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v2, v6 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v2, v8, v9, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX6-NEXT: v_sub_i32_e64 v4, s[4:5], v3, v7 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, v9, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v4i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v4 +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v0, v4 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v8, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v9, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v8, v9, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v1, v5 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v5 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v8, v9, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v2, v6 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v6 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v2, v8, v9, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v3, v7 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v7 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v4, v3 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v4 +; GFX8-NEXT: v_cndmask_b32_e64 v3, v8, v9, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v4i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) + ret <4 x i32> %result +} + +define <8 x i32> @v_ssubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { +; GFX6-LABEL: v_ssubsat_v8i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v8 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v16, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v17, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v1, v9 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v2, v10 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v2, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v3, v11 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v3, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v4, v12 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v4, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v13 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v5, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v6, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc +; GFX6-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v15 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v7, v16, v17, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v8i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v8 +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v0, v8 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v16, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v17, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v1, v9 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v9 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v2, v10 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v10 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v2, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v3, v11 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v11 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v3 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v3, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v4, v12 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v12 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v4 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v4, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v5, v13 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v13 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v5 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v5, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v6, v14 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v14 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v6 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v6, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v7, v15 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v15 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v8, v7 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v8 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v16, v17, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v8i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v8 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v9 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v10 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v11 clamp +; GFX9-NEXT: v_sub_i32 v4, v4, v12 clamp +; GFX9-NEXT: v_sub_i32 v5, v5, v13 clamp +; GFX9-NEXT: v_sub_i32 v6, v6, v14 clamp +; GFX9-NEXT: v_sub_i32 v7, v7, v15 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs) + ret <8 x i32> %result +} + +define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { +; GFX6-LABEL: v_ssubsat_v16i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v0, v16 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 +; GFX6-NEXT: v_bfrev_b32_e32 v32, 1 +; GFX6-NEXT: v_bfrev_b32_e32 v33, -2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v0, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v1, v17 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v2, v18 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v2, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v3, v19 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v3, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v4, v20 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v4, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v5, v21 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v5 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v5, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v6, v22 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v6 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v6, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v7, v23 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v7 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v7, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v8, v24 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v8 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v8, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v9, v25 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v9 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v9, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v10, v26 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v10 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v10, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v10, v16, v10, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v11, v27 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v11 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v11, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v12, v28 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v12 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v12, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v13, v29 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v13 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v13, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v14, v30 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v14 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v14, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v14, v16, v14, vcc +; GFX6-NEXT: v_sub_i32_e64 v16, s[4:5], v15, v31 +; GFX6-NEXT: v_cmp_lt_i32_e32 vcc, 0, v31 +; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 +; GFX6-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX6-NEXT: v_cndmask_b32_e64 v15, v32, v33, s[6:7] +; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_v16i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v16 +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v0, v16 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v32, 1 +; GFX8-NEXT: v_bfrev_b32_e32 v33, -2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v0, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v1, v17 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v17 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v1 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v1, v16, v1, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v2, v18 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v18 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v2 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v2, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v2, v16, v2, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v3, v19 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v19 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v3 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v3, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v3, v16, v3, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v4, v20 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v20 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v4 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v4, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v5, v21 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v21 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v5 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v5, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v5, v16, v5, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v6, v22 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v22 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v6 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v6, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v6, v16, v6, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v7, v23 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v23 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v7 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v7, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v7, v16, v7, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v8, v24 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v24 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v8 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v8, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v9, v25 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v25 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v9 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v9, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v10, v26 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v26 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v10 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v10, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v10, v16, v10, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v11, v27 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v27 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v11 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v11, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v12, v28 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v28 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v12 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v12, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v12, v16, v12, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v13, v29 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v29 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v13 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v13, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v14, v30 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v30 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v14 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v14, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v14, v16, v14, vcc +; GFX8-NEXT: v_sub_u32_e64 v16, s[4:5], v15, v31 +; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, 0, v31 +; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v16, v15 +; GFX8-NEXT: v_cmp_gt_i32_e64 s[6:7], 0, v16 +; GFX8-NEXT: v_cndmask_b32_e64 v15, v32, v33, s[6:7] +; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v15, v16, v15, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_v16i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp +; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp +; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp +; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp +; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp +; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp +; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp +; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp +; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp +; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp +; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp +; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp +; GFX9-NEXT: v_sub_i32 v15, v15, v31 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) + ret <16 x i32> %result +} + + +define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) { +; GFX6-LABEL: v_ssubsat_i64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 +; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc +; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] +; GFX6-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX6-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_ssubsat_i64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2 +; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] +; GFX8-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX8-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_ssubsat_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2 +; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1] +; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3] +; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc +; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] +; GFX9-NEXT: v_bfrev_b32_e32 v2, -2 +; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs) + ret i64 %result +} + +declare i8 @llvm.ssub.sat.i8(i8, i8) #0 +declare i16 @llvm.ssub.sat.i16(i16, i16) #0 +declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #0 +declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0 +declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #0 +declare i32 @llvm.ssub.sat.i32(i32, i32) #0 +declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #0 +declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #0 +declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #0 +declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>) #0 +declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #0 +declare i64 @llvm.ssub.sat.i64(i64, i64) #0 + +attributes #0 = { nounwind readnone speculatable willreturn } Index: llvm/test/CodeGen/AMDGPU/uaddsat.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AMDGPU/uaddsat.ll @@ -0,0 +1,522 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) { +; GFX6-LABEL: v_uaddsat_i8: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_movk_i32 s4, 0xff +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_u32_e32 v0, s4, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_i8: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs) + ret i8 %result +} + +define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) { +; GFX6-LABEL: v_uaddsat_i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: v_min_u32_e32 v0, s4, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) + ret i16 %result +} + +define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) { +; GFX6-LABEL: v_uaddsat_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v2, v1 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v2 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) + ret i32 %result +} + +define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { +; GFX6-LABEL: v_uaddsat_v2i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_min_u32_e32 v1, s4, v1 +; GFX6-NEXT: v_min_u32_e32 v0, s4, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v2i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v2i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) + ret <2 x i16> %result +} + +define <3 x i16> @v_uaddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { +; GFX6-LABEL: v_uaddsat_v3i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_min_u32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_min_u32_e32 v0, s4, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v5 +; GFX6-NEXT: v_min_u32_e32 v1, s4, v1 +; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v1 +; GFX6-NEXT: v_alignbit_b32 v1, v1, v0, 16 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v3i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp +; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v3i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp +; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) + ret <3 x i16> %result +} + +define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { +; GFX6-LABEL: v_uaddsat_v4i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v5, s4, v5 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: v_and_b32_e32 v4, s4, v4 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_min_u32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v7, s4, v7 +; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 +; GFX6-NEXT: v_and_b32_e32 v6, s4, v6 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_min_u32_e32 v0, s4, v0 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v6 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v7 +; GFX6-NEXT: v_min_u32_e32 v2, s4, v2 +; GFX6-NEXT: v_min_u32_e32 v1, s4, v1 +; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v4i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v2 clamp +; GFX8-NEXT: v_add_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v1, v1, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) + %cast = bitcast <4 x i16> %result to <2 x float> + ret <2 x float> %cast +} + +define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { +; GFX6-LABEL: v_uaddsat_v2i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v4, v2 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v4 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_not_b32_e32 v2, v3 +; GFX6-NEXT: v_min_u32_e32 v1, v1, v2 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v2i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v2 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v3 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v2 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) + ret <2 x i32> %result +} + +define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { +; GFX6-LABEL: v_uaddsat_v3i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v6, v3 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v6 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_not_b32_e32 v3, v4 +; GFX6-NEXT: v_min_u32_e32 v1, v1, v3 +; GFX6-NEXT: v_not_b32_e32 v3, v5 +; GFX6-NEXT: v_min_u32_e32 v2, v2, v3 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v3i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v3 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v4 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v5 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v3i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v3 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v4 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) + ret <3 x i32> %result +} + +define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { +; GFX6-LABEL: v_uaddsat_v4i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v8, v4 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v8 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_not_b32_e32 v4, v5 +; GFX6-NEXT: v_min_u32_e32 v1, v1, v4 +; GFX6-NEXT: v_not_b32_e32 v4, v6 +; GFX6-NEXT: v_min_u32_e32 v2, v2, v4 +; GFX6-NEXT: v_not_b32_e32 v4, v7 +; GFX6-NEXT: v_min_u32_e32 v3, v3, v4 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v4i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v4 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v5 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v6 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v7 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v4i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v4 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v5 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v6 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) + ret <4 x i32> %result +} + +define <8 x i32> @v_uaddsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { +; GFX6-LABEL: v_uaddsat_v8i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v16, v8 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v16 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v9 +; GFX6-NEXT: v_min_u32_e32 v1, v1, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v10 +; GFX6-NEXT: v_min_u32_e32 v2, v2, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v11 +; GFX6-NEXT: v_min_u32_e32 v3, v3, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v12 +; GFX6-NEXT: v_min_u32_e32 v4, v4, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v13 +; GFX6-NEXT: v_min_u32_e32 v5, v5, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v14 +; GFX6-NEXT: v_min_u32_e32 v6, v6, v8 +; GFX6-NEXT: v_not_b32_e32 v8, v15 +; GFX6-NEXT: v_min_u32_e32 v7, v7, v8 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v9 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v10 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v11 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v12 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v13 +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v14 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v15 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v8i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v8 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v9 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v10 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v11 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v12 clamp +; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v13 clamp +; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v14 clamp +; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v15 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v8i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v8 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v9 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v10 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v11 clamp +; GFX9-NEXT: v_add_u32_e64 v4, v4, v12 clamp +; GFX9-NEXT: v_add_u32_e64 v5, v5, v13 clamp +; GFX9-NEXT: v_add_u32_e64 v6, v6, v14 clamp +; GFX9-NEXT: v_add_u32_e64 v7, v7, v15 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs) + ret <8 x i32> %result +} + +define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { +; GFX6-LABEL: v_uaddsat_v16i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_not_b32_e32 v32, v16 +; GFX6-NEXT: v_min_u32_e32 v0, v0, v32 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v17 +; GFX6-NEXT: v_min_u32_e32 v1, v1, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v18 +; GFX6-NEXT: v_min_u32_e32 v2, v2, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v19 +; GFX6-NEXT: v_min_u32_e32 v3, v3, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v20 +; GFX6-NEXT: v_min_u32_e32 v4, v4, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v21 +; GFX6-NEXT: v_min_u32_e32 v5, v5, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v22 +; GFX6-NEXT: v_min_u32_e32 v6, v6, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v23 +; GFX6-NEXT: v_min_u32_e32 v7, v7, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v24 +; GFX6-NEXT: v_min_u32_e32 v8, v8, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v25 +; GFX6-NEXT: v_min_u32_e32 v9, v9, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v26 +; GFX6-NEXT: v_min_u32_e32 v10, v10, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v27 +; GFX6-NEXT: v_min_u32_e32 v11, v11, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v28 +; GFX6-NEXT: v_min_u32_e32 v12, v12, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v29 +; GFX6-NEXT: v_min_u32_e32 v13, v13, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v30 +; GFX6-NEXT: v_min_u32_e32 v14, v14, v16 +; GFX6-NEXT: v_not_b32_e32 v16, v31 +; GFX6-NEXT: v_min_u32_e32 v15, v15, v16 +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v17 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v18 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v19 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v20 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v21 +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v22 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v23 +; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v24 +; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v25 +; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v26 +; GFX6-NEXT: v_add_i32_e32 v11, vcc, v11, v27 +; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v28 +; GFX6-NEXT: v_add_i32_e32 v13, vcc, v13, v29 +; GFX6-NEXT: v_add_i32_e32 v14, vcc, v14, v30 +; GFX6-NEXT: v_add_i32_e32 v15, vcc, v15, v31 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_v16i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v16 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v17 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v18 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v19 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v20 clamp +; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v21 clamp +; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v22 clamp +; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v23 clamp +; GFX8-NEXT: v_add_u32_e64 v8, s[4:5], v8, v24 clamp +; GFX8-NEXT: v_add_u32_e64 v9, s[4:5], v9, v25 clamp +; GFX8-NEXT: v_add_u32_e64 v10, s[4:5], v10, v26 clamp +; GFX8-NEXT: v_add_u32_e64 v11, s[4:5], v11, v27 clamp +; GFX8-NEXT: v_add_u32_e64 v12, s[4:5], v12, v28 clamp +; GFX8-NEXT: v_add_u32_e64 v13, s[4:5], v13, v29 clamp +; GFX8-NEXT: v_add_u32_e64 v14, s[4:5], v14, v30 clamp +; GFX8-NEXT: v_add_u32_e64 v15, s[4:5], v15, v31 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_v16i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e64 v0, v0, v16 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v17 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v18 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v19 clamp +; GFX9-NEXT: v_add_u32_e64 v4, v4, v20 clamp +; GFX9-NEXT: v_add_u32_e64 v5, v5, v21 clamp +; GFX9-NEXT: v_add_u32_e64 v6, v6, v22 clamp +; GFX9-NEXT: v_add_u32_e64 v7, v7, v23 clamp +; GFX9-NEXT: v_add_u32_e64 v8, v8, v24 clamp +; GFX9-NEXT: v_add_u32_e64 v9, v9, v25 clamp +; GFX9-NEXT: v_add_u32_e64 v10, v10, v26 clamp +; GFX9-NEXT: v_add_u32_e64 v11, v11, v27 clamp +; GFX9-NEXT: v_add_u32_e64 v12, v12, v28 clamp +; GFX9-NEXT: v_add_u32_e64 v13, v13, v29 clamp +; GFX9-NEXT: v_add_u32_e64 v14, v14, v30 clamp +; GFX9-NEXT: v_add_u32_e64 v15, v15, v31 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) + ret <16 x i32> %result +} + + +define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) { +; GFX6-LABEL: v_uaddsat_i64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v0, v2 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc +; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] +; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_uaddsat_i64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v2 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v1, v3, vcc +; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] +; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_uaddsat_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v3, vcc +; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, -1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs) + ret i64 %result +} + +declare i8 @llvm.uadd.sat.i8(i8, i8) #0 +declare i16 @llvm.uadd.sat.i16(i16, i16) #0 +declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #0 +declare <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16>, <3 x i16>) #0 +declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>) #0 +declare i32 @llvm.uadd.sat.i32(i32, i32) #0 +declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>) #0 +declare <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32>, <3 x i32>) #0 +declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #0 +declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>) #0 +declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>) #0 +declare i64 @llvm.uadd.sat.i64(i64, i64) #0 + +attributes #0 = { nounwind readnone speculatable willreturn } Index: llvm/test/CodeGen/AMDGPU/usubsat.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AMDGPU/usubsat.ll @@ -0,0 +1,492 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) { +; GFX6-LABEL: v_usubsat_i8: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_movk_i32 s4, 0xff +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_u32_e32 v0, v0, v1 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_i8: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 +; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs) + ret i8 %result +} + +define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) { +; GFX6-LABEL: v_usubsat_i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_u32_e32 v0, v0, v1 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) + ret i16 %result +} + +define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) { +; GFX6-LABEL: v_usubsat_i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v1 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) + ret i32 %result +} + +define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) { +; GFX6-LABEL: v_usubsat_v2i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v4, s4, v2 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_and_b32_e32 v5, s4, v3 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v5 +; GFX6-NEXT: v_max_u32_e32 v0, v0, v4 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v2i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u16_sdwa v2, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v2i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) + ret <2 x i16> %result +} + +define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) { +; GFX6-LABEL: v_usubsat_v3i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v7, s4, v3 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_and_b32_e32 v8, s4, v4 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v8 +; GFX6-NEXT: v_max_u32_e32 v0, v0, v7 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_and_b32_e32 v6, s4, v5 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_max_u32_e32 v1, v2, v6 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v1 +; GFX6-NEXT: v_alignbit_b32 v1, v1, v0, 16 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v3i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp +; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v3i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs) + ret <3 x i16> %result +} + +define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) { +; GFX6-LABEL: v_usubsat_v4i16: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: s_mov_b32 s4, 0xffff +; GFX6-NEXT: v_and_b32_e32 v10, s4, v4 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_and_b32_e32 v11, s4, v5 +; GFX6-NEXT: v_and_b32_e32 v1, s4, v1 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v11 +; GFX6-NEXT: v_max_u32_e32 v0, v0, v10 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_and_b32_e32 v8, s4, v6 +; GFX6-NEXT: v_and_b32_e32 v2, s4, v2 +; GFX6-NEXT: v_and_b32_e32 v9, s4, v7 +; GFX6-NEXT: v_and_b32_e32 v3, s4, v3 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v0, s4, v0 +; GFX6-NEXT: v_max_u32_e32 v2, v2, v8 +; GFX6-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX6-NEXT: v_max_u32_e32 v1, v3, v9 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v7 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX6-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v4i16: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u16_sdwa v4, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v2 clamp +; GFX8-NEXT: v_sub_u16_sdwa v2, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v1, v1, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v4i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) + %cast = bitcast <4 x i16> %result to <2 x float> + ret <2 x float> %cast +} + +define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) { +; GFX6-LABEL: v_usubsat_v2i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v2 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v3 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v2i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v2i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v2 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v3 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) + ret <2 x i32> %result +} + +define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) { +; GFX6-LABEL: v_usubsat_v3i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v3 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v4 +; GFX6-NEXT: v_max_u32_e32 v2, v2, v5 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v3i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v3i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v3 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v4 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v5 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) + ret <3 x i32> %result +} + +define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) { +; GFX6-LABEL: v_usubsat_v4i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v4 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v5 +; GFX6-NEXT: v_max_u32_e32 v2, v2, v6 +; GFX6-NEXT: v_max_u32_e32 v3, v3, v7 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v7 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v4i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v7 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v4i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v4 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v5 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v6 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v7 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) + ret <4 x i32> %result +} + +define <8 x i32> @v_usubsat_v8i32(<8 x i32> %lhs, <8 x i32> %rhs) { +; GFX6-LABEL: v_usubsat_v8i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v8 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v9 +; GFX6-NEXT: v_max_u32_e32 v2, v2, v10 +; GFX6-NEXT: v_max_u32_e32 v3, v3, v11 +; GFX6-NEXT: v_max_u32_e32 v4, v4, v12 +; GFX6-NEXT: v_max_u32_e32 v5, v5, v13 +; GFX6-NEXT: v_max_u32_e32 v6, v6, v14 +; GFX6-NEXT: v_max_u32_e32 v7, v7, v15 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v9 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v10 +; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v11 +; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v12 +; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v13 +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v14 +; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v15 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v8i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v8 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v9 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v10 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v11 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v12 clamp +; GFX8-NEXT: v_sub_u32_e64 v5, s[4:5], v5, v13 clamp +; GFX8-NEXT: v_sub_u32_e64 v6, s[4:5], v6, v14 clamp +; GFX8-NEXT: v_sub_u32_e64 v7, s[4:5], v7, v15 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v8i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v8 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v9 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v10 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v11 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, v4, v12 clamp +; GFX9-NEXT: v_sub_u32_e64 v5, v5, v13 clamp +; GFX9-NEXT: v_sub_u32_e64 v6, v6, v14 clamp +; GFX9-NEXT: v_sub_u32_e64 v7, v7, v15 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %lhs, <8 x i32> %rhs) + ret <8 x i32> %result +} + +define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) { +; GFX6-LABEL: v_usubsat_v16i32: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_max_u32_e32 v0, v0, v16 +; GFX6-NEXT: v_max_u32_e32 v1, v1, v17 +; GFX6-NEXT: v_max_u32_e32 v2, v2, v18 +; GFX6-NEXT: v_max_u32_e32 v3, v3, v19 +; GFX6-NEXT: v_max_u32_e32 v4, v4, v20 +; GFX6-NEXT: v_max_u32_e32 v5, v5, v21 +; GFX6-NEXT: v_max_u32_e32 v6, v6, v22 +; GFX6-NEXT: v_max_u32_e32 v7, v7, v23 +; GFX6-NEXT: v_max_u32_e32 v8, v8, v24 +; GFX6-NEXT: v_max_u32_e32 v9, v9, v25 +; GFX6-NEXT: v_max_u32_e32 v10, v10, v26 +; GFX6-NEXT: v_max_u32_e32 v11, v11, v27 +; GFX6-NEXT: v_max_u32_e32 v12, v12, v28 +; GFX6-NEXT: v_max_u32_e32 v13, v13, v29 +; GFX6-NEXT: v_max_u32_e32 v14, v14, v30 +; GFX6-NEXT: v_max_u32_e32 v15, v15, v31 +; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v16 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v17 +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v18 +; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v19 +; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v20 +; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v21 +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v22 +; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v23 +; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v24 +; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v25 +; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v26 +; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v27 +; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v28 +; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v29 +; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v30 +; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v31 +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_v16i32: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v19 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v20 clamp +; GFX8-NEXT: v_sub_u32_e64 v5, s[4:5], v5, v21 clamp +; GFX8-NEXT: v_sub_u32_e64 v6, s[4:5], v6, v22 clamp +; GFX8-NEXT: v_sub_u32_e64 v7, s[4:5], v7, v23 clamp +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v8, v24 clamp +; GFX8-NEXT: v_sub_u32_e64 v9, s[4:5], v9, v25 clamp +; GFX8-NEXT: v_sub_u32_e64 v10, s[4:5], v10, v26 clamp +; GFX8-NEXT: v_sub_u32_e64 v11, s[4:5], v11, v27 clamp +; GFX8-NEXT: v_sub_u32_e64 v12, s[4:5], v12, v28 clamp +; GFX8-NEXT: v_sub_u32_e64 v13, s[4:5], v13, v29 clamp +; GFX8-NEXT: v_sub_u32_e64 v14, s[4:5], v14, v30 clamp +; GFX8-NEXT: v_sub_u32_e64 v15, s[4:5], v15, v31 clamp +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_v16i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v16 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v17 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v18 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v19 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, v4, v20 clamp +; GFX9-NEXT: v_sub_u32_e64 v5, v5, v21 clamp +; GFX9-NEXT: v_sub_u32_e64 v6, v6, v22 clamp +; GFX9-NEXT: v_sub_u32_e64 v7, v7, v23 clamp +; GFX9-NEXT: v_sub_u32_e64 v8, v8, v24 clamp +; GFX9-NEXT: v_sub_u32_e64 v9, v9, v25 clamp +; GFX9-NEXT: v_sub_u32_e64 v10, v10, v26 clamp +; GFX9-NEXT: v_sub_u32_e64 v11, v11, v27 clamp +; GFX9-NEXT: v_sub_u32_e64 v12, v12, v28 clamp +; GFX9-NEXT: v_sub_u32_e64 v13, v13, v29 clamp +; GFX9-NEXT: v_sub_u32_e64 v14, v14, v30 clamp +; GFX9-NEXT: v_sub_u32_e64 v15, v15, v31 clamp +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) + ret <16 x i32> %result +} + + +define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) { +; GFX6-LABEL: v_usubsat_i64: +; GFX6: ; %bb.0: +; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v0, v2 +; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc +; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] +; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc +; GFX6-NEXT: s_setpc_b64 s[30:31] +; +; GFX8-LABEL: v_usubsat_i64: +; GFX8: ; %bb.0: +; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v2 +; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] +; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc +; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: v_usubsat_i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v0, v2 +; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, v[2:3], v[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v1, v3, 0, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs) + ret i64 %result +} + +declare i8 @llvm.usub.sat.i8(i8, i8) #0 +declare i16 @llvm.usub.sat.i16(i16, i16) #0 +declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #0 +declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #0 +declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #0 +declare i32 @llvm.usub.sat.i32(i32, i32) #0 +declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #0 +declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #0 +declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #0 +declare <8 x i32> @llvm.usub.sat.v8i32(<8 x i32>, <8 x i32>) #0 +declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #0 +declare i64 @llvm.usub.sat.i64(i64, i64) #0 + +attributes #0 = { nounwind readnone speculatable willreturn } Index: llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll =================================================================== --- /dev/null +++ llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll @@ -0,0 +1,303 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s + +define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { +; GFX7-LABEL: @uadd_sat_v2i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: ret <2 x i16> [[INS_1]] +; +; GFX8-LABEL: @uadd_sat_v2i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) +; GFX8-NEXT: ret <2 x i16> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i16> %arg0, i64 0 + %arg0.1 = extractelement <2 x i16> %arg0, i64 1 + %arg1.0 = extractelement <2 x i16> %arg1, i64 0 + %arg1.1 = extractelement <2 x i16> %arg1, i64 1 + %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1) + %ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1 + ret <2 x i16> %ins.1 +} + +define <2 x i16> @usub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { +; GFX7-LABEL: @usub_sat_v2i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: ret <2 x i16> [[INS_1]] +; +; GFX8-LABEL: @usub_sat_v2i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) +; GFX8-NEXT: ret <2 x i16> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i16> %arg0, i64 0 + %arg0.1 = extractelement <2 x i16> %arg0, i64 1 + %arg1.0 = extractelement <2 x i16> %arg1, i64 0 + %arg1.1 = extractelement <2 x i16> %arg1, i64 1 + %add.0 = call i16 @llvm.usub.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.usub.sat.i16(i16 %arg0.1, i16 %arg1.1) + %ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1 + ret <2 x i16> %ins.1 +} + +define <2 x i16> @sadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { +; GFX7-LABEL: @sadd_sat_v2i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: ret <2 x i16> [[INS_1]] +; +; GFX8-LABEL: @sadd_sat_v2i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) +; GFX8-NEXT: ret <2 x i16> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i16> %arg0, i64 0 + %arg0.1 = extractelement <2 x i16> %arg0, i64 1 + %arg1.0 = extractelement <2 x i16> %arg1, i64 0 + %arg1.1 = extractelement <2 x i16> %arg1, i64 1 + %add.0 = call i16 @llvm.sadd.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.sadd.sat.i16(i16 %arg0.1, i16 %arg1.1) + %ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1 + ret <2 x i16> %ins.1 +} + +define <2 x i16> @ssub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { +; GFX7-LABEL: @ssub_sat_v2i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: ret <2 x i16> [[INS_1]] +; +; GFX8-LABEL: @ssub_sat_v2i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) +; GFX8-NEXT: ret <2 x i16> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i16> %arg0, i64 0 + %arg0.1 = extractelement <2 x i16> %arg0, i64 1 + %arg1.0 = extractelement <2 x i16> %arg1, i64 0 + %arg1.1 = extractelement <2 x i16> %arg1, i64 1 + %add.0 = call i16 @llvm.ssub.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.ssub.sat.i16(i16 %arg0.1, i16 %arg1.1) + %ins.0 = insertelement <2 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1 + ret <2 x i16> %ins.1 +} + +; FIXME: Should not vectorize +define <2 x i32> @uadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { +; GCN-LABEL: @uadd_sat_v2i32( +; GCN-NEXT: bb: +; GCN-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[ARG0:%.*]], <2 x i32> [[ARG1:%.*]]) +; GCN-NEXT: ret <2 x i32> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i32> %arg0, i64 0 + %arg0.1 = extractelement <2 x i32> %arg0, i64 1 + %arg1.0 = extractelement <2 x i32> %arg1, i64 0 + %arg1.1 = extractelement <2 x i32> %arg1, i64 1 + %add.0 = call i32 @llvm.uadd.sat.i32(i32 %arg0.0, i32 %arg1.0) + %add.1 = call i32 @llvm.uadd.sat.i32(i32 %arg0.1, i32 %arg1.1) + %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 + %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 + ret <2 x i32> %ins.1 +} + +define <2 x i32> @usub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { +; GCN-LABEL: @usub_sat_v2i32( +; GCN-NEXT: bb: +; GCN-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> [[ARG0:%.*]], <2 x i32> [[ARG1:%.*]]) +; GCN-NEXT: ret <2 x i32> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i32> %arg0, i64 0 + %arg0.1 = extractelement <2 x i32> %arg0, i64 1 + %arg1.0 = extractelement <2 x i32> %arg1, i64 0 + %arg1.1 = extractelement <2 x i32> %arg1, i64 1 + %add.0 = call i32 @llvm.usub.sat.i32(i32 %arg0.0, i32 %arg1.0) + %add.1 = call i32 @llvm.usub.sat.i32(i32 %arg0.1, i32 %arg1.1) + %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 + %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 + ret <2 x i32> %ins.1 +} + +define <2 x i32> @sadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { +; GCN-LABEL: @sadd_sat_v2i32( +; GCN-NEXT: bb: +; GCN-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> [[ARG0:%.*]], <2 x i32> [[ARG1:%.*]]) +; GCN-NEXT: ret <2 x i32> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i32> %arg0, i64 0 + %arg0.1 = extractelement <2 x i32> %arg0, i64 1 + %arg1.0 = extractelement <2 x i32> %arg1, i64 0 + %arg1.1 = extractelement <2 x i32> %arg1, i64 1 + %add.0 = call i32 @llvm.sadd.sat.i32(i32 %arg0.0, i32 %arg1.0) + %add.1 = call i32 @llvm.sadd.sat.i32(i32 %arg0.1, i32 %arg1.1) + %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 + %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 + ret <2 x i32> %ins.1 +} + +define <2 x i32> @ssub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { +; GCN-LABEL: @ssub_sat_v2i32( +; GCN-NEXT: bb: +; GCN-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> [[ARG0:%.*]], <2 x i32> [[ARG1:%.*]]) +; GCN-NEXT: ret <2 x i32> [[TMP0]] +; +bb: + %arg0.0 = extractelement <2 x i32> %arg0, i64 0 + %arg0.1 = extractelement <2 x i32> %arg0, i64 1 + %arg1.0 = extractelement <2 x i32> %arg1, i64 0 + %arg1.1 = extractelement <2 x i32> %arg1, i64 1 + %add.0 = call i32 @llvm.ssub.sat.i32(i32 %arg0.0, i32 %arg1.0) + %add.1 = call i32 @llvm.ssub.sat.i32(i32 %arg0.1, i32 %arg1.1) + %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 + %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 + ret <2 x i32> %ins.1 +} + +define <3 x i16> @uadd_sat_v3i16(<3 x i16> %arg0, <3 x i16> %arg1) { +; GFX7-LABEL: @uadd_sat_v3i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <3 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <3 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1]], i64 2 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <3 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2 +; GFX7-NEXT: ret <3 x i16> [[INS_2]] +; +; GFX8-LABEL: @uadd_sat_v3i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2 +; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2 +; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <3 x i16> [[ARG0]], <3 x i16> undef, <2 x i32> +; GFX8-NEXT: [[TMP1:%.*]] = shufflevector <3 x i16> [[ARG1]], <3 x i16> undef, <2 x i32> +; GFX8-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +; GFX8-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]]) +; GFX8-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i32 0 +; GFX8-NEXT: [[INS_0:%.*]] = insertelement <3 x i16> undef, i16 [[TMP3]], i64 0 +; GFX8-NEXT: [[TMP4:%.*]] = extractelement <2 x i16> [[TMP2]], i32 1 +; GFX8-NEXT: [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[TMP4]], i64 1 +; GFX8-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2 +; GFX8-NEXT: ret <3 x i16> [[INS_2]] +; +bb: + %arg0.0 = extractelement <3 x i16> %arg0, i64 0 + %arg0.1 = extractelement <3 x i16> %arg0, i64 1 + %arg0.2 = extractelement <3 x i16> %arg0, i64 2 + %arg1.0 = extractelement <3 x i16> %arg1, i64 0 + %arg1.1 = extractelement <3 x i16> %arg1, i64 1 + %arg1.2 = extractelement <3 x i16> %arg1, i64 2 + %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1) + %add.2 = call i16 @llvm.uadd.sat.i16(i16 %arg0.2, i16 %arg1.2) + %ins.0 = insertelement <3 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <3 x i16> %ins.0, i16 %add.1, i64 1 + %ins.2 = insertelement <3 x i16> %ins.1, i16 %add.2, i64 2 + ret <3 x i16> %ins.2 +} + +define <4 x i16> @uadd_sat_v4i16(<4 x i16> %arg0, <4 x i16> %arg1) { +; GFX7-LABEL: @uadd_sat_v4i16( +; GFX7-NEXT: bb: +; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <4 x i16> [[ARG0:%.*]], i64 0 +; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <4 x i16> [[ARG0]], i64 1 +; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <4 x i16> [[ARG0]], i64 2 +; GFX7-NEXT: [[ARG0_3:%.*]] = extractelement <4 x i16> [[ARG0]], i64 3 +; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 0 +; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i16> [[ARG1]], i64 1 +; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1]], i64 2 +; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3 +; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) +; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) +; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]]) +; GFX7-NEXT: [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]]) +; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i16> undef, i16 [[ADD_0]], i64 0 +; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 +; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[INS_1]], i16 [[ADD_2]], i64 2 +; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3 +; GFX7-NEXT: ret <4 x i16> [[INS_3]] +; +; GFX8-LABEL: @uadd_sat_v4i16( +; GFX8-NEXT: bb: +; GFX8-NEXT: [[TMP0:%.*]] = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> [[ARG0:%.*]], <4 x i16> [[ARG1:%.*]]) +; GFX8-NEXT: ret <4 x i16> [[TMP0]] +; +bb: + %arg0.0 = extractelement <4 x i16> %arg0, i64 0 + %arg0.1 = extractelement <4 x i16> %arg0, i64 1 + %arg0.2 = extractelement <4 x i16> %arg0, i64 2 + %arg0.3 = extractelement <4 x i16> %arg0, i64 3 + %arg1.0 = extractelement <4 x i16> %arg1, i64 0 + %arg1.1 = extractelement <4 x i16> %arg1, i64 1 + %arg1.2 = extractelement <4 x i16> %arg1, i64 2 + %arg1.3 = extractelement <4 x i16> %arg1, i64 3 + %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0) + %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1) + %add.2 = call i16 @llvm.uadd.sat.i16(i16 %arg0.2, i16 %arg1.2) + %add.3 = call i16 @llvm.uadd.sat.i16(i16 %arg0.3, i16 %arg1.3) + %ins.0 = insertelement <4 x i16> undef, i16 %add.0, i64 0 + %ins.1 = insertelement <4 x i16> %ins.0, i16 %add.1, i64 1 + %ins.2 = insertelement <4 x i16> %ins.1, i16 %add.2, i64 2 + %ins.3 = insertelement <4 x i16> %ins.2, i16 %add.3, i64 3 + ret <4 x i16> %ins.3 +} + +declare i16 @llvm.uadd.sat.i16(i16, i16) #0 +declare i16 @llvm.usub.sat.i16(i16, i16) #0 +declare i16 @llvm.sadd.sat.i16(i16, i16) #0 +declare i16 @llvm.ssub.sat.i16(i16, i16) #0 + +declare i32 @llvm.uadd.sat.i32(i32, i32) #0 +declare i32 @llvm.usub.sat.i32(i32, i32) #0 +declare i32 @llvm.sadd.sat.i32(i32, i32) #0 +declare i32 @llvm.ssub.sat.i32(i32, i32) #0 + +attributes #0 = { nounwind readnone speculatable willreturn }