Index: llvm/lib/Target/AMDGPU/AMDGPUGISel.td =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -51,6 +51,11 @@ GIComplexOperandMatcher, GIComplexPatternEquiv; +// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods? +def gi_vop3opsel : + GIComplexOperandMatcher, + GIComplexPatternEquiv; + def gi_smrd_imm : GIComplexOperandMatcher, GIComplexPatternEquiv; Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -421,7 +421,7 @@ .moreElementsIf(isSmallOddVector(0), oneMoreElement(0)) .legalIf(isPointer(0)); - if (ST.hasVOP3PInsts()) { + if (ST.hasVOP3PInsts() && ST.hasNoCarryAddSubSat()) { assert(ST.hasIntClamp() && "all targets with VOP3P should support clamp"); getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL}) .legalFor({S32, S16, V2S16}) @@ -431,7 +431,7 @@ .widenScalarToNextPow2(0, 32); getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT, G_SADDSAT, G_SSUBSAT}) - .lowerFor({S32, S16, V2S16}) // FIXME: legal and merge with add/sub/mul + .legalFor({S32, S16, V2S16}) // Clamp modifier .minScalar(0, S16) .clampMaxNumElements(0, S16, 2) .scalarize(0) @@ -449,7 +449,7 @@ .widenScalarToNextPow2(0, 32); // FIXME: min should be 16 getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT}) - .lowerFor({S32, S16}) // FIXME: legal with clamp modifier + .legalFor({S32, S16}) // Clamp modifier .minScalar(0, S16) .scalarize(0) .widenScalarToNextPow2(0, 16) @@ -469,7 +469,7 @@ if (ST.hasIntClamp()) { getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT}) - .lowerFor({S32}) // FIXME: legal with clamp modifier. + .legalFor({S32}) // Clamp modifier. .scalarize(0) .minScalarOrElt(0, S32) .lower(); Index: llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -586,6 +586,10 @@ return GFX9Insts; } + bool hasNoCarryAddSubSat() const { + return GFX9Insts; + } + TrapHandlerAbi getTrapHandlerAbi() const { return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone; } Index: llvm/lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP2Instructions.td +++ llvm/lib/Target/AMDGPU/VOP2Instructions.td @@ -828,6 +828,24 @@ } // End Predicates = [Has16BitInsts] +let SubtargetPredicate = HasIntClamp in { +// Set clamp bit for saturation. +def : VOPBinOpClampPat; +def : VOPBinOpClampPat; +} + +let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in { +let AddedComplexity = 1 in { // Prefer over form with carry-out. +def : VOPBinOpClampPat; +def : VOPBinOpClampPat; +} +} + +let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in { +def : VOPBinOpClampPat; +def : VOPBinOpClampPat; +} + //===----------------------------------------------------------------------===// // Target-specific instruction encodings. //===----------------------------------------------------------------------===// Index: llvm/lib/Target/AMDGPU/VOP3Instructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -667,6 +667,20 @@ def : ThreeOp_i32_Pats; def : ThreeOp_i32_Pats; +def : VOPBinOpClampPat; +def : VOPBinOpClampPat; + + +// FIXME: Probably should hardcode clamp bit in pseudo and avoid this. +class OpSelBinOpClampPat : GCNPat< + (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)), + (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))), + (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0) +>; + +def : OpSelBinOpClampPat; +def : OpSelBinOpClampPat; } // End SubtargetPredicate = isGFX9Plus def VOP3_PERMLANE_Profile : VOP3_Profile, VOP3_OPSEL> { Index: llvm/lib/Target/AMDGPU/VOP3PInstructions.td =================================================================== --- llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -77,6 +77,8 @@ def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile, lshr_rev>; +let SubtargetPredicate = HasVOP3PInsts in { + // Undo sub x, c -> add x, -c canonicalization since c is more likely // an inline immediate than -c. // The constant will be emitted as a mov, and folded later. @@ -86,6 +88,19 @@ (V_PK_SUB_U16 $src0_modifiers, $src0, SRCMODS.OP_SEL_1, NegSubInlineConstV216:$src1) >; +// Integer operations with clamp bit set. +class VOP3PSatPat : GCNPat< + (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)), + (v2i16 (VOP3PMods v2i16:$src1, i32:$src1_modifiers))), + (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE) +>; + +def : VOP3PSatPat; +def : VOP3PSatPat; +def : VOP3PSatPat; +def : VOP3PSatPat; +} // End SubtargetPredicate = HasVOP3PInsts + multiclass MadFmaMixPats(Op), getDivergentFrag.ret, Op), Op); } +class getVSrcOp { + RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16); +} + +// Class for binary integer operations with the clamp bit set for saturation +// TODO: Add sub with negated inline constant pattern. +class VOPBinOpClampPat : + GCNPat<(node vt:$src0, vt:$src1), + (inst getVSrcOp.ret:$src0, getVSrcOp.ret:$src1, + DSTCLAMP.ENABLE) +>; + + include "VOPCInstructions.td" include "VOP1Instructions.td" include "VOP2Instructions.td" Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir @@ -59,17 +59,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -137,17 +128,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -282,34 +264,19 @@ ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C6]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C6]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C3]](s16) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C3]](s16) ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX9: [[SMAX2:%[0-9]+]]:_(s16) = G_SMAX [[SHL2]], [[C6]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[SMAX2]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(s16) = G_SMIN [[SHL2]], [[C6]] - ; GFX9: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[SMIN2]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(s16) = G_SMAX [[SUB3]], [[SHL3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB2]] - ; GFX9: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[SMIN3]] - ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ADD1]], [[C3]](s16) - ; GFX9: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 + ; GFX9: [[SADDSAT1:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL2]], [[SHL3]] + ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT1]], [[C3]](s16) + ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16) - ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]] + ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16) - ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]] + ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) @@ -375,17 +342,8 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[TRUNC1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[SMIN1]] - ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]] + ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -484,20 +442,8 @@ ; GFX9-LABEL: name: saddsat_v2s16 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[COPY]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[COPY]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[COPY1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[COPY]], [[SMIN1]] - ; GFX9: $vgpr0 = COPY [[ADD]](<2 x s16>) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[SADDSAT]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %2:_(<2 x s16>) = G_SADDSAT %0, %1 @@ -676,30 +622,9 @@ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC4]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC5]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[SMIN1]] - ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32) - ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]] - ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC7]], [[SMAX2]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]] - ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC8]], [[SMIN2]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[BUILD_VECTOR_TRUNC3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB2]] - ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[SMIN3]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>), [[DEF2]](<2 x s16>) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]] + ; GFX9: [[SADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SADDSAT]](<2 x s16>), [[SADDSAT1]](<2 x s16>), [[DEF2]](<2 x s16>) ; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0 ; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>) @@ -870,30 +795,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[UV2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV]], [[SMIN1]] - ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV1]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC3]], [[SMAX2]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV1]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC4]], [[SMIN2]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[UV3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB2]] - ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV1]], [[SMIN3]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[UV]], [[UV2]] + ; GFX9: [[SADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[UV1]], [[UV3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SADDSAT]](<2 x s16>), [[SADDSAT1]](<2 x s16>) ; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3 @@ -938,17 +842,8 @@ ; GFX9-LABEL: name: saddsat_s32 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[COPY1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[SMIN1]] - ; GFX9: $vgpr0 = COPY [[ADD]](s32) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[SADDSAT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_SADDSAT %0, %1 @@ -1014,24 +909,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[UV]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[UV]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[UV2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]] - ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[SMIN1]] - ; GFX9: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[UV1]], [[C2]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX2]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[UV1]], [[C2]] - ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN2]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[UV3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]] - ; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[SMIN3]] - ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32) + ; GFX9: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[UV]], [[UV2]] + ; GFX9: [[SADDSAT1:%[0-9]+]]:_(s32) = G_SADDSAT [[UV1]], [[UV3]] + ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SADDSAT]](s32), [[SADDSAT1]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir @@ -59,17 +59,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C1]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -137,17 +128,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C1]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -282,34 +264,19 @@ ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C6]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C4]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C6]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C5]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]] - ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C3]](s16) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C3]](s16) ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX9: [[SMAX2:%[0-9]+]]:_(s16) = G_SMAX [[SHL2]], [[C6]] - ; GFX9: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[SMAX2]], [[C4]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(s16) = G_SMIN [[SHL2]], [[C6]] - ; GFX9: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[SMIN2]], [[C5]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(s16) = G_SMAX [[SUB3]], [[SHL3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB4]] - ; GFX9: [[SUB5:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[SMIN3]] - ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SUB5]], [[C3]](s16) - ; GFX9: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 + ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL2]], [[SHL3]] + ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT1]], [[C3]](s16) + ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16) - ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]] + ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16) - ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]] + ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) @@ -375,17 +342,8 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767 - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768 - ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C1]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[TRUNC1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[SMIN1]] - ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB2]](s16) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[TRUNC]], [[TRUNC1]] + ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBSAT]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -484,20 +442,8 @@ ; GFX9-LABEL: name: ssubsat_v2s16 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[COPY]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[COPY]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC1]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[COPY1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[SMIN1]] - ; GFX9: $vgpr0 = COPY [[SUB2]](<2 x s16>) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[SSUBSAT]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %2:_(<2 x s16>) = G_SSUBSAT %0, %1 @@ -676,30 +622,9 @@ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC4]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMIN1]] - ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32) - ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]] - ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX2]], [[BUILD_VECTOR_TRUNC7]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]] - ; GFX9: [[SUB4:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN2]], [[BUILD_VECTOR_TRUNC8]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[BUILD_VECTOR_TRUNC3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB4]] - ; GFX9: [[SUB5:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN3]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SUB2]](<2 x s16>), [[SUB5]](<2 x s16>), [[DEF2]](<2 x s16>) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]] + ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SSUBSAT]](<2 x s16>), [[SSUBSAT1]](<2 x s16>), [[DEF2]](<2 x s16>) ; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0 ; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>) @@ -870,30 +795,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768 - ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC]] - ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC1]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[UV2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV]], [[SMIN1]] - ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32) - ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV1]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX2]], [[BUILD_VECTOR_TRUNC3]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV1]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[SUB4:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN2]], [[BUILD_VECTOR_TRUNC4]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[UV3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB4]] - ; GFX9: [[SUB5:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV1]], [[SMIN3]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SUB2]](<2 x s16>), [[SUB5]](<2 x s16>) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[UV]], [[UV2]] + ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[UV1]], [[UV3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SSUBSAT]](<2 x s16>), [[SSUBSAT1]](<2 x s16>) ; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3 @@ -938,17 +842,8 @@ ; GFX9-LABEL: name: ssubsat_s32 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C1]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[COPY1]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SMIN1]] - ; GFX9: $vgpr0 = COPY [[SUB2]](s32) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[SSUBSAT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_SSUBSAT %0, %1 @@ -1014,24 +909,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647 - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[UV]], [[C2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C]] - ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[UV]], [[C2]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C1]] - ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[UV2]] - ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]] - ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[SMIN1]] - ; GFX9: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[UV1]], [[C2]] - ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C]] - ; GFX9: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[UV1]], [[C2]] - ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C1]] - ; GFX9: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[UV3]] - ; GFX9: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]] - ; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[SMIN3]] - ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB2]](s32), [[SUB5]](s32) + ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[UV]], [[UV2]] + ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(s32) = G_SSUBSAT [[UV1]], [[UV3]] + ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SSUBSAT]](s32), [[SSUBSAT1]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir @@ -32,11 +32,8 @@ ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: uaddsat_s7 @@ -47,11 +44,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -92,11 +86,8 @@ ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: uaddsat_s8 @@ -107,11 +98,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -187,24 +175,19 @@ ; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C4]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C3]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16) ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[SHL2]], [[C4]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[SHL3]] - ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[UMIN1]] - ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[ADD1]], [[C3]](s16) - ; GFX8: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 + ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]] + ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16) + ; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) - ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]] + ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16) - ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]] + ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) @@ -226,24 +209,19 @@ ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C4]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]] - ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C3]](s16) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16) ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX9: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[SHL2]], [[C4]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[SHL3]] - ; GFX9: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[UMIN1]] - ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[ADD1]], [[C3]](s16) - ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 + ; GFX9: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]] + ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16) + ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) - ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]] + ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16) - ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]] + ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]] ; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16) ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]] ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16) @@ -286,22 +264,16 @@ ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC1]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]] - ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]] + ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: uaddsat_s16 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC1]] - ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]] - ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]] + ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -364,15 +336,10 @@ ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC2]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]] - ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC3]] - ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC2]] + ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC3]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) @@ -380,12 +347,8 @@ ; GFX9-LABEL: name: uaddsat_v2s16 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[COPY]], [[BUILD_VECTOR_TRUNC]] - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[COPY1]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[COPY]], [[UMIN]] - ; GFX9: $vgpr0 = COPY [[ADD]](<2 x s16>) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[UADDSAT]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %2:_(<2 x s16>) = G_UADDSAT %0, %1 @@ -482,24 +445,17 @@ ; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>) ; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32) ; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) - ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC3]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]] - ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC4]] - ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]] - ; GFX8: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C1]] - ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[XOR2]], [[TRUNC5]] - ; GFX8: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[UMIN2]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC3]] + ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC4]] + ; GFX8: [[UADDSAT2:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC2]], [[TRUNC5]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16) - ; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32) + ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT2]](s16) + ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32) ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]] ; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; GFX8: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>) @@ -536,16 +492,9 @@ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32) - ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC4]] - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[UMIN]] - ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) - ; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC5]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR1]], [[BUILD_VECTOR_TRUNC3]] - ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[UMIN1]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>), [[DEF2]](<2 x s16>) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]] + ; GFX9: [[UADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UADDSAT]](<2 x s16>), [[UADDSAT1]](<2 x s16>), [[DEF2]](<2 x s16>) ; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0 ; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>) @@ -650,26 +599,17 @@ ; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32) ; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; GFX8: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) - ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC4]] - ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]] - ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC5]] - ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]] - ; GFX8: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C1]] - ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[XOR2]], [[TRUNC6]] - ; GFX8: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[UMIN2]] - ; GFX8: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C1]] - ; GFX8: [[UMIN3:%[0-9]+]]:_(s16) = G_UMIN [[XOR3]], [[TRUNC7]] - ; GFX8: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[UMIN3]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC4]] + ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC5]] + ; GFX8: [[UADDSAT2:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC2]], [[TRUNC6]] + ; GFX8: [[UADDSAT3:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC3]], [[TRUNC7]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16) - ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ADD3]](s16) + ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT2]](s16) + ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT3]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32) ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]] ; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) @@ -680,16 +620,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV]], [[BUILD_VECTOR_TRUNC]] - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[UV2]] - ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV]], [[UMIN]] - ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) - ; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV1]], [[BUILD_VECTOR_TRUNC1]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR1]], [[UV3]] - ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV1]], [[UMIN1]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[UV]], [[UV2]] + ; GFX9: [[UADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[UV1]], [[UV3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UADDSAT]](<2 x s16>), [[UADDSAT1]](<2 x s16>) ; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3 @@ -714,19 +647,13 @@ ; GFX8-LABEL: name: uaddsat_s32 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]] - ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]] - ; GFX8: $vgpr0 = COPY [[ADD]](s32) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]] + ; GFX8: $vgpr0 = COPY [[UADDSAT]](s32) ; GFX9-LABEL: name: uaddsat_s32 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]] - ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]] - ; GFX9: $vgpr0 = COPY [[ADD]](s32) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[UADDSAT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_UADDSAT %0, %1 @@ -758,28 +685,18 @@ ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX8: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[C]] - ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[UV2]] - ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UMIN]] - ; GFX8: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[C]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[UV3]] - ; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UMIN1]] - ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32) + ; GFX8: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[UV]], [[UV2]] + ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s32) = G_UADDSAT [[UV1]], [[UV3]] + ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UADDSAT]](s32), [[UADDSAT1]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9-LABEL: name: uaddsat_v2s32 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[C]] - ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[UV2]] - ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UMIN]] - ; GFX9: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[C]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[UV3]] - ; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UMIN1]] - ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32) + ; GFX9: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[UV]], [[UV2]] + ; GFX9: [[UADDSAT1:%[0-9]+]]:_(s32) = G_UADDSAT [[UV1]], [[UV3]] + ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UADDSAT]](s32), [[UADDSAT1]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir @@ -30,9 +30,8 @@ ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: usubsat_s7 @@ -43,9 +42,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -84,9 +82,8 @@ ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16) ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: usubsat_s8 @@ -97,9 +94,8 @@ ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16) - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16) ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 @@ -172,16 +168,14 @@ ; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C3]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16) ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[SHL2]], [[SHL3]] - ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[UMIN1]] - ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[SUB1]], [[C3]](s16) + ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]] + ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16) ; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] @@ -208,16 +202,14 @@ ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8 ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16) ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16) - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]] - ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C3]](s16) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]] + ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16) ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) ; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16) ; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16) - ; GFX9: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[SHL2]], [[SHL3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[UMIN1]] - ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[SUB1]], [[C3]](s16) + ; GFX9: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]] + ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16) ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16) ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]] @@ -263,18 +255,16 @@ ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]] - ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]] + ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16) ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32) ; GFX9-LABEL: name: usubsat_s16 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32) - ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]] - ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]] - ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]] + ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16) ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -334,12 +324,10 @@ ; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32) ; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC2]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC3]] - ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC2]] + ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC3]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) @@ -347,9 +335,8 @@ ; GFX9-LABEL: name: usubsat_v2s16 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1 - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[COPY]], [[COPY1]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[UMIN]] - ; GFX9: $vgpr0 = COPY [[SUB]](<2 x s16>) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[USUBSAT]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 %2:_(<2 x s16>) = G_USUBSAT %0, %1 @@ -442,18 +429,15 @@ ; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>) ; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32) ; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC3]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC4]] - ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]] - ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC2]], [[TRUNC5]] - ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[UMIN2]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC3]] + ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC4]] + ; GFX8: [[USUBSAT2:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC2]], [[TRUNC5]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16) + ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT2]](s16) ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32) ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]] @@ -492,11 +476,9 @@ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32) ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32) - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[UMIN]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[UMIN1]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SUB]](<2 x s16>), [[SUB1]](<2 x s16>), [[DEF2]](<2 x s16>) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]] + ; GFX9: [[USUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[USUBSAT]](<2 x s16>), [[USUBSAT1]](<2 x s16>), [[DEF2]](<2 x s16>) ; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0 ; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0 ; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>) @@ -596,21 +578,17 @@ ; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32) ; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; GFX8: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32) - ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC4]] - ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC5]] - ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]] - ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC2]], [[TRUNC6]] - ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[UMIN2]] - ; GFX8: [[UMIN3:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC3]], [[TRUNC7]] - ; GFX8: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[TRUNC3]], [[UMIN3]] - ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16) - ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC4]] + ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC5]] + ; GFX8: [[USUBSAT2:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC2]], [[TRUNC6]] + ; GFX8: [[USUBSAT3:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC3]], [[TRUNC7]] + ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16) + ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16) ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32) ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]] ; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16) - ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[SUB3]](s16) + ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT2]](s16) + ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT3]](s16) ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32) ; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]] ; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) @@ -621,11 +599,9 @@ ; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>) ; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>) - ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[UV]], [[UV2]] - ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV]], [[UMIN]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[UV1]], [[UV3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV1]], [[UMIN1]] - ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SUB]](<2 x s16>), [[SUB1]](<2 x s16>) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[UV]], [[UV2]] + ; GFX9: [[USUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[UV1]], [[UV3]] + ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[USUBSAT]](<2 x s16>), [[USUBSAT1]](<2 x s16>) ; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>) %0:_(<4 x s16>) = COPY $vgpr0_vgpr1 %1:_(<4 x s16>) = COPY $vgpr2_vgpr3 @@ -648,15 +624,13 @@ ; GFX8-LABEL: name: usubsat_s32 ; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]] - ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]] - ; GFX8: $vgpr0 = COPY [[SUB]](s32) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]] + ; GFX8: $vgpr0 = COPY [[USUBSAT]](s32) ; GFX9-LABEL: name: usubsat_s32 ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 - ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]] - ; GFX9: $vgpr0 = COPY [[SUB]](s32) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]] + ; GFX9: $vgpr0 = COPY [[USUBSAT]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_USUBSAT %0, %1 @@ -685,22 +659,18 @@ ; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[UV]], [[UV2]] - ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UMIN]] - ; GFX8: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]] - ; GFX8: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]] - ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32) + ; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]] + ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s32) = G_USUBSAT [[UV1]], [[UV3]] + ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[USUBSAT]](s32), [[USUBSAT1]](s32) ; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; GFX9-LABEL: name: usubsat_v2s32 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>) - ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[UV]], [[UV2]] - ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UMIN]] - ; GFX9: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]] - ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]] - ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32) + ; GFX9: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]] + ; GFX9: [[USUBSAT1:%[0-9]+]]:_(s32) = G_USUBSAT [[UV1]], [[UV3]] + ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[USUBSAT]](s32), [[USUBSAT1]](s32) ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll @@ -39,14 +39,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0 -; GFX9-NEXT: v_min_i16_e32 v3, 0, v0 -; GFX9-NEXT: v_max_i16_e32 v2, 0, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_max_i16_e32 v1, v3, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -57,13 +51,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i16_e64 v2, v0, 0 -; GFX10-NEXT: v_max_i16_e64 v3, v0, 0 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2 -; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs) @@ -118,54 +106,23 @@ ; GFX9-LABEL: s_saddsat_i7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_sext_i32_i16 s3, s0 -; GFX9-NEXT: s_sext_i32_i16 s4, 0 -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s5, s3, s4 -; GFX9-NEXT: s_sub_i32 s5, 0x7fff, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s3, 0x8000, s3 -; GFX9-NEXT: s_sext_i32_i16 s3, s3 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s3, s5 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_sext_i32_i16 s0, s0 -; GFX9-NEXT: s_ashr_i32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_i7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX10-NEXT: s_sext_i32_i16 s4, 0 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s3, s4 -; GFX10-NEXT: s_sub_i32 s5, 0x7fff, s5 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sub_i32 s3, 0x8000, s3 -; GFX10-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s3, s5 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_sext_i32_i16 s0, s0 -; GFX10-NEXT: s_ashr_i32 s0, s0, s2 +; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs) ret i7 %result @@ -206,14 +163,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 -; GFX9-NEXT: v_min_i16_e32 v3, 0, v0 -; GFX9-NEXT: v_max_i16_e32 v2, 0, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_max_i16_e32 v1, v3, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -224,13 +175,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i16_e64 v2, v0, 0 -; GFX10-NEXT: v_max_i16_e64 v3, v0, 0 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2 -; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs) @@ -285,54 +230,23 @@ ; GFX9-LABEL: s_saddsat_i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_sext_i32_i16 s3, s0 -; GFX9-NEXT: s_sext_i32_i16 s4, 0 -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s5, s3, s4 -; GFX9-NEXT: s_sub_i32 s5, 0x7fff, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s3, 0x8000, s3 -; GFX9-NEXT: s_sext_i32_i16 s3, s3 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s3, s5 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_sext_i32_i16 s0, s0 -; GFX9-NEXT: s_ashr_i32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_i8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX10-NEXT: s_sext_i32_i16 s4, 0 +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s3, s4 -; GFX10-NEXT: s_sub_i32 s5, 0x7fff, s5 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sub_i32 s3, 0x8000, s3 -; GFX10-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s3, s5 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_sext_i32_i16 s0, s0 -; GFX10-NEXT: s_ashr_i32 s0, s0, s2 +; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs) ret i8 %result @@ -374,14 +288,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0 -; GFX9-NEXT: v_min_i32_e32 v3, 0, v0 -; GFX9-NEXT: v_max_i32_e32 v2, 0, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_sub_u32_e32 v3, 0x80000000, v3 -; GFX9-NEXT: v_sub_u32_e32 v2, 0x7fffffff, v2 -; GFX9-NEXT: v_max_i32_e32 v1, v3, v1 -; GFX9-NEXT: v_min_i32_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -392,13 +300,7 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i32_e32 v2, 0, v0 -; GFX10-NEXT: v_max_i32_e32 v3, 0, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x80000000, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, 0x7fffffff, v3 -; GFX10-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs) @@ -445,39 +347,22 @@ ; ; GFX9-LABEL: s_saddsat_i24: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshl_b32 s0, s0, 8 ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, s0, 0 -; GFX9-NEXT: s_sub_i32 s2, 0x7fffffff, s2 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s3, s0, 0 -; GFX9-NEXT: s_sub_i32 s3, 0x80000000, s3 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_ashr_i32 s0, s0, 8 +; GFX9-NEXT: s_lshl_b32 s0, s0, 8 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_i24: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_lshl_b32 s0, s0, 8 ; GFX10-NEXT: s_lshl_b32 s1, s1, 8 -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s0, 0 -; GFX10-NEXT: s_sub_i32 s2, 0x7fffffff, s2 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 -; GFX10-NEXT: s_cselect_b32 s3, s0, 0 -; GFX10-NEXT: s_sub_i32 s3, 0x80000000, s3 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_ashr_i32 s0, s0, 8 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs) ret i24 %result @@ -511,27 +396,15 @@ ; GFX9-LABEL: v_saddsat_i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_i32_e32 v3, 0, v0 -; GFX9-NEXT: v_max_i32_e32 v2, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v3, 0x80000000, v3 -; GFX9-NEXT: v_sub_u32_e32 v2, 0x7fffffff, v2 -; GFX9-NEXT: v_max_i32_e32 v1, v3, v1 -; GFX9-NEXT: v_min_i32_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v2, 0, v0 -; GFX10-NEXT: v_max_i32_e32 v3, 0, v0 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x80000000, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, 0x7fffffff, v3 -; GFX10-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -585,33 +458,16 @@ ; ; GFX9-LABEL: s_saddsat_i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, s0, 0 -; GFX9-NEXT: s_sub_i32 s2, 0x7fffffff, s2 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s3, s0, 0 -; GFX9-NEXT: s_sub_i32 s3, 0x80000000, s3 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_add_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s0, 0 -; GFX10-NEXT: s_sub_i32 s2, 0x7fffffff, s2 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 -; GFX10-NEXT: s_cselect_b32 s3, s0, 0 -; GFX10-NEXT: s_sub_i32 s3, 0x80000000, s3 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_add_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -646,29 +502,13 @@ ; ; GFX9-LABEL: saddsat_i32_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s1, s0, 0 -; GFX9-NEXT: s_sub_i32 s1, 0x7fffffff, s1 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_cselect_b32 s2, s0, 0 -; GFX9-NEXT: s_sub_i32 s2, 0x80000000, s2 -; GFX9-NEXT: v_max_i32_e32 v0, s2, v0 -; GFX9-NEXT: v_min_i32_e32 v0, s1, v0 -; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i32_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s1, s0, 0 -; GFX10-NEXT: s_sub_i32 s1, 0x7fffffff, s1 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 -; GFX10-NEXT: s_cselect_b32 s2, s0, 0 -; GFX10-NEXT: s_sub_i32 s2, 0x80000000, s2 -; GFX10-NEXT: v_max_i32_e32 v0, s2, v0 -; GFX10-NEXT: v_min_i32_e32 v0, s1, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -700,25 +540,13 @@ ; ; GFX9-LABEL: saddsat_i32_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_i32_e32 v2, 0, v0 -; GFX9-NEXT: v_max_i32_e32 v1, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v2, 0x80000000, v2 -; GFX9-NEXT: v_sub_u32_e32 v1, 0x7fffffff, v1 -; GFX9-NEXT: v_max_i32_e32 v2, s0, v2 -; GFX9-NEXT: v_min_i32_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i32 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i32_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_i32_e32 v1, 0, v0 -; GFX10-NEXT: v_max_i32_e32 v2, 0, v0 +; GFX10-NEXT: v_add_nc_i32 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x80000000, v1 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x7fffffff, v2 -; GFX10-NEXT: v_max_i32_e32 v1, s0, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -771,45 +599,17 @@ ; GFX9-LABEL: v_saddsat_v2i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v5, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v4, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4 -; GFX9-NEXT: v_max_i32_e32 v2, v5, v2 -; GFX9-NEXT: v_min_i32_e32 v2, v2, v4 -; GFX9-NEXT: v_min_i32_e32 v4, 0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 -; GFX9-NEXT: v_max_i32_e32 v2, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4 -; GFX9-NEXT: v_sub_u32_e32 v2, s4, v2 -; GFX9-NEXT: v_max_i32_e32 v3, v4, v3 -; GFX9-NEXT: v_min_i32_e32 v2, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v2i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v4, 0, v0 -; GFX10-NEXT: v_min_i32_e32 v5, 0, v1 -; GFX10-NEXT: s_mov_b32 s4, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v6, 0, v0 -; GFX10-NEXT: v_max_i32_e32 v7, 0, v1 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, s4, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v5, s4, v5 -; GFX10-NEXT: s_brev_b32 s4, -2 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp +; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v6, s4, v6 -; GFX10-NEXT: v_max_i32_e32 v11, v4, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v7, s4, v7 -; GFX10-NEXT: v_max_i32_e32 v10, v5, v3 -; GFX10-NEXT: v_min_i32_e32 v2, v11, v6 -; GFX10-NEXT: v_min_i32_e32 v3, v10, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -874,59 +674,21 @@ ; ; GFX9-LABEL: s_saddsat_v2i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: s_cselect_b32 s6, s0, 0 -; GFX9-NEXT: s_sub_i32 s6, s4, s6 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s7, s0, 0 -; GFX9-NEXT: s_sub_i32 s7, s5, s7 -; GFX9-NEXT: s_cmp_gt_i32 s7, s2 -; GFX9-NEXT: s_cselect_b32 s2, s7, s2 -; GFX9-NEXT: s_cmp_lt_i32 s2, s6 -; GFX9-NEXT: s_cselect_b32 s2, s2, s6 -; GFX9-NEXT: s_add_i32 s0, s0, s2 -; GFX9-NEXT: s_cmp_gt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s2, s1, 0 -; GFX9-NEXT: s_sub_i32 s2, s4, s2 -; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s4, s1, 0 -; GFX9-NEXT: s_sub_i32 s4, s5, s4 -; GFX9-NEXT: s_cmp_gt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_cmp_lt_i32 s3, s2 -; GFX9-NEXT: s_cselect_b32 s2, s3, s2 -; GFX9-NEXT: s_add_i32 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v2i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: s_cselect_b32 s5, s0, 0 -; GFX10-NEXT: s_mov_b32 s6, 0x80000000 -; GFX10-NEXT: s_sub_i32 s5, s4, s5 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s2 clamp +; GFX10-NEXT: v_add_nc_i32 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s7, s0, 0 -; GFX10-NEXT: s_sub_i32 s7, s6, s7 -; GFX10-NEXT: s_cmp_gt_i32 s7, s2 -; GFX10-NEXT: s_cselect_b32 s2, s7, s2 -; GFX10-NEXT: s_cmp_lt_i32 s2, s5 -; GFX10-NEXT: s_cselect_b32 s2, s2, s5 -; GFX10-NEXT: s_add_i32 s0, s0, s2 -; GFX10-NEXT: s_cmp_gt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s2, s1, 0 -; GFX10-NEXT: s_sub_i32 s2, s4, s2 -; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s4, s1, 0 -; GFX10-NEXT: s_sub_i32 s4, s6, s4 -; GFX10-NEXT: s_cmp_gt_i32 s4, s3 -; GFX10-NEXT: s_cselect_b32 s3, s4, s3 -; GFX10-NEXT: s_cmp_lt_i32 s3, s2 -; GFX10-NEXT: s_cselect_b32 s2, s3, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -992,59 +754,19 @@ ; GFX9-LABEL: v_saddsat_v3i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v7, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v7, s5, v7 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v6, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v6, s4, v6 -; GFX9-NEXT: v_max_i32_e32 v3, v7, v3 -; GFX9-NEXT: v_min_i32_e32 v3, v3, v6 -; GFX9-NEXT: v_min_i32_e32 v6, 0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 -; GFX9-NEXT: v_max_i32_e32 v3, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6 -; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 -; GFX9-NEXT: v_max_i32_e32 v4, v6, v4 -; GFX9-NEXT: v_min_i32_e32 v3, v4, v3 -; GFX9-NEXT: v_min_i32_e32 v4, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_max_i32_e32 v3, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3 -; GFX9-NEXT: v_max_i32_e32 v4, v4, v5 -; GFX9-NEXT: v_min_i32_e32 v3, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_add_i32 v0, v0, v3 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v4 clamp +; GFX9-NEXT: v_add_i32 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v3i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v7, 0, v0 -; GFX10-NEXT: v_min_i32_e32 v8, 0, v1 -; GFX10-NEXT: v_min_i32_e32 v9, 0, v2 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v6, 0, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v14, s5, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v15, s5, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, s5, v9 -; GFX10-NEXT: v_max_i32_e32 v10, 0, v1 -; GFX10-NEXT: v_max_i32_e32 v11, 0, v2 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_max_i32_e32 v3, v14, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v6, s4, v6 -; GFX10-NEXT: v_sub_nc_u32_e32 v7, s4, v10 -; GFX10-NEXT: v_max_i32_e32 v4, v15, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, s4, v11 -; GFX10-NEXT: v_max_i32_e32 v5, v19, v5 -; GFX10-NEXT: v_min_i32_e32 v3, v3, v6 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v3 clamp +; GFX10-NEXT: v_add_nc_i32 v1, v1, v4 clamp +; GFX10-NEXT: v_add_nc_i32 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i32_e32 v4, v4, v7 -; GFX10-NEXT: v_min_i32_e32 v5, v5, v8 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v4 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -1131,81 +853,26 @@ ; ; GFX9-LABEL: s_saddsat_v3i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_brev_b32 s6, -2 -; GFX9-NEXT: s_cselect_b32 s8, s0, 0 -; GFX9-NEXT: s_sub_i32 s8, s6, s8 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_mov_b32 s7, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s9, s0, 0 -; GFX9-NEXT: s_sub_i32 s9, s7, s9 -; GFX9-NEXT: s_cmp_gt_i32 s9, s3 -; GFX9-NEXT: s_cselect_b32 s3, s9, s3 -; GFX9-NEXT: s_cmp_lt_i32 s3, s8 -; GFX9-NEXT: s_cselect_b32 s3, s3, s8 -; GFX9-NEXT: s_add_i32 s0, s0, s3 -; GFX9-NEXT: s_cmp_gt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s3, s1, 0 -; GFX9-NEXT: s_sub_i32 s3, s6, s3 -; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s8, s1, 0 -; GFX9-NEXT: s_sub_i32 s8, s7, s8 -; GFX9-NEXT: s_cmp_gt_i32 s8, s4 -; GFX9-NEXT: s_cselect_b32 s4, s8, s4 -; GFX9-NEXT: s_cmp_lt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_add_i32 s1, s1, s3 -; GFX9-NEXT: s_cmp_gt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s3, s2, 0 -; GFX9-NEXT: s_sub_i32 s3, s6, s3 -; GFX9-NEXT: s_cmp_lt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s4, s2, 0 -; GFX9-NEXT: s_sub_i32 s4, s7, s4 -; GFX9-NEXT: s_cmp_gt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_add_i32 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v3i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 -; GFX10-NEXT: s_brev_b32 s6, -2 -; GFX10-NEXT: s_cselect_b32 s7, s0, 0 -; GFX10-NEXT: s_mov_b32 s8, 0x80000000 -; GFX10-NEXT: s_sub_i32 s7, s6, s7 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s3 clamp +; GFX10-NEXT: v_add_nc_i32 v1, s1, s4 clamp +; GFX10-NEXT: v_add_nc_i32 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s9, s0, 0 -; GFX10-NEXT: s_sub_i32 s9, s8, s9 -; GFX10-NEXT: s_cmp_gt_i32 s9, s3 -; GFX10-NEXT: s_cselect_b32 s3, s9, s3 -; GFX10-NEXT: s_cmp_lt_i32 s3, s7 -; GFX10-NEXT: s_cselect_b32 s3, s3, s7 -; GFX10-NEXT: s_add_i32 s0, s0, s3 -; GFX10-NEXT: s_cmp_gt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s3, s1, 0 -; GFX10-NEXT: s_sub_i32 s3, s6, s3 -; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s7, s1, 0 -; GFX10-NEXT: s_sub_i32 s7, s8, s7 -; GFX10-NEXT: s_cmp_gt_i32 s7, s4 -; GFX10-NEXT: s_cselect_b32 s4, s7, s4 -; GFX10-NEXT: s_cmp_lt_i32 s4, s3 -; GFX10-NEXT: s_cselect_b32 s3, s4, s3 -; GFX10-NEXT: s_add_i32 s1, s1, s3 -; GFX10-NEXT: s_cmp_gt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s3, s2, 0 -; GFX10-NEXT: s_sub_i32 s3, s6, s3 -; GFX10-NEXT: s_cmp_lt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s4, s2, 0 -; GFX10-NEXT: s_sub_i32 s4, s8, s4 -; GFX10-NEXT: s_cmp_gt_i32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_cmp_lt_i32 s4, s3 -; GFX10-NEXT: s_cselect_b32 s3, s4, s3 -; GFX10-NEXT: s_add_i32 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -1285,73 +952,21 @@ ; GFX9-LABEL: v_saddsat_v4i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v9, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v9, s5, v9 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v8, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v8, s4, v8 -; GFX9-NEXT: v_max_i32_e32 v4, v9, v4 -; GFX9-NEXT: v_min_i32_e32 v4, v4, v8 -; GFX9-NEXT: v_min_i32_e32 v8, 0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v4 -; GFX9-NEXT: v_max_i32_e32 v4, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v8, s5, v8 -; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4 -; GFX9-NEXT: v_max_i32_e32 v5, v8, v5 -; GFX9-NEXT: v_min_i32_e32 v4, v5, v4 -; GFX9-NEXT: v_min_i32_e32 v5, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v4 -; GFX9-NEXT: v_max_i32_e32 v4, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v6 -; GFX9-NEXT: v_min_i32_e32 v4, v5, v4 -; GFX9-NEXT: v_min_i32_e32 v5, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v5, 0x80000000, v5 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_max_i32_e32 v4, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v4, 0x7fffffff, v4 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v7 -; GFX9-NEXT: v_min_i32_e32 v4, v5, v4 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 +; GFX9-NEXT: v_add_i32 v0, v0, v4 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v5 clamp +; GFX9-NEXT: v_add_i32 v2, v2, v6 clamp +; GFX9-NEXT: v_add_i32 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v4i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v8, 0, v0 -; GFX10-NEXT: s_mov_b32 s4, 0x80000000 -; GFX10-NEXT: v_min_i32_e32 v11, 0, v1 -; GFX10-NEXT: v_min_i32_e32 v12, 0, v3 -; GFX10-NEXT: v_max_i32_e32 v9, 0, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v15, s4, v8 -; GFX10-NEXT: v_min_i32_e32 v8, 0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, s4, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v12, 0x80000000, v12 -; GFX10-NEXT: v_max_i32_e32 v10, 0, v1 -; GFX10-NEXT: v_max_i32_e32 v13, 0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, s4, v8 -; GFX10-NEXT: v_max_i32_e32 v14, 0, v3 -; GFX10-NEXT: s_brev_b32 s5, -2 -; GFX10-NEXT: v_max_i32_e32 v5, v11, v5 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, s5, v10 -; GFX10-NEXT: v_max_i32_e32 v6, v8, v6 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, s5, v13 -; GFX10-NEXT: v_sub_nc_u32_e32 v9, s5, v9 -; GFX10-NEXT: v_max_i32_e32 v4, v15, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, 0x7fffffff, v14 -; GFX10-NEXT: v_max_i32_e32 v7, v12, v7 -; GFX10-NEXT: v_min_i32_e32 v11, v6, v11 -; GFX10-NEXT: v_min_i32_e32 v19, v5, v10 -; GFX10-NEXT: v_min_i32_e32 v15, v4, v9 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v4 clamp +; GFX10-NEXT: v_add_nc_i32 v1, v1, v5 clamp +; GFX10-NEXT: v_add_nc_i32 v2, v2, v6 clamp +; GFX10-NEXT: v_add_nc_i32 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i32_e32 v6, v7, v8 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v11 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v19 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v15 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -1460,103 +1075,31 @@ ; ; GFX9-LABEL: s_saddsat_v4i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_brev_b32 s8, -2 -; GFX9-NEXT: s_cselect_b32 s10, s0, 0 -; GFX9-NEXT: s_sub_i32 s10, s8, s10 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_mov_b32 s9, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s11, s0, 0 -; GFX9-NEXT: s_sub_i32 s11, s9, s11 -; GFX9-NEXT: s_cmp_gt_i32 s11, s4 -; GFX9-NEXT: s_cselect_b32 s4, s11, s4 -; GFX9-NEXT: s_cmp_lt_i32 s4, s10 -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 -; GFX9-NEXT: s_add_i32 s0, s0, s4 -; GFX9-NEXT: s_cmp_gt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s4, s1, 0 -; GFX9-NEXT: s_sub_i32 s4, s8, s4 -; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s10, s1, 0 -; GFX9-NEXT: s_sub_i32 s10, s9, s10 -; GFX9-NEXT: s_cmp_gt_i32 s10, s5 -; GFX9-NEXT: s_cselect_b32 s5, s10, s5 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_add_i32 s1, s1, s4 -; GFX9-NEXT: s_cmp_gt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s4, s2, 0 -; GFX9-NEXT: s_sub_i32 s4, s8, s4 -; GFX9-NEXT: s_cmp_lt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s5, s2, 0 -; GFX9-NEXT: s_sub_i32 s5, s9, s5 -; GFX9-NEXT: s_cmp_gt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_add_i32 s2, s2, s4 -; GFX9-NEXT: s_cmp_gt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s4, s3, 0 -; GFX9-NEXT: s_sub_i32 s4, s8, s4 -; GFX9-NEXT: s_cmp_lt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s5, s3, 0 -; GFX9-NEXT: s_sub_i32 s5, s9, s5 -; GFX9-NEXT: s_cmp_gt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_add_i32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v4i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 -; GFX10-NEXT: s_brev_b32 s8, -2 -; GFX10-NEXT: s_cselect_b32 s9, s0, 0 -; GFX10-NEXT: s_mov_b32 s10, 0x80000000 -; GFX10-NEXT: s_sub_i32 s9, s8, s9 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s4 clamp +; GFX10-NEXT: v_add_nc_i32 v1, s1, s5 clamp +; GFX10-NEXT: v_add_nc_i32 v2, s2, s6 clamp +; GFX10-NEXT: v_add_nc_i32 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s11, s0, 0 -; GFX10-NEXT: s_sub_i32 s11, s10, s11 -; GFX10-NEXT: s_cmp_gt_i32 s11, s4 -; GFX10-NEXT: s_cselect_b32 s4, s11, s4 -; GFX10-NEXT: s_cmp_lt_i32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s9 -; GFX10-NEXT: s_add_i32 s0, s0, s4 -; GFX10-NEXT: s_cmp_gt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s4, s1, 0 -; GFX10-NEXT: s_sub_i32 s4, s8, s4 -; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s9, s1, 0 -; GFX10-NEXT: s_sub_i32 s9, s10, s9 -; GFX10-NEXT: s_cmp_gt_i32 s9, s5 -; GFX10-NEXT: s_cselect_b32 s5, s9, s5 -; GFX10-NEXT: s_cmp_lt_i32 s5, s4 -; GFX10-NEXT: s_cselect_b32 s4, s5, s4 -; GFX10-NEXT: s_add_i32 s1, s1, s4 -; GFX10-NEXT: s_cmp_gt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s4, s2, 0 -; GFX10-NEXT: s_sub_i32 s4, s8, s4 -; GFX10-NEXT: s_cmp_lt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s5, s2, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_gt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_cmp_lt_i32 s5, s4 -; GFX10-NEXT: s_cselect_b32 s4, s5, s4 -; GFX10-NEXT: s_add_i32 s2, s2, s4 -; GFX10-NEXT: s_cmp_gt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s4, s3, 0 -; GFX10-NEXT: s_sub_i32 s4, s8, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s5, s3, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_gt_i32 s5, s7 -; GFX10-NEXT: s_cselect_b32 s5, s5, s7 -; GFX10-NEXT: s_cmp_lt_i32 s5, s4 -; GFX10-NEXT: s_cselect_b32 s4, s5, s4 -; GFX10-NEXT: s_add_i32 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -1654,90 +1197,22 @@ ; GFX9-LABEL: v_saddsat_v5i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v12, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v12, s5, v12 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v10, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v10, s4, v10 -; GFX9-NEXT: v_max_i32_e32 v5, v12, v5 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v10 -; GFX9-NEXT: v_min_i32_e32 v10, 0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v5 -; GFX9-NEXT: v_max_i32_e32 v5, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v10, s5, v10 -; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5 -; GFX9-NEXT: v_max_i32_e32 v6, v10, v6 -; GFX9-NEXT: v_min_i32_e32 v5, v6, v5 -; GFX9-NEXT: v_min_i32_e32 v6, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v5 -; GFX9-NEXT: v_max_i32_e32 v5, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5 -; GFX9-NEXT: v_max_i32_e32 v6, v6, v7 -; GFX9-NEXT: v_min_i32_e32 v5, v6, v5 -; GFX9-NEXT: v_mov_b32_e32 v13, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v6, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v6, v13, v6 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_bfrev_b32_e32 v11, -2 -; GFX9-NEXT: v_max_i32_e32 v5, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v5, v11, v5 -; GFX9-NEXT: v_max_i32_e32 v6, v6, v8 -; GFX9-NEXT: v_min_i32_e32 v5, v6, v5 -; GFX9-NEXT: v_min_i32_e32 v6, 0, v4 -; GFX9-NEXT: v_sub_u32_e32 v6, v13, v6 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_max_i32_e32 v5, 0, v4 -; GFX9-NEXT: v_sub_u32_e32 v5, v11, v5 -; GFX9-NEXT: v_max_i32_e32 v6, v6, v9 -; GFX9-NEXT: v_min_i32_e32 v5, v6, v5 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v5 +; GFX9-NEXT: v_add_i32 v0, v0, v5 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v6 clamp +; GFX9-NEXT: v_add_i32 v2, v2, v7 clamp +; GFX9-NEXT: v_add_i32 v3, v3, v8 clamp +; GFX9-NEXT: v_add_i32 v4, v4, v9 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v5i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v13, 0, v1 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_min_i32_e32 v10, 0, v0 -; GFX10-NEXT: v_min_i32_e32 v16, 0, v2 -; GFX10-NEXT: v_mov_b32_e32 v15, 0x80000000 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, s5, v13 -; GFX10-NEXT: v_min_i32_e32 v17, 0, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, s5, v10 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, s5, v16 -; GFX10-NEXT: v_max_i32_e32 v11, 0, v0 -; GFX10-NEXT: v_max_i32_e32 v23, v13, v6 -; GFX10-NEXT: v_min_i32_e32 v13, 0, v3 -; GFX10-NEXT: v_max_i32_e32 v5, v10, v5 -; GFX10-NEXT: v_bfrev_b32_e32 v12, -2 -; GFX10-NEXT: v_max_i32_e32 v14, 0, v1 -; GFX10-NEXT: v_max_i32_e32 v10, 0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, v15, v13 -; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v17 -; GFX10-NEXT: v_max_i32_e32 v18, 0, v3 -; GFX10-NEXT: v_max_i32_e32 v19, 0, v4 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_max_i32_e32 v7, v16, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, s4, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v14, s4, v14 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, s4, v10 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v12, v18 -; GFX10-NEXT: v_max_i32_e32 v27, v13, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v19 -; GFX10-NEXT: v_max_i32_e32 v9, v15, v9 -; GFX10-NEXT: v_min_i32_e32 v5, v5, v11 -; GFX10-NEXT: v_min_i32_e32 v6, v23, v14 -; GFX10-NEXT: v_min_i32_e32 v7, v7, v10 -; GFX10-NEXT: v_min_i32_e32 v8, v27, v16 -; GFX10-NEXT: v_min_i32_e32 v9, v9, v12 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v5 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v6 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v8 -; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v9 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v5 clamp +; GFX10-NEXT: v_add_nc_i32 v1, v1, v6 clamp +; GFX10-NEXT: v_add_nc_i32 v2, v2, v7 clamp +; GFX10-NEXT: v_add_nc_i32 v3, v3, v8 clamp +; GFX10-NEXT: v_add_nc_i32 v4, v4, v9 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) @@ -1869,125 +1344,36 @@ ; ; GFX9-LABEL: s_saddsat_v5i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_brev_b32 s10, -2 -; GFX9-NEXT: s_cselect_b32 s12, s0, 0 -; GFX9-NEXT: s_sub_i32 s12, s10, s12 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_mov_b32 s11, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s13, s0, 0 -; GFX9-NEXT: s_sub_i32 s13, s11, s13 -; GFX9-NEXT: s_cmp_gt_i32 s13, s5 -; GFX9-NEXT: s_cselect_b32 s5, s13, s5 -; GFX9-NEXT: s_cmp_lt_i32 s5, s12 -; GFX9-NEXT: s_cselect_b32 s5, s5, s12 -; GFX9-NEXT: s_add_i32 s0, s0, s5 -; GFX9-NEXT: s_cmp_gt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s5, s1, 0 -; GFX9-NEXT: s_sub_i32 s5, s10, s5 -; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s12, s1, 0 -; GFX9-NEXT: s_sub_i32 s12, s11, s12 -; GFX9-NEXT: s_cmp_gt_i32 s12, s6 -; GFX9-NEXT: s_cselect_b32 s6, s12, s6 -; GFX9-NEXT: s_cmp_lt_i32 s6, s5 -; GFX9-NEXT: s_cselect_b32 s5, s6, s5 -; GFX9-NEXT: s_add_i32 s1, s1, s5 -; GFX9-NEXT: s_cmp_gt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s5, s2, 0 -; GFX9-NEXT: s_sub_i32 s5, s10, s5 -; GFX9-NEXT: s_cmp_lt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s6, s2, 0 -; GFX9-NEXT: s_sub_i32 s6, s11, s6 -; GFX9-NEXT: s_cmp_gt_i32 s6, s7 -; GFX9-NEXT: s_cselect_b32 s6, s6, s7 -; GFX9-NEXT: s_cmp_lt_i32 s6, s5 -; GFX9-NEXT: s_cselect_b32 s5, s6, s5 -; GFX9-NEXT: s_add_i32 s2, s2, s5 -; GFX9-NEXT: s_cmp_gt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s5, s3, 0 -; GFX9-NEXT: s_sub_i32 s5, s10, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s6, s3, 0 -; GFX9-NEXT: s_sub_i32 s6, s11, s6 -; GFX9-NEXT: s_cmp_gt_i32 s6, s8 -; GFX9-NEXT: s_cselect_b32 s6, s6, s8 -; GFX9-NEXT: s_cmp_lt_i32 s6, s5 -; GFX9-NEXT: s_cselect_b32 s5, s6, s5 -; GFX9-NEXT: s_add_i32 s3, s3, s5 -; GFX9-NEXT: s_cmp_gt_i32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s5, s4, 0 -; GFX9-NEXT: s_sub_i32 s5, s10, s5 -; GFX9-NEXT: s_cmp_lt_i32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s6, s4, 0 -; GFX9-NEXT: s_sub_i32 s6, s11, s6 -; GFX9-NEXT: s_cmp_gt_i32 s6, s9 -; GFX9-NEXT: s_cselect_b32 s6, s6, s9 -; GFX9-NEXT: s_cmp_lt_i32 s6, s5 -; GFX9-NEXT: s_cselect_b32 s5, s6, s5 -; GFX9-NEXT: s_add_i32 s4, s4, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s5 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 +; GFX9-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v5i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 -; GFX10-NEXT: s_brev_b32 s10, -2 -; GFX10-NEXT: s_cselect_b32 s11, s0, 0 -; GFX10-NEXT: s_mov_b32 s12, 0x80000000 -; GFX10-NEXT: s_sub_i32 s11, s10, s11 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s5 clamp +; GFX10-NEXT: v_add_nc_i32 v1, s1, s6 clamp +; GFX10-NEXT: v_add_nc_i32 v2, s2, s7 clamp +; GFX10-NEXT: v_add_nc_i32 v3, s3, s8 clamp +; GFX10-NEXT: v_add_nc_i32 v4, s4, s9 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s13, s0, 0 -; GFX10-NEXT: s_sub_i32 s13, s12, s13 -; GFX10-NEXT: s_cmp_gt_i32 s13, s5 -; GFX10-NEXT: s_cselect_b32 s5, s13, s5 -; GFX10-NEXT: s_cmp_lt_i32 s5, s11 -; GFX10-NEXT: s_cselect_b32 s5, s5, s11 -; GFX10-NEXT: s_add_i32 s0, s0, s5 -; GFX10-NEXT: s_cmp_gt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s5, s1, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s11, s1, 0 -; GFX10-NEXT: s_sub_i32 s11, s12, s11 -; GFX10-NEXT: s_cmp_gt_i32 s11, s6 -; GFX10-NEXT: s_cselect_b32 s6, s11, s6 -; GFX10-NEXT: s_cmp_lt_i32 s6, s5 -; GFX10-NEXT: s_cselect_b32 s5, s6, s5 -; GFX10-NEXT: s_add_i32 s1, s1, s5 -; GFX10-NEXT: s_cmp_gt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s5, s2, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_lt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s6, s2, 0 -; GFX10-NEXT: s_sub_i32 s6, s12, s6 -; GFX10-NEXT: s_cmp_gt_i32 s6, s7 -; GFX10-NEXT: s_cselect_b32 s6, s6, s7 -; GFX10-NEXT: s_cmp_lt_i32 s6, s5 -; GFX10-NEXT: s_cselect_b32 s5, s6, s5 -; GFX10-NEXT: s_add_i32 s2, s2, s5 -; GFX10-NEXT: s_cmp_gt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s5, s3, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_lt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s6, s3, 0 -; GFX10-NEXT: s_sub_i32 s6, s12, s6 -; GFX10-NEXT: s_cmp_gt_i32 s6, s8 -; GFX10-NEXT: s_cselect_b32 s6, s6, s8 -; GFX10-NEXT: s_cmp_lt_i32 s6, s5 -; GFX10-NEXT: s_cselect_b32 s5, s6, s5 -; GFX10-NEXT: s_add_i32 s3, s3, s5 -; GFX10-NEXT: s_cmp_gt_i32 s4, 0 -; GFX10-NEXT: s_cselect_b32 s5, s4, 0 -; GFX10-NEXT: s_sub_i32 s5, s10, s5 -; GFX10-NEXT: s_cmp_lt_i32 s4, 0 -; GFX10-NEXT: s_cselect_b32 s6, s4, 0 -; GFX10-NEXT: s_sub_i32 s6, s12, s6 -; GFX10-NEXT: s_cmp_gt_i32 s6, s9 -; GFX10-NEXT: s_cselect_b32 s6, s6, s9 -; GFX10-NEXT: s_cmp_lt_i32 s6, s5 -; GFX10-NEXT: s_cselect_b32 s5, s6, s5 -; GFX10-NEXT: s_add_i32 s4, s4, s5 ; GFX10-NEXT: ; return to shader part epilog %result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) ret <5 x i32> %result @@ -2239,244 +1625,44 @@ ; GFX9-LABEL: v_saddsat_v16i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s4, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v32, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v32, s4, v32 -; GFX9-NEXT: v_max_i32_e32 v16, v32, v16 -; GFX9-NEXT: s_brev_b32 s5, -2 -; GFX9-NEXT: v_max_i32_e32 v32, 0, v0 -; GFX9-NEXT: v_sub_u32_e32 v32, s5, v32 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v32 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v16 -; GFX9-NEXT: v_min_i32_e32 v16, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v16, s4, v16 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v17, 0, v1 -; GFX9-NEXT: v_sub_u32_e32 v17, s5, v17 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v16 -; GFX9-NEXT: v_min_i32_e32 v16, 0, v2 -; GFX9-NEXT: v_sub_u32_e32 v16, s4, v16 -; GFX9-NEXT: v_max_i32_e32 v17, 0, v2 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v18 -; GFX9-NEXT: v_sub_u32_e32 v17, s5, v17 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v16 -; GFX9-NEXT: v_mov_b32_e32 v16, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_bfrev_b32_e32 v18, -2 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v3 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v4 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v4 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v20 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v5 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v5 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v21 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v5, v5, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v6 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v6 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v22 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v7 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v7 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v23 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v7, v7, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v8 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v8 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v24 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v8, v8, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v9 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v9 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v25 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v9, v9, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v10 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v10 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v26 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v10, v10, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v11 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v11 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v27 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v11, v11, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v12 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v12 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v28 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v12, v12, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v13 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v13 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v29 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v13, v13, v17 -; GFX9-NEXT: v_min_i32_e32 v17, 0, v14 -; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17 -; GFX9-NEXT: v_max_i32_e32 v19, 0, v14 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v30 -; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_add_u32_e32 v14, v14, v17 -; GFX9-NEXT: v_max_i32_e32 v17, 0, v15 -; GFX9-NEXT: v_sub_u32_e32 v17, v18, v17 -; GFX9-NEXT: v_min_i32_e32 v18, 0, v15 -; GFX9-NEXT: v_sub_u32_e32 v16, v16, v18 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v31 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_add_u32_e32 v15, v15, v16 +; GFX9-NEXT: v_add_i32 v0, v0, v16 clamp +; GFX9-NEXT: v_add_i32 v1, v1, v17 clamp +; GFX9-NEXT: v_add_i32 v2, v2, v18 clamp +; GFX9-NEXT: v_add_i32 v3, v3, v19 clamp +; GFX9-NEXT: v_add_i32 v4, v4, v20 clamp +; GFX9-NEXT: v_add_i32 v5, v5, v21 clamp +; GFX9-NEXT: v_add_i32 v6, v6, v22 clamp +; GFX9-NEXT: v_add_i32 v7, v7, v23 clamp +; GFX9-NEXT: v_add_i32 v8, v8, v24 clamp +; GFX9-NEXT: v_add_i32 v9, v9, v25 clamp +; GFX9-NEXT: v_add_i32 v10, v10, v26 clamp +; GFX9-NEXT: v_add_i32 v11, v11, v27 clamp +; GFX9-NEXT: v_add_i32 v12, v12, v28 clamp +; GFX9-NEXT: v_add_i32 v13, v13, v29 clamp +; GFX9-NEXT: v_add_i32 v14, v14, v30 clamp +; GFX9-NEXT: v_add_i32 v15, v15, v31 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v16i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i32_e32 v32, 0, v0 -; GFX10-NEXT: s_mov_b32 s4, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v33, 0, v0 -; GFX10-NEXT: s_brev_b32 s5, -2 -; GFX10-NEXT: v_min_i32_e32 v36, 0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v35, s4, v32 -; GFX10-NEXT: v_min_i32_e32 v32, 0, v1 -; GFX10-NEXT: v_sub_nc_u32_e32 v33, s5, v33 -; GFX10-NEXT: v_max_i32_e32 v37, 0, v1 -; GFX10-NEXT: v_sub_nc_u32_e32 v36, s4, v36 -; GFX10-NEXT: v_max_i32_e32 v16, v35, v16 -; GFX10-NEXT: v_sub_nc_u32_e32 v32, s4, v32 -; GFX10-NEXT: v_mov_b32_e32 v35, 0x80000000 -; GFX10-NEXT: v_min_i32_e32 v38, 0, v3 -; GFX10-NEXT: v_max_i32_e32 v18, v36, v18 -; GFX10-NEXT: v_min_i32_e32 v16, v16, v33 -; GFX10-NEXT: v_max_i32_e32 v33, 0, v2 -; GFX10-NEXT: v_max_i32_e32 v39, v32, v17 -; GFX10-NEXT: v_sub_nc_u32_e32 v36, v35, v38 -; GFX10-NEXT: v_sub_nc_u32_e32 v37, s5, v37 -; GFX10-NEXT: v_bfrev_b32_e32 v34, -2 -; GFX10-NEXT: v_sub_nc_u32_e32 v32, s5, v33 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v16 -; GFX10-NEXT: v_max_i32_e32 v33, 0, v3 -; GFX10-NEXT: v_min_i32_e32 v39, v39, v37 -; GFX10-NEXT: v_max_i32_e32 v19, v36, v19 -; GFX10-NEXT: v_min_i32_e32 v16, v18, v32 -; GFX10-NEXT: v_min_i32_e32 v32, 0, v6 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v33 -; GFX10-NEXT: v_min_i32_e32 v38, 0, v5 -; GFX10-NEXT: v_max_i32_e32 v17, 0, v4 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v16 -; GFX10-NEXT: v_min_i32_e32 v16, 0, v4 -; GFX10-NEXT: v_min_i32_e32 v18, v19, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v35, v38 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v39 -; GFX10-NEXT: v_sub_nc_u32_e32 v32, v35, v32 -; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v16 -; GFX10-NEXT: v_max_i32_e32 v33, 0, v5 -; GFX10-NEXT: v_max_i32_e32 v36, 0, v6 -; GFX10-NEXT: v_max_i32_e32 v19, v19, v21 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v18 -; GFX10-NEXT: v_max_i32_e32 v16, v39, v20 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v34, v17 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v34, v33 -; GFX10-NEXT: v_sub_nc_u32_e32 v21, v34, v36 -; GFX10-NEXT: v_max_i32_e32 v22, v32, v22 -; GFX10-NEXT: v_min_i32_e32 v18, 0, v7 -; GFX10-NEXT: v_min_i32_e32 v39, v16, v17 -; GFX10-NEXT: v_min_i32_e32 v38, v19, v20 -; GFX10-NEXT: v_max_i32_e32 v16, 0, v7 -; GFX10-NEXT: v_min_i32_e32 v19, v22, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v35, v18 -; GFX10-NEXT: v_min_i32_e32 v18, 0, v8 -; GFX10-NEXT: v_min_i32_e32 v20, 0, v9 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v34, v16 -; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v19 -; GFX10-NEXT: v_max_i32_e32 v19, 0, v8 -; GFX10-NEXT: v_max_i32_e32 v17, v17, v23 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v35, v18 -; GFX10-NEXT: v_min_i32_e32 v22, 0, v10 -; GFX10-NEXT: v_max_i32_e32 v21, 0, v9 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v35, v20 -; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v39 -; GFX10-NEXT: v_max_i32_e32 v18, v18, v24 -; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v22 -; GFX10-NEXT: v_min_i32_e32 v16, v17, v16 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v34, v19 -; GFX10-NEXT: v_max_i32_e32 v23, 0, v10 -; GFX10-NEXT: v_max_i32_e32 v20, v20, v25 -; GFX10-NEXT: v_sub_nc_u32_e32 v21, v34, v21 -; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v16 -; GFX10-NEXT: v_min_i32_e32 v17, v18, v19 -; GFX10-NEXT: v_min_i32_e32 v16, 0, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v23 -; GFX10-NEXT: v_max_i32_e32 v19, v39, v26 -; GFX10-NEXT: v_min_i32_e32 v22, 0, v12 -; GFX10-NEXT: v_min_i32_e32 v20, v20, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v35, v16 -; GFX10-NEXT: v_min_i32_e32 v26, 0, v15 -; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v17 -; GFX10-NEXT: v_min_i32_e32 v17, v19, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v35, v22 -; GFX10-NEXT: v_min_i32_e32 v22, 0, v14 -; GFX10-NEXT: v_min_i32_e32 v21, 0, v13 -; GFX10-NEXT: v_max_i32_e32 v24, 0, v14 -; GFX10-NEXT: v_max_i32_e32 v25, 0, v15 -; GFX10-NEXT: v_add_nc_u32_e32 v9, v9, v20 -; GFX10-NEXT: v_max_i32_e32 v20, 0, v13 -; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v22 -; GFX10-NEXT: v_max_i32_e32 v23, 0, v11 -; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v17 -; GFX10-NEXT: v_max_i32_e32 v17, 0, v12 -; GFX10-NEXT: v_max_i32_e32 v16, v16, v27 -; GFX10-NEXT: v_sub_nc_u32_e32 v27, v35, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v26, v35, v26 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v23 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v34, v17 -; GFX10-NEXT: v_max_i32_e32 v19, v19, v28 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v34, v20 -; GFX10-NEXT: v_max_i32_e32 v21, v27, v29 -; GFX10-NEXT: v_sub_nc_u32_e32 v24, v34, v24 -; GFX10-NEXT: v_max_i32_e32 v22, v39, v30 -; GFX10-NEXT: v_sub_nc_u32_e32 v25, v34, v25 -; GFX10-NEXT: v_max_i32_e32 v23, v26, v31 -; GFX10-NEXT: v_min_i32_e32 v16, v16, v18 -; GFX10-NEXT: v_min_i32_e32 v17, v19, v17 -; GFX10-NEXT: v_min_i32_e32 v18, v21, v20 -; GFX10-NEXT: v_min_i32_e32 v19, v22, v24 -; GFX10-NEXT: v_min_i32_e32 v20, v23, v25 -; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v38 -; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v16 -; GFX10-NEXT: v_add_nc_u32_e32 v12, v12, v17 -; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v18 -; GFX10-NEXT: v_add_nc_u32_e32 v14, v14, v19 -; GFX10-NEXT: v_add_nc_u32_e32 v15, v15, v20 +; GFX10-NEXT: v_add_nc_i32 v0, v0, v16 clamp +; GFX10-NEXT: v_add_nc_i32 v1, v1, v17 clamp +; GFX10-NEXT: v_add_nc_i32 v2, v2, v18 clamp +; GFX10-NEXT: v_add_nc_i32 v3, v3, v19 clamp +; GFX10-NEXT: v_add_nc_i32 v4, v4, v20 clamp +; GFX10-NEXT: v_add_nc_i32 v5, v5, v21 clamp +; GFX10-NEXT: v_add_nc_i32 v6, v6, v22 clamp +; GFX10-NEXT: v_add_nc_i32 v7, v7, v23 clamp +; GFX10-NEXT: v_add_nc_i32 v8, v8, v24 clamp +; GFX10-NEXT: v_add_nc_i32 v9, v9, v25 clamp +; GFX10-NEXT: v_add_nc_i32 v10, v10, v26 clamp +; GFX10-NEXT: v_add_nc_i32 v11, v11, v27 clamp +; GFX10-NEXT: v_add_nc_i32 v12, v12, v28 clamp +; GFX10-NEXT: v_add_nc_i32 v13, v13, v29 clamp +; GFX10-NEXT: v_add_nc_i32 v14, v14, v30 clamp +; GFX10-NEXT: v_add_nc_i32 v15, v15, v31 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) @@ -2850,367 +2036,91 @@ ; ; GFX9-LABEL: s_saddsat_v16i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, 0 -; GFX9-NEXT: s_brev_b32 s32, -2 -; GFX9-NEXT: s_cselect_b32 s34, s0, 0 -; GFX9-NEXT: s_sub_i32 s34, s32, s34 -; GFX9-NEXT: s_cmp_lt_i32 s0, 0 -; GFX9-NEXT: s_mov_b32 s33, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s35, s0, 0 -; GFX9-NEXT: s_sub_i32 s35, s33, s35 -; GFX9-NEXT: s_cmp_gt_i32 s35, s16 -; GFX9-NEXT: s_cselect_b32 s16, s35, s16 -; GFX9-NEXT: s_cmp_lt_i32 s16, s34 -; GFX9-NEXT: s_cselect_b32 s16, s16, s34 -; GFX9-NEXT: s_add_i32 s0, s0, s16 -; GFX9-NEXT: s_cmp_gt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s16, s1, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s1, 0 -; GFX9-NEXT: s_cselect_b32 s34, s1, 0 -; GFX9-NEXT: s_sub_i32 s34, s33, s34 -; GFX9-NEXT: s_cmp_gt_i32 s34, s17 -; GFX9-NEXT: s_cselect_b32 s17, s34, s17 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s1, s1, s16 -; GFX9-NEXT: s_cmp_gt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s16, s2, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s2, 0 -; GFX9-NEXT: s_cselect_b32 s17, s2, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s18 -; GFX9-NEXT: s_cselect_b32 s17, s17, s18 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s2, s2, s16 -; GFX9-NEXT: s_cmp_gt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s16, s3, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s3, 0 -; GFX9-NEXT: s_cselect_b32 s17, s3, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s19 -; GFX9-NEXT: s_cselect_b32 s17, s17, s19 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s3, s3, s16 -; GFX9-NEXT: s_cmp_gt_i32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s16, s4, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s17, s4, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s20 -; GFX9-NEXT: s_cselect_b32 s17, s17, s20 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s4, s4, s16 -; GFX9-NEXT: s_cmp_gt_i32 s5, 0 -; GFX9-NEXT: s_cselect_b32 s16, s5, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s5, 0 -; GFX9-NEXT: s_cselect_b32 s17, s5, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s21 -; GFX9-NEXT: s_cselect_b32 s17, s17, s21 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s5, s5, s16 -; GFX9-NEXT: s_cmp_gt_i32 s6, 0 -; GFX9-NEXT: s_cselect_b32 s16, s6, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s6, 0 -; GFX9-NEXT: s_cselect_b32 s17, s6, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s22 -; GFX9-NEXT: s_cselect_b32 s17, s17, s22 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s6, s6, s16 -; GFX9-NEXT: s_cmp_gt_i32 s7, 0 -; GFX9-NEXT: s_cselect_b32 s16, s7, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s7, 0 -; GFX9-NEXT: s_cselect_b32 s17, s7, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s23 -; GFX9-NEXT: s_cselect_b32 s17, s17, s23 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s7, s7, s16 -; GFX9-NEXT: s_cmp_gt_i32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s16, s8, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s17, s8, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s24 -; GFX9-NEXT: s_cselect_b32 s17, s17, s24 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s8, s8, s16 -; GFX9-NEXT: s_cmp_gt_i32 s9, 0 -; GFX9-NEXT: s_cselect_b32 s16, s9, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s9, 0 -; GFX9-NEXT: s_cselect_b32 s17, s9, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s25 -; GFX9-NEXT: s_cselect_b32 s17, s17, s25 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s9, s9, s16 -; GFX9-NEXT: s_cmp_gt_i32 s10, 0 -; GFX9-NEXT: s_cselect_b32 s16, s10, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s10, 0 -; GFX9-NEXT: s_cselect_b32 s17, s10, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s26 -; GFX9-NEXT: s_cselect_b32 s17, s17, s26 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s10, s10, s16 -; GFX9-NEXT: s_cmp_gt_i32 s11, 0 -; GFX9-NEXT: s_cselect_b32 s16, s11, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s11, 0 -; GFX9-NEXT: s_cselect_b32 s17, s11, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s27 -; GFX9-NEXT: s_cselect_b32 s17, s17, s27 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s11, s11, s16 -; GFX9-NEXT: s_cmp_gt_i32 s12, 0 -; GFX9-NEXT: s_cselect_b32 s16, s12, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s12, 0 -; GFX9-NEXT: s_cselect_b32 s17, s12, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s28 -; GFX9-NEXT: s_cselect_b32 s17, s17, s28 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s12, s12, s16 -; GFX9-NEXT: s_cmp_gt_i32 s13, 0 -; GFX9-NEXT: s_cselect_b32 s16, s13, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s13, 0 -; GFX9-NEXT: s_cselect_b32 s17, s13, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s29 -; GFX9-NEXT: s_cselect_b32 s17, s17, s29 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s13, s13, s16 -; GFX9-NEXT: s_cmp_gt_i32 s14, 0 -; GFX9-NEXT: s_cselect_b32 s16, s14, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s14, 0 -; GFX9-NEXT: s_cselect_b32 s17, s14, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s30 -; GFX9-NEXT: s_cselect_b32 s17, s17, s30 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s14, s14, s16 -; GFX9-NEXT: s_cmp_gt_i32 s15, 0 -; GFX9-NEXT: s_cselect_b32 s16, s15, 0 -; GFX9-NEXT: s_sub_i32 s16, s32, s16 -; GFX9-NEXT: s_cmp_lt_i32 s15, 0 -; GFX9-NEXT: s_cselect_b32 s17, s15, 0 -; GFX9-NEXT: s_sub_i32 s17, s33, s17 -; GFX9-NEXT: s_cmp_gt_i32 s17, s31 -; GFX9-NEXT: s_cselect_b32 s17, s17, s31 -; GFX9-NEXT: s_cmp_lt_i32 s17, s16 -; GFX9-NEXT: s_cselect_b32 s16, s17, s16 -; GFX9-NEXT: s_add_i32 s15, s15, s16 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: v_mov_b32_e32 v14, s30 +; GFX9-NEXT: v_mov_b32_e32 v15, s31 +; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp +; GFX9-NEXT: v_add_i32 v5, s5, v5 clamp +; GFX9-NEXT: v_add_i32 v6, s6, v6 clamp +; GFX9-NEXT: v_add_i32 v7, s7, v7 clamp +; GFX9-NEXT: v_add_i32 v8, s8, v8 clamp +; GFX9-NEXT: v_add_i32 v9, s9, v9 clamp +; GFX9-NEXT: v_add_i32 v10, s10, v10 clamp +; GFX9-NEXT: v_add_i32 v11, s11, v11 clamp +; GFX9-NEXT: v_add_i32 v12, s12, v12 clamp +; GFX9-NEXT: v_add_i32 v13, s13, v13 clamp +; GFX9-NEXT: v_add_i32 v14, s14, v14 clamp +; GFX9-NEXT: v_add_i32 v15, s15, v15 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 +; GFX9-NEXT: v_readfirstlane_b32 s5, v5 +; GFX9-NEXT: v_readfirstlane_b32 s6, v6 +; GFX9-NEXT: v_readfirstlane_b32 s7, v7 +; GFX9-NEXT: v_readfirstlane_b32 s8, v8 +; GFX9-NEXT: v_readfirstlane_b32 s9, v9 +; GFX9-NEXT: v_readfirstlane_b32 s10, v10 +; GFX9-NEXT: v_readfirstlane_b32 s11, v11 +; GFX9-NEXT: v_readfirstlane_b32 s12, v12 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v16i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, 0 -; GFX10-NEXT: s_brev_b32 s32, -2 -; GFX10-NEXT: s_cselect_b32 s33, s0, 0 -; GFX10-NEXT: s_mov_b32 s34, 0x80000000 -; GFX10-NEXT: s_sub_i32 s46, s32, s33 -; GFX10-NEXT: s_cmp_lt_i32 s0, 0 +; GFX10-NEXT: v_add_nc_i32 v0, s0, s16 clamp +; GFX10-NEXT: v_add_nc_i32 v1, s1, s17 clamp +; GFX10-NEXT: v_add_nc_i32 v2, s2, s18 clamp +; GFX10-NEXT: v_add_nc_i32 v3, s3, s19 clamp +; GFX10-NEXT: v_add_nc_i32 v4, s4, s20 clamp +; GFX10-NEXT: v_add_nc_i32 v5, s5, s21 clamp +; GFX10-NEXT: v_add_nc_i32 v6, s6, s22 clamp +; GFX10-NEXT: v_add_nc_i32 v7, s7, s23 clamp +; GFX10-NEXT: v_add_nc_i32 v8, s8, s24 clamp +; GFX10-NEXT: v_add_nc_i32 v9, s9, s25 clamp +; GFX10-NEXT: v_add_nc_i32 v10, s10, s26 clamp +; GFX10-NEXT: v_add_nc_i32 v11, s11, s27 clamp +; GFX10-NEXT: v_add_nc_i32 v12, s12, s28 clamp +; GFX10-NEXT: v_add_nc_i32 v13, s13, s29 clamp +; GFX10-NEXT: v_add_nc_i32 v14, s14, s30 clamp +; GFX10-NEXT: v_add_nc_i32 v15, s15, s31 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 +; GFX10-NEXT: v_readfirstlane_b32 s5, v5 +; GFX10-NEXT: v_readfirstlane_b32 s6, v6 +; GFX10-NEXT: v_readfirstlane_b32 s7, v7 +; GFX10-NEXT: v_readfirstlane_b32 s8, v8 +; GFX10-NEXT: v_readfirstlane_b32 s9, v9 +; GFX10-NEXT: v_readfirstlane_b32 s10, v10 +; GFX10-NEXT: v_readfirstlane_b32 s11, v11 +; GFX10-NEXT: v_readfirstlane_b32 s12, v12 +; GFX10-NEXT: v_readfirstlane_b32 s13, v13 +; GFX10-NEXT: v_readfirstlane_b32 s14, v14 +; GFX10-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s35, s0, 0 -; GFX10-NEXT: s_sub_i32 s35, s34, s35 -; GFX10-NEXT: s_cmp_gt_i32 s35, s16 -; GFX10-NEXT: s_cselect_b32 s16, s35, s16 -; GFX10-NEXT: s_cmp_lt_i32 s16, s46 -; GFX10-NEXT: s_cselect_b32 s46, s16, s46 -; GFX10-NEXT: s_add_i32 s0, s0, s46 -; GFX10-NEXT: s_cmp_gt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s46, s1, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s1, 0 -; GFX10-NEXT: s_cselect_b32 s33, s1, 0 -; GFX10-NEXT: s_sub_i32 s46, s34, s33 -; GFX10-NEXT: s_cmp_gt_i32 s46, s17 -; GFX10-NEXT: s_cselect_b32 s17, s46, s17 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s46, s17, s16 -; GFX10-NEXT: s_add_i32 s1, s1, s46 -; GFX10-NEXT: s_cmp_gt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s46, s2, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s2, 0 -; GFX10-NEXT: s_cselect_b32 s17, s2, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s18 -; GFX10-NEXT: s_cselect_b32 s17, s17, s18 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s2, s2, s16 -; GFX10-NEXT: s_cmp_gt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s46, s3, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s3, 0 -; GFX10-NEXT: s_cselect_b32 s17, s3, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s19 -; GFX10-NEXT: s_cselect_b32 s17, s17, s19 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s3, s3, s16 -; GFX10-NEXT: s_cmp_gt_i32 s4, 0 -; GFX10-NEXT: s_cselect_b32 s46, s4, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s4, 0 -; GFX10-NEXT: s_cselect_b32 s17, s4, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s20 -; GFX10-NEXT: s_cselect_b32 s17, s17, s20 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s4, s4, s16 -; GFX10-NEXT: s_cmp_gt_i32 s5, 0 -; GFX10-NEXT: s_cselect_b32 s46, s5, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s5, 0 -; GFX10-NEXT: s_cselect_b32 s17, s5, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s21 -; GFX10-NEXT: s_cselect_b32 s17, s17, s21 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s5, s5, s16 -; GFX10-NEXT: s_cmp_gt_i32 s6, 0 -; GFX10-NEXT: s_cselect_b32 s46, s6, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s6, 0 -; GFX10-NEXT: s_cselect_b32 s17, s6, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s22 -; GFX10-NEXT: s_cselect_b32 s17, s17, s22 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s6, s6, s16 -; GFX10-NEXT: s_cmp_gt_i32 s7, 0 -; GFX10-NEXT: s_cselect_b32 s46, s7, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s7, 0 -; GFX10-NEXT: s_cselect_b32 s17, s7, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s23 -; GFX10-NEXT: s_cselect_b32 s17, s17, s23 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s7, s7, s16 -; GFX10-NEXT: s_cmp_gt_i32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s46, s8, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s17, s8, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s24 -; GFX10-NEXT: s_cselect_b32 s17, s17, s24 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s8, s8, s16 -; GFX10-NEXT: s_cmp_gt_i32 s9, 0 -; GFX10-NEXT: s_cselect_b32 s46, s9, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s9, 0 -; GFX10-NEXT: s_cselect_b32 s17, s9, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s25 -; GFX10-NEXT: s_cselect_b32 s17, s17, s25 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s9, s9, s16 -; GFX10-NEXT: s_cmp_gt_i32 s10, 0 -; GFX10-NEXT: s_cselect_b32 s46, s10, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s10, 0 -; GFX10-NEXT: s_cselect_b32 s17, s10, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s26 -; GFX10-NEXT: s_cselect_b32 s17, s17, s26 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s10, s10, s16 -; GFX10-NEXT: s_cmp_gt_i32 s11, 0 -; GFX10-NEXT: s_cselect_b32 s46, s11, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s11, 0 -; GFX10-NEXT: s_cselect_b32 s17, s11, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s27 -; GFX10-NEXT: s_cselect_b32 s17, s17, s27 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s11, s11, s16 -; GFX10-NEXT: s_cmp_gt_i32 s12, 0 -; GFX10-NEXT: s_cselect_b32 s46, s12, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s12, 0 -; GFX10-NEXT: s_cselect_b32 s17, s12, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s28 -; GFX10-NEXT: s_cselect_b32 s17, s17, s28 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s12, s12, s16 -; GFX10-NEXT: s_cmp_gt_i32 s13, 0 -; GFX10-NEXT: s_cselect_b32 s46, s13, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s13, 0 -; GFX10-NEXT: s_cselect_b32 s17, s13, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s29 -; GFX10-NEXT: s_cselect_b32 s17, s17, s29 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s13, s13, s16 -; GFX10-NEXT: s_cmp_gt_i32 s14, 0 -; GFX10-NEXT: s_cselect_b32 s46, s14, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s46 -; GFX10-NEXT: s_cmp_lt_i32 s14, 0 -; GFX10-NEXT: s_cselect_b32 s17, s14, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s30 -; GFX10-NEXT: s_cselect_b32 s17, s17, s30 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s14, s14, s16 -; GFX10-NEXT: s_cmp_gt_i32 s15, 0 -; GFX10-NEXT: s_cselect_b32 s30, s15, 0 -; GFX10-NEXT: s_sub_i32 s16, s32, s30 -; GFX10-NEXT: s_cmp_lt_i32 s15, 0 -; GFX10-NEXT: s_cselect_b32 s17, s15, 0 -; GFX10-NEXT: s_sub_i32 s17, s34, s17 -; GFX10-NEXT: s_cmp_gt_i32 s17, s31 -; GFX10-NEXT: s_cselect_b32 s17, s17, s31 -; GFX10-NEXT: s_cmp_lt_i32 s17, s16 -; GFX10-NEXT: s_cselect_b32 s16, s17, s16 -; GFX10-NEXT: s_add_i32 s15, s15, s16 ; GFX10-NEXT: ; return to shader part epilog %result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) ret <16 x i32> %result @@ -3247,27 +2157,15 @@ ; GFX9-LABEL: v_saddsat_i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_i16_e32 v3, 0, v0 -; GFX9-NEXT: v_max_i16_e32 v2, 0, v0 -; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_max_i16_e32 v1, v3, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v2 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_i16_e64 v2, v0, 0 -; GFX10-NEXT: v_max_i16_e64 v3, v0, 0 +; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2 -; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -3315,45 +2213,16 @@ ; ; GFX9-LABEL: s_saddsat_i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sext_i32_i16 s2, s0 -; GFX9-NEXT: s_sext_i32_i16 s3, 0 -; GFX9-NEXT: s_cmp_gt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s4, s2, s3 -; GFX9-NEXT: s_sub_i32 s4, 0x7fff, s4 -; GFX9-NEXT: s_cmp_lt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_sub_i32 s2, 0x8000, s2 -; GFX9-NEXT: s_sext_i32_i16 s2, s2 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s2, s4 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_add_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sext_i32_i16 s2, 0 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s2 +; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s4, s3, s2 -; GFX10-NEXT: s_sub_i32 s4, 0x7fff, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, s2 -; GFX10-NEXT: s_cselect_b32 s2, s3, s2 -; GFX10-NEXT: s_sub_i32 s2, 0x8000, s2 -; GFX10-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-NEXT: s_cmp_gt_i32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_sext_i32_i16 s2, s4 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_add_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -3393,33 +2262,13 @@ ; ; GFX9-LABEL: saddsat_i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sext_i32_i16 s1, s0 -; GFX9-NEXT: s_sext_i32_i16 s2, 0 -; GFX9-NEXT: s_cmp_gt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s3, s1, s2 -; GFX9-NEXT: s_sub_i32 s3, 0x7fff, s3 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_sub_i32 s1, 0x8000, s1 -; GFX9-NEXT: v_max_i16_e32 v0, s1, v0 -; GFX9-NEXT: v_min_i16_e32 v0, s3, v0 -; GFX9-NEXT: v_add_u16_e32 v0, s0, v0 +; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sext_i32_i16 s1, s0 -; GFX10-NEXT: s_sext_i32_i16 s2, 0 +; GFX10-NEXT: v_add_nc_i16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_gt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s3, s1, s2 -; GFX10-NEXT: s_sub_i32 s3, 0x7fff, s3 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_sub_i32 s1, 0x8000, s1 -; GFX10-NEXT: v_max_i16_e64 v0, s1, v0 -; GFX10-NEXT: v_min_i16_e64 v0, v0, s3 -; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -3454,25 +2303,13 @@ ; ; GFX9-LABEL: saddsat_i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_i16_e32 v2, 0, v0 -; GFX9-NEXT: v_max_i16_e32 v1, 0, v0 -; GFX9-NEXT: v_sub_u16_e32 v2, 0x8000, v2 -; GFX9-NEXT: v_sub_u16_e32 v1, 0x7fff, v1 -; GFX9-NEXT: v_max_i16_e32 v2, s0, v2 -; GFX9-NEXT: v_min_i16_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_i16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_i16_e64 v1, v0, 0 -; GFX10-NEXT: v_max_i16_e64 v2, v0, 0 +; GFX10-NEXT: v_add_nc_i16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u16_e64 v1, 0x8000, v1 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x7fff, v2 -; GFX10-NEXT: v_max_i16_e64 v1, v1, s0 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v2 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -3533,37 +2370,15 @@ ; GFX9-LABEL: v_saddsat_v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v3, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v3, s5, v3 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v2, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v2, s4, v2 -; GFX9-NEXT: v_pk_max_i16 v1, v3, v1 -; GFX9-NEXT: v_pk_min_i16 v1, v1, v2 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 +; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v2i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, 0, 0 -; GFX10-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX10-NEXT: v_pk_min_i16 v2, v0, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX10-NEXT: v_pk_max_i16 v3, v0, s4 -; GFX10-NEXT: s_movk_i32 s6, 0x7fff +; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v2, s5, v2 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s6, s6 -; GFX10-NEXT: v_pk_sub_i16 v3, s4, v3 -; GFX10-NEXT: v_pk_max_i16 v1, v2, v1 -; GFX10-NEXT: v_pk_min_i16 v1, v1, v3 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) ret <2 x i16> %result @@ -3656,115 +2471,16 @@ ; ; GFX9-LABEL: s_saddsat_v2i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s4, 0, 0 -; GFX9-NEXT: s_sext_i32_i16 s7, s4 -; GFX9-NEXT: s_sext_i32_i16 s5, s0 -; GFX9-NEXT: s_ashr_i32 s6, s0, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s8, s5, s7 -; GFX9-NEXT: s_cmp_gt_i32 s6, s4 -; GFX9-NEXT: s_movk_i32 s2, 0x7fff -; GFX9-NEXT: s_cselect_b32 s9, s6, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: s_lshr_b32 s9, s2, 16 -; GFX9-NEXT: s_lshr_b32 s10, s8, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s8 -; GFX9-NEXT: s_sub_i32 s8, s9, s10 -; GFX9-NEXT: s_cmp_lt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_i32 s6, s4 -; GFX9-NEXT: s_mov_b32 s3, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s4, s6, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s3 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_sub_i32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s4, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_sext_i32_i16 s5, s1 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s1, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s1 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s8 -; GFX9-NEXT: s_sext_i32_i16 s3, s1 -; GFX9-NEXT: s_sext_i32_i16 s4, s2 -; GFX9-NEXT: s_ashr_i32 s1, s1, 16 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s3, s1 -; GFX9-NEXT: s_lshr_b32 s2, s0, 16 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_add_i32 s2, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v2i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s2, 0, 0 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s5, s2 -; GFX10-NEXT: s_ashr_i32 s4, s0, 16 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s3, s5 -; GFX10-NEXT: s_movk_i32 s7, 0x7fff -; GFX10-NEXT: s_cselect_b32 s6, s3, s5 -; GFX10-NEXT: s_cmp_gt_i32 s4, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s7 -; GFX10-NEXT: s_cselect_b32 s8, s4, s2 +; GFX10-NEXT: v_pk_add_i16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8 -; GFX10-NEXT: s_lshr_b32 s8, s7, 16 -; GFX10-NEXT: s_lshr_b32 s9, s6, 16 -; GFX10-NEXT: s_sub_i32 s6, s7, s6 -; GFX10-NEXT: s_sub_i32 s7, s8, s9 -; GFX10-NEXT: s_cmp_lt_i32 s3, s5 -; GFX10-NEXT: s_cselect_b32 s3, s3, s5 -; GFX10-NEXT: s_cmp_lt_i32 s4, s2 -; GFX10-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s2, s4, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s2 -; GFX10-NEXT: s_lshr_b32 s3, s4, 16 -; GFX10-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-NEXT: s_sub_i32 s2, s4, s2 -; GFX10-NEXT: s_sub_i32 s3, s3, s5 -; GFX10-NEXT: s_sext_i32_i16 s4, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_sext_i32_i16 s3, s2 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_cmp_gt_i32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s4, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s1 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_lshr_b32 s2, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_add_i32 s2, s2, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to i32 @@ -3840,75 +2556,13 @@ ; ; GFX9-LABEL: saddsat_v2i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s3, 0, 0 -; GFX9-NEXT: s_sext_i32_i16 s6, s3 -; GFX9-NEXT: s_sext_i32_i16 s4, s0 -; GFX9-NEXT: s_ashr_i32 s5, s0, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s7, s4, s6 -; GFX9-NEXT: s_cmp_gt_i32 s5, s3 -; GFX9-NEXT: s_movk_i32 s1, 0x7fff -; GFX9-NEXT: s_cselect_b32 s8, s5, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s1 -; GFX9-NEXT: s_lshr_b32 s8, s1, 16 -; GFX9-NEXT: s_lshr_b32 s9, s7, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s7 -; GFX9-NEXT: s_sub_i32 s7, s8, s9 -; GFX9-NEXT: s_cmp_lt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_cmp_lt_i32 s5, s3 -; GFX9-NEXT: s_mov_b32 s2, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s3, s5, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s3 -; GFX9-NEXT: s_sub_i32 s3, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s7 -; GFX9-NEXT: v_pk_max_i16 v0, s2, v0 -; GFX9-NEXT: v_pk_min_i16 v0, v0, s1 -; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 +; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_v2i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, 0, 0 -; GFX10-NEXT: s_sext_i32_i16 s2, s0 -; GFX10-NEXT: s_sext_i32_i16 s4, s1 -; GFX10-NEXT: s_ashr_i32 s3, s0, 16 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s2, s4 -; GFX10-NEXT: s_movk_i32 s6, 0x7fff -; GFX10-NEXT: s_cselect_b32 s5, s2, s4 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: s_cselect_b32 s7, s3, s1 +; GFX10-NEXT: v_pk_add_i16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GFX10-NEXT: s_lshr_b32 s7, s6, 16 -; GFX10-NEXT: s_lshr_b32 s8, s5, 16 -; GFX10-NEXT: s_sub_i32 s5, s6, s5 -; GFX10-NEXT: s_sub_i32 s6, s7, s8 -; GFX10-NEXT: s_cmp_lt_i32 s2, s4 -; GFX10-NEXT: s_cselect_b32 s2, s2, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, s1 -; GFX10-NEXT: s_mov_b32 s4, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX10-NEXT: s_lshr_b32 s2, s3, 16 -; GFX10-NEXT: s_lshr_b32 s4, s1, 16 -; GFX10-NEXT: s_sub_i32 s1, s3, s1 -; GFX10-NEXT: s_sub_i32 s2, s2, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2 -; GFX10-NEXT: v_pk_max_i16 v0, s1, v0 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s5, s6 -; GFX10-NEXT: v_pk_min_i16 v0, v0, s1 -; GFX10-NEXT: v_pk_add_u16 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -3972,35 +2626,13 @@ ; ; GFX9-LABEL: saddsat_v2i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s2, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, 0, 0 -; GFX9-NEXT: s_movk_i32 s1, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: v_pk_min_i16 v2, v0, s3 -; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s1 -; GFX9-NEXT: v_pk_max_i16 v1, v0, s3 -; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 -; GFX9-NEXT: v_pk_max_i16 v2, v2, s0 -; GFX9-NEXT: v_pk_min_i16 v1, v2, v1 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 +; GFX9-NEXT: v_pk_add_i16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: saddsat_v2i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, 0, 0 -; GFX10-NEXT: s_mov_b32 s2, 0xffff8000 -; GFX10-NEXT: v_pk_min_i16 v1, v0, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX10-NEXT: v_pk_max_i16 v2, v0, s1 -; GFX10-NEXT: s_movk_i32 s3, 0x7fff +; GFX10-NEXT: v_pk_add_i16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v1, s2, v1 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s3 -; GFX10-NEXT: v_pk_sub_i16 v2, s1, v2 -; GFX10-NEXT: v_pk_max_i16 v1, v1, s0 -; GFX10-NEXT: v_pk_min_i16 v1, v1, v2 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -4119,51 +2751,17 @@ ; GFX9-LABEL: v_saddsat_v4i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v5, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v5, s5, v5 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v4, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, s4, v4 -; GFX9-NEXT: v_pk_max_i16 v2, v5, v2 -; GFX9-NEXT: v_pk_min_i16 v2, v2, v4 -; GFX9-NEXT: v_pk_min_i16 v4, v1, s6 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 -; GFX9-NEXT: v_pk_max_i16 v2, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, s5, v4 -; GFX9-NEXT: v_pk_sub_i16 v2, s4, v2 -; GFX9-NEXT: v_pk_max_i16 v3, v4, v3 -; GFX9-NEXT: v_pk_min_i16 v2, v3, v2 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v2 +; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v4i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, 0, 0 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 -; GFX10-NEXT: v_pk_min_i16 v4, v0, s5 -; GFX10-NEXT: v_pk_min_i16 v5, v1, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v6, v0, s5 -; GFX10-NEXT: v_pk_max_i16 v7, v1, s5 -; GFX10-NEXT: v_pk_sub_i16 v4, s6, v4 -; GFX10-NEXT: v_pk_sub_i16 v5, s6, v5 -; GFX10-NEXT: s_movk_i32 s4, 0x7fff +; GFX10-NEXT: v_pk_add_i16 v0, v0, v2 clamp +; GFX10-NEXT: v_pk_add_i16 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX10-NEXT: v_pk_max_i16 v11, v4, v2 -; GFX10-NEXT: v_pk_sub_i16 v6, s4, v6 -; GFX10-NEXT: v_pk_sub_i16 v4, s4, v7 -; GFX10-NEXT: v_pk_max_i16 v3, v5, v3 -; GFX10-NEXT: v_pk_min_i16 v2, v11, v6 -; GFX10-NEXT: v_pk_min_i16 v3, v3, v4 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x float> @@ -4327,201 +2925,21 @@ ; ; GFX9-LABEL: s_saddsat_v4i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX9-NEXT: s_sext_i32_i16 s9, s6 -; GFX9-NEXT: s_sext_i32_i16 s7, s0 -; GFX9-NEXT: s_ashr_i32 s8, s0, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_gt_i32 s7, s9 -; GFX9-NEXT: s_cselect_b32 s10, s7, s9 -; GFX9-NEXT: s_cmp_gt_i32 s8, s6 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_cselect_b32 s11, s8, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: s_lshr_b32 s12, s10, 16 -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_sub_i32 s10, s4, s10 -; GFX9-NEXT: s_sub_i32 s12, s11, s12 -; GFX9-NEXT: s_cmp_lt_i32 s7, s9 -; GFX9-NEXT: s_cselect_b32 s7, s7, s9 -; GFX9-NEXT: s_cmp_lt_i32 s8, s6 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s8, s8, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s12 -; GFX9-NEXT: s_lshr_b32 s12, s7, 16 -; GFX9-NEXT: s_lshr_b32 s8, s5, 16 -; GFX9-NEXT: s_sub_i32 s7, s5, s7 -; GFX9-NEXT: s_sub_i32 s12, s8, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s12 -; GFX9-NEXT: s_sext_i32_i16 s12, s7 -; GFX9-NEXT: s_sext_i32_i16 s13, s2 -; GFX9-NEXT: s_ashr_i32 s7, s7, 16 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s12, s13 -; GFX9-NEXT: s_cselect_b32 s12, s12, s13 -; GFX9-NEXT: s_cmp_gt_i32 s7, s2 -; GFX9-NEXT: s_cselect_b32 s2, s7, s2 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s12, s2 -; GFX9-NEXT: s_sext_i32_i16 s7, s2 -; GFX9-NEXT: s_sext_i32_i16 s12, s10 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_ashr_i32 s10, s10, 16 -; GFX9-NEXT: s_cmp_lt_i32 s7, s12 -; GFX9-NEXT: s_cselect_b32 s7, s7, s12 -; GFX9-NEXT: s_cmp_lt_i32 s2, s10 -; GFX9-NEXT: s_cselect_b32 s2, s2, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s7, s2 -; GFX9-NEXT: s_lshr_b32 s7, s0, 16 -; GFX9-NEXT: s_lshr_b32 s10, s2, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s2 -; GFX9-NEXT: s_add_i32 s7, s7, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s7 -; GFX9-NEXT: s_sext_i32_i16 s2, s1 -; GFX9-NEXT: s_ashr_i32 s7, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s2, s9 -; GFX9-NEXT: s_cselect_b32 s10, s2, s9 -; GFX9-NEXT: s_cmp_gt_i32 s7, s6 -; GFX9-NEXT: s_cselect_b32 s12, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s12 -; GFX9-NEXT: s_lshr_b32 s12, s10, 16 -; GFX9-NEXT: s_sub_i32 s4, s4, s10 -; GFX9-NEXT: s_sub_i32 s10, s11, s12 -; GFX9-NEXT: s_cmp_lt_i32 s2, s9 -; GFX9-NEXT: s_cselect_b32 s2, s2, s9 -; GFX9-NEXT: s_cmp_lt_i32 s7, s6 -; GFX9-NEXT: s_cselect_b32 s6, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX9-NEXT: s_lshr_b32 s6, s2, 16 -; GFX9-NEXT: s_sub_i32 s2, s5, s2 -; GFX9-NEXT: s_sub_i32 s5, s8, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX9-NEXT: s_sext_i32_i16 s5, s2 -; GFX9-NEXT: s_sext_i32_i16 s6, s3 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_gt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s5, s2 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10 -; GFX9-NEXT: s_sext_i32_i16 s3, s2 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_lt_i32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s3, s3, s5 -; GFX9-NEXT: s_cmp_lt_i32 s2, s4 -; GFX9-NEXT: s_cselect_b32 s2, s2, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s2 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s2 -; GFX9-NEXT: s_add_i32 s3, s3, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v4i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s4, 0, 0 -; GFX10-NEXT: s_sext_i32_i16 s5, s0 -; GFX10-NEXT: s_sext_i32_i16 s7, s4 -; GFX10-NEXT: s_ashr_i32 s6, s0, 16 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_gt_i32 s5, s7 -; GFX10-NEXT: s_movk_i32 s9, 0x7fff -; GFX10-NEXT: s_cselect_b32 s8, s5, s7 -; GFX10-NEXT: s_cmp_gt_i32 s6, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s9 -; GFX10-NEXT: s_cselect_b32 s10, s6, s4 -; GFX10-NEXT: s_mov_b32 s12, 0xffff8000 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10 -; GFX10-NEXT: s_lshr_b32 s10, s9, 16 -; GFX10-NEXT: s_lshr_b32 s11, s8, 16 -; GFX10-NEXT: s_sub_i32 s8, s9, s8 -; GFX10-NEXT: s_sub_i32 s11, s10, s11 -; GFX10-NEXT: s_cmp_lt_i32 s5, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s12 -; GFX10-NEXT: s_cselect_b32 s5, s5, s7 -; GFX10-NEXT: s_cmp_lt_i32 s6, s4 -; GFX10-NEXT: s_sext_i32_i16 s14, s2 -; GFX10-NEXT: s_cselect_b32 s6, s6, s4 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX10-NEXT: s_lshr_b32 s6, s12, 16 -; GFX10-NEXT: s_lshr_b32 s13, s5, 16 -; GFX10-NEXT: s_sub_i32 s5, s12, s5 -; GFX10-NEXT: s_sub_i32 s13, s6, s13 +; GFX10-NEXT: v_pk_add_i16 v0, s0, s2 clamp +; GFX10-NEXT: v_pk_add_i16 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s13 -; GFX10-NEXT: s_sext_i32_i16 s13, s5 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_gt_i32 s13, s14 -; GFX10-NEXT: s_cselect_b32 s13, s13, s14 -; GFX10-NEXT: s_cmp_gt_i32 s5, s2 -; GFX10-NEXT: s_cselect_b32 s2, s5, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s8, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s13, s2 -; GFX10-NEXT: s_sext_i32_i16 s11, s5 -; GFX10-NEXT: s_sext_i32_i16 s8, s2 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_i32 s8, s11 -; GFX10-NEXT: s_cselect_b32 s8, s8, s11 -; GFX10-NEXT: s_cmp_lt_i32 s2, s5 -; GFX10-NEXT: s_cselect_b32 s2, s2, s5 -; GFX10-NEXT: s_lshr_b32 s5, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s8, s2 -; GFX10-NEXT: s_lshr_b32 s8, s2, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s2 -; GFX10-NEXT: s_sext_i32_i16 s2, s1 -; GFX10-NEXT: s_add_i32 s5, s5, s8 -; GFX10-NEXT: s_ashr_i32 s8, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s2, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s5 -; GFX10-NEXT: s_cselect_b32 s11, s2, s7 -; GFX10-NEXT: s_cmp_gt_i32 s8, s4 -; GFX10-NEXT: s_cselect_b32 s13, s8, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s13 -; GFX10-NEXT: s_lshr_b32 s13, s11, 16 -; GFX10-NEXT: s_sub_i32 s9, s9, s11 -; GFX10-NEXT: s_sub_i32 s10, s10, s13 -; GFX10-NEXT: s_cmp_lt_i32 s2, s7 -; GFX10-NEXT: s_cselect_b32 s2, s2, s7 -; GFX10-NEXT: s_cmp_lt_i32 s8, s4 -; GFX10-NEXT: s_cselect_b32 s4, s8, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_sub_i32 s2, s12, s2 -; GFX10-NEXT: s_sub_i32 s4, s6, s4 -; GFX10-NEXT: s_sext_i32_i16 s6, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_sext_i32_i16 s4, s2 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s4, s6 -; GFX10-NEXT: s_cselect_b32 s4, s4, s6 -; GFX10-NEXT: s_cmp_gt_i32 s2, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s9, s10 -; GFX10-NEXT: s_cselect_b32 s2, s2, s3 -; GFX10-NEXT: s_sext_i32_i16 s3, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s2 -; GFX10-NEXT: s_ashr_i32 s4, s6, 16 -; GFX10-NEXT: s_sext_i32_i16 s6, s2 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_lt_i32 s6, s3 -; GFX10-NEXT: s_cselect_b32 s3, s6, s3 -; GFX10-NEXT: s_cmp_lt_i32 s2, s4 -; GFX10-NEXT: s_cselect_b32 s2, s2, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s2 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s2 -; GFX10-NEXT: s_add_i32 s3, s3, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x i32> @@ -4682,65 +3100,19 @@ ; GFX9-LABEL: v_saddsat_v6i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v7, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v7, s5, v7 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v6, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v6, s4, v6 -; GFX9-NEXT: v_pk_max_i16 v3, v7, v3 -; GFX9-NEXT: v_pk_min_i16 v3, v3, v6 -; GFX9-NEXT: v_pk_min_i16 v6, v1, s6 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v3 -; GFX9-NEXT: v_pk_max_i16 v3, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v6, s5, v6 -; GFX9-NEXT: v_pk_sub_i16 v3, s4, v3 -; GFX9-NEXT: v_pk_max_i16 v4, v6, v4 -; GFX9-NEXT: v_pk_min_i16 v3, v4, v3 -; GFX9-NEXT: v_pk_min_i16 v4, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, s5, v4 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 -; GFX9-NEXT: v_pk_max_i16 v3, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v3, s4, v3 -; GFX9-NEXT: v_pk_max_i16 v4, v4, v5 -; GFX9-NEXT: v_pk_min_i16 v3, v4, v3 -; GFX9-NEXT: v_pk_add_u16 v2, v2, v3 +; GFX9-NEXT: v_pk_add_i16 v0, v0, v3 clamp +; GFX9-NEXT: v_pk_add_i16 v1, v1, v4 clamp +; GFX9-NEXT: v_pk_add_i16 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v6i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, 0, 0 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 -; GFX10-NEXT: v_pk_min_i16 v7, v0, s5 -; GFX10-NEXT: v_pk_min_i16 v8, v1, s5 -; GFX10-NEXT: v_pk_min_i16 v9, v2, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v6, v0, s5 -; GFX10-NEXT: v_pk_sub_i16 v14, s6, v7 -; GFX10-NEXT: v_pk_sub_i16 v15, s6, v8 -; GFX10-NEXT: v_pk_sub_i16 v19, s6, v9 -; GFX10-NEXT: v_pk_max_i16 v10, v1, s5 -; GFX10-NEXT: v_pk_max_i16 v11, v2, s5 -; GFX10-NEXT: s_movk_i32 s4, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v3, v14, v3 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX10-NEXT: v_pk_max_i16 v4, v15, v4 -; GFX10-NEXT: v_pk_sub_i16 v6, s4, v6 -; GFX10-NEXT: v_pk_sub_i16 v7, s4, v10 -; GFX10-NEXT: v_pk_sub_i16 v8, s4, v11 -; GFX10-NEXT: v_pk_max_i16 v5, v19, v5 +; GFX10-NEXT: v_pk_add_i16 v0, v0, v3 clamp +; GFX10-NEXT: v_pk_add_i16 v1, v1, v4 clamp +; GFX10-NEXT: v_pk_add_i16 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_min_i16 v3, v3, v6 -; GFX10-NEXT: v_pk_min_i16 v4, v4, v7 -; GFX10-NEXT: v_pk_min_i16 v5, v5, v8 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v3 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v4 -; GFX10-NEXT: v_pk_add_u16 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x float> @@ -4974,287 +3346,26 @@ ; ; GFX9-LABEL: s_saddsat_v6i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s8, 0, 0 -; GFX9-NEXT: s_sext_i32_i16 s11, s8 -; GFX9-NEXT: s_sext_i32_i16 s9, s0 -; GFX9-NEXT: s_ashr_i32 s10, s0, 16 -; GFX9-NEXT: s_ashr_i32 s8, s8, 16 -; GFX9-NEXT: s_cmp_gt_i32 s9, s11 -; GFX9-NEXT: s_cselect_b32 s12, s9, s11 -; GFX9-NEXT: s_cmp_gt_i32 s10, s8 -; GFX9-NEXT: s_movk_i32 s6, 0x7fff -; GFX9-NEXT: s_cselect_b32 s13, s10, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX9-NEXT: s_lshr_b32 s14, s12, 16 -; GFX9-NEXT: s_lshr_b32 s13, s6, 16 -; GFX9-NEXT: s_sub_i32 s12, s6, s12 -; GFX9-NEXT: s_sub_i32 s14, s13, s14 -; GFX9-NEXT: s_cmp_lt_i32 s9, s11 -; GFX9-NEXT: s_cselect_b32 s9, s9, s11 -; GFX9-NEXT: s_cmp_lt_i32 s10, s8 -; GFX9-NEXT: s_mov_b32 s7, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s10, s10, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s10, s7, 16 -; GFX9-NEXT: s_sub_i32 s9, s7, s9 -; GFX9-NEXT: s_sub_i32 s14, s10, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX9-NEXT: s_sext_i32_i16 s14, s9 -; GFX9-NEXT: s_sext_i32_i16 s15, s3 -; GFX9-NEXT: s_ashr_i32 s9, s9, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s14, s15 -; GFX9-NEXT: s_cselect_b32 s14, s14, s15 -; GFX9-NEXT: s_cmp_gt_i32 s9, s3 -; GFX9-NEXT: s_cselect_b32 s3, s9, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s14, s3 -; GFX9-NEXT: s_sext_i32_i16 s9, s3 -; GFX9-NEXT: s_sext_i32_i16 s14, s12 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s12, s12, 16 -; GFX9-NEXT: s_cmp_lt_i32 s9, s14 -; GFX9-NEXT: s_cselect_b32 s9, s9, s14 -; GFX9-NEXT: s_cmp_lt_i32 s3, s12 -; GFX9-NEXT: s_cselect_b32 s3, s3, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s9, s3 -; GFX9-NEXT: s_lshr_b32 s9, s0, 16 -; GFX9-NEXT: s_lshr_b32 s12, s3, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s3 -; GFX9-NEXT: s_add_i32 s9, s9, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s9 -; GFX9-NEXT: s_sext_i32_i16 s3, s1 -; GFX9-NEXT: s_ashr_i32 s9, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s12, s3, s11 -; GFX9-NEXT: s_cmp_gt_i32 s9, s8 -; GFX9-NEXT: s_cselect_b32 s14, s9, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX9-NEXT: s_lshr_b32 s14, s12, 16 -; GFX9-NEXT: s_sub_i32 s12, s6, s12 -; GFX9-NEXT: s_sub_i32 s14, s13, s14 -; GFX9-NEXT: s_cmp_lt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s3, s3, s11 -; GFX9-NEXT: s_cmp_lt_i32 s9, s8 -; GFX9-NEXT: s_cselect_b32 s9, s9, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s9 -; GFX9-NEXT: s_lshr_b32 s9, s3, 16 -; GFX9-NEXT: s_sub_i32 s3, s7, s3 -; GFX9-NEXT: s_sub_i32 s9, s10, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX9-NEXT: s_sext_i32_i16 s9, s3 -; GFX9-NEXT: s_sext_i32_i16 s14, s4 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s9, s14 -; GFX9-NEXT: s_cselect_b32 s9, s9, s14 -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s9, s3 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_sext_i32_i16 s9, s12 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s12, s12, 16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s9 -; GFX9-NEXT: s_cselect_b32 s4, s4, s9 -; GFX9-NEXT: s_cmp_lt_i32 s3, s12 -; GFX9-NEXT: s_cselect_b32 s3, s3, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX9-NEXT: s_lshr_b32 s4, s1, 16 -; GFX9-NEXT: s_lshr_b32 s9, s3, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_sext_i32_i16 s3, s2 -; GFX9-NEXT: s_ashr_i32 s4, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s9, s3, s11 -; GFX9-NEXT: s_cmp_gt_i32 s4, s8 -; GFX9-NEXT: s_cselect_b32 s12, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s12 -; GFX9-NEXT: s_lshr_b32 s12, s9, 16 -; GFX9-NEXT: s_sub_i32 s6, s6, s9 -; GFX9-NEXT: s_sub_i32 s9, s13, s12 -; GFX9-NEXT: s_cmp_lt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s3, s3, s11 -; GFX9-NEXT: s_cmp_lt_i32 s4, s8 -; GFX9-NEXT: s_cselect_b32 s4, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_sub_i32 s3, s7, s3 -; GFX9-NEXT: s_sub_i32 s4, s10, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_sext_i32_i16 s7, s5 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_cmp_gt_i32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s3, s3, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s9 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_sext_i32_i16 s5, s6 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, s6 -; GFX9-NEXT: s_cselect_b32 s3, s3, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_add_i32 s2, s2, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_add_i16 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v6i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX10-NEXT: s_sext_i32_i16 s7, s0 -; GFX10-NEXT: s_sext_i32_i16 s9, s6 -; GFX10-NEXT: s_ashr_i32 s8, s0, 16 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s9 -; GFX10-NEXT: s_movk_i32 s11, 0x7fff -; GFX10-NEXT: s_cselect_b32 s10, s7, s9 -; GFX10-NEXT: s_cmp_gt_i32 s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s11 -; GFX10-NEXT: s_cselect_b32 s12, s8, s6 -; GFX10-NEXT: s_mov_b32 s14, 0xffff8000 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s10, s12 -; GFX10-NEXT: s_lshr_b32 s12, s11, 16 -; GFX10-NEXT: s_lshr_b32 s13, s10, 16 -; GFX10-NEXT: s_sub_i32 s10, s11, s10 -; GFX10-NEXT: s_sub_i32 s13, s12, s13 -; GFX10-NEXT: s_cmp_lt_i32 s7, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s14, s14, s14 -; GFX10-NEXT: s_cselect_b32 s7, s7, s9 -; GFX10-NEXT: s_cmp_lt_i32 s8, s6 -; GFX10-NEXT: s_sext_i32_i16 s16, s3 -; GFX10-NEXT: s_cselect_b32 s8, s8, s6 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX10-NEXT: s_lshr_b32 s8, s14, 16 -; GFX10-NEXT: s_lshr_b32 s15, s7, 16 -; GFX10-NEXT: s_sub_i32 s7, s14, s7 -; GFX10-NEXT: s_sub_i32 s15, s8, s15 +; GFX10-NEXT: v_pk_add_i16 v0, s0, s3 clamp +; GFX10-NEXT: v_pk_add_i16 v1, s1, s4 clamp +; GFX10-NEXT: v_pk_add_i16 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s15 -; GFX10-NEXT: s_sext_i32_i16 s15, s7 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_cmp_gt_i32 s15, s16 -; GFX10-NEXT: s_cselect_b32 s15, s15, s16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s3 -; GFX10-NEXT: s_sext_i32_i16 s16, s4 -; GFX10-NEXT: s_cselect_b32 s3, s7, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s10, s13 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s15, s3 -; GFX10-NEXT: s_sext_i32_i16 s13, s7 -; GFX10-NEXT: s_sext_i32_i16 s10, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_cmp_lt_i32 s10, s13 -; GFX10-NEXT: s_cselect_b32 s10, s10, s13 -; GFX10-NEXT: s_cmp_lt_i32 s3, s7 -; GFX10-NEXT: s_cselect_b32 s3, s3, s7 -; GFX10-NEXT: s_lshr_b32 s7, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s10, s3 -; GFX10-NEXT: s_lshr_b32 s10, s3, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s3 -; GFX10-NEXT: s_sext_i32_i16 s3, s1 -; GFX10-NEXT: s_add_i32 s7, s7, s10 -; GFX10-NEXT: s_ashr_i32 s10, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s3, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s7 -; GFX10-NEXT: s_cselect_b32 s13, s3, s9 -; GFX10-NEXT: s_cmp_gt_i32 s10, s6 -; GFX10-NEXT: s_cselect_b32 s15, s10, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s13, s13, s15 -; GFX10-NEXT: s_lshr_b32 s15, s13, 16 -; GFX10-NEXT: s_sub_i32 s13, s11, s13 -; GFX10-NEXT: s_sub_i32 s15, s12, s15 -; GFX10-NEXT: s_cmp_lt_i32 s3, s9 -; GFX10-NEXT: s_cselect_b32 s3, s3, s9 -; GFX10-NEXT: s_cmp_lt_i32 s10, s6 -; GFX10-NEXT: s_cselect_b32 s10, s10, s6 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s10 -; GFX10-NEXT: s_lshr_b32 s10, s3, 16 -; GFX10-NEXT: s_sub_i32 s3, s14, s3 -; GFX10-NEXT: s_sub_i32 s10, s8, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s10 -; GFX10-NEXT: s_sext_i32_i16 s10, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_gt_i32 s10, s16 -; GFX10-NEXT: s_cselect_b32 s10, s10, s16 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s13, s15 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s10, s3 -; GFX10-NEXT: s_sext_i32_i16 s13, s4 -; GFX10-NEXT: s_sext_i32_i16 s10, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_i32 s10, s13 -; GFX10-NEXT: s_cselect_b32 s10, s10, s13 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s10, s3 -; GFX10-NEXT: s_lshr_b32 s10, s1, 16 -; GFX10-NEXT: s_lshr_b32 s13, s3, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s3 -; GFX10-NEXT: s_add_i32 s10, s10, s13 -; GFX10-NEXT: s_ashr_i32 s3, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s4, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s10 -; GFX10-NEXT: s_cselect_b32 s13, s4, s9 -; GFX10-NEXT: s_cmp_gt_i32 s3, s6 -; GFX10-NEXT: s_cselect_b32 s15, s3, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s13, s13, s15 -; GFX10-NEXT: s_lshr_b32 s15, s13, 16 -; GFX10-NEXT: s_sub_i32 s11, s11, s13 -; GFX10-NEXT: s_sub_i32 s12, s12, s15 -; GFX10-NEXT: s_cmp_lt_i32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s9 -; GFX10-NEXT: s_cmp_lt_i32 s3, s6 -; GFX10-NEXT: s_cselect_b32 s3, s3, s6 -; GFX10-NEXT: s_sext_i32_i16 s6, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX10-NEXT: s_lshr_b32 s4, s3, 16 -; GFX10-NEXT: s_sub_i32 s3, s14, s3 -; GFX10-NEXT: s_sub_i32 s4, s8, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX10-NEXT: s_ashr_i32 s4, s5, 16 -; GFX10-NEXT: s_sext_i32_i16 s5, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_gt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s11, s12 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3 -; GFX10-NEXT: s_ashr_i32 s5, s6, 16 -; GFX10-NEXT: s_sext_i32_i16 s6, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_i32 s6, s4 -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, s5 -; GFX10-NEXT: s_cselect_b32 s3, s3, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_add_i32 s2, s2, s3 -; GFX10-NEXT: s_add_i32 s4, s4, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x i32> @@ -5444,79 +3555,21 @@ ; GFX9-LABEL: v_saddsat_v8i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, 0, 0 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v9, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v9, s5, v9 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v8, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v8, s4, v8 -; GFX9-NEXT: v_pk_max_i16 v4, v9, v4 -; GFX9-NEXT: v_pk_min_i16 v4, v4, v8 -; GFX9-NEXT: v_pk_min_i16 v8, v1, s6 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v8, s5, v8 -; GFX9-NEXT: v_pk_sub_i16 v4, s4, v4 -; GFX9-NEXT: v_pk_max_i16 v5, v8, v5 -; GFX9-NEXT: v_pk_min_i16 v4, v5, v4 -; GFX9-NEXT: v_pk_min_i16 v5, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v5, s5, v5 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, s4, v4 -; GFX9-NEXT: v_pk_max_i16 v5, v5, v6 -; GFX9-NEXT: v_pk_min_i16 v4, v5, v4 -; GFX9-NEXT: v_pk_min_i16 v5, v3, s6 -; GFX9-NEXT: v_pk_sub_i16 v5, s5, v5 -; GFX9-NEXT: v_pk_add_u16 v2, v2, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v3, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, s4, v4 -; GFX9-NEXT: v_pk_max_i16 v5, v5, v7 -; GFX9-NEXT: v_pk_min_i16 v4, v5, v4 -; GFX9-NEXT: v_pk_add_u16 v3, v3, v4 +; GFX9-NEXT: v_pk_add_i16 v0, v0, v4 clamp +; GFX9-NEXT: v_pk_add_i16 v1, v1, v5 clamp +; GFX9-NEXT: v_pk_add_i16 v2, v2, v6 clamp +; GFX9-NEXT: v_pk_add_i16 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_saddsat_v8i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, 0, 0 -; GFX10-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX10-NEXT: v_pk_min_i16 v8, v0, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX10-NEXT: v_pk_min_i16 v11, v1, s4 -; GFX10-NEXT: v_pk_min_i16 v12, v3, s4 -; GFX10-NEXT: v_pk_max_i16 v9, v0, s4 -; GFX10-NEXT: v_pk_sub_i16 v15, s5, v8 -; GFX10-NEXT: v_pk_min_i16 v8, v2, s4 -; GFX10-NEXT: v_pk_sub_i16 v11, s5, v11 -; GFX10-NEXT: v_pk_sub_i16 v12, s5, v12 -; GFX10-NEXT: v_pk_max_i16 v10, v1, s4 -; GFX10-NEXT: v_pk_max_i16 v13, v2, s4 -; GFX10-NEXT: v_pk_sub_i16 v8, s5, v8 -; GFX10-NEXT: v_pk_max_i16 v14, v3, s4 -; GFX10-NEXT: s_movk_i32 s6, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v4, v15, v4 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v5, v11, v5 -; GFX10-NEXT: v_pk_sub_i16 v9, s6, v9 -; GFX10-NEXT: v_pk_sub_i16 v10, s6, v10 -; GFX10-NEXT: v_pk_max_i16 v6, v8, v6 -; GFX10-NEXT: v_pk_sub_i16 v11, s6, v13 -; GFX10-NEXT: v_pk_sub_i16 v8, s6, v14 -; GFX10-NEXT: v_pk_max_i16 v7, v12, v7 -; GFX10-NEXT: v_pk_min_i16 v15, v4, v9 -; GFX10-NEXT: v_pk_min_i16 v19, v5, v10 -; GFX10-NEXT: v_pk_min_i16 v11, v6, v11 +; GFX10-NEXT: v_pk_add_i16 v0, v0, v4 clamp +; GFX10-NEXT: v_pk_add_i16 v1, v1, v5 clamp +; GFX10-NEXT: v_pk_add_i16 v2, v2, v6 clamp +; GFX10-NEXT: v_pk_add_i16 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_min_i16 v6, v7, v8 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v15 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v19 -; GFX10-NEXT: v_pk_add_u16 v2, v2, v11 -; GFX10-NEXT: v_pk_add_u16 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x float> @@ -5820,373 +3873,31 @@ ; ; GFX9-LABEL: s_saddsat_v8i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s10, 0, 0 -; GFX9-NEXT: s_sext_i32_i16 s13, s10 -; GFX9-NEXT: s_sext_i32_i16 s11, s0 -; GFX9-NEXT: s_ashr_i32 s12, s0, 16 -; GFX9-NEXT: s_ashr_i32 s10, s10, 16 -; GFX9-NEXT: s_cmp_gt_i32 s11, s13 -; GFX9-NEXT: s_cselect_b32 s14, s11, s13 -; GFX9-NEXT: s_cmp_gt_i32 s12, s10 -; GFX9-NEXT: s_movk_i32 s8, 0x7fff -; GFX9-NEXT: s_cselect_b32 s15, s12, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s8 -; GFX9-NEXT: s_lshr_b32 s16, s14, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_sub_i32 s14, s8, s14 -; GFX9-NEXT: s_sub_i32 s16, s15, s16 -; GFX9-NEXT: s_cmp_lt_i32 s11, s13 -; GFX9-NEXT: s_cselect_b32 s11, s11, s13 -; GFX9-NEXT: s_cmp_lt_i32 s12, s10 -; GFX9-NEXT: s_mov_b32 s9, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s12, s12, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s16 -; GFX9-NEXT: s_lshr_b32 s16, s11, 16 -; GFX9-NEXT: s_lshr_b32 s12, s9, 16 -; GFX9-NEXT: s_sub_i32 s11, s9, s11 -; GFX9-NEXT: s_sub_i32 s16, s12, s16 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s16 -; GFX9-NEXT: s_sext_i32_i16 s16, s11 -; GFX9-NEXT: s_sext_i32_i16 s17, s4 -; GFX9-NEXT: s_ashr_i32 s11, s11, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_cmp_gt_i32 s11, s4 -; GFX9-NEXT: s_cselect_b32 s4, s11, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s4 -; GFX9-NEXT: s_sext_i32_i16 s11, s4 -; GFX9-NEXT: s_sext_i32_i16 s16, s14 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s14, s14, 16 -; GFX9-NEXT: s_cmp_lt_i32 s11, s16 -; GFX9-NEXT: s_cselect_b32 s11, s11, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s14 -; GFX9-NEXT: s_cselect_b32 s4, s4, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s11, s4 -; GFX9-NEXT: s_lshr_b32 s11, s0, 16 -; GFX9-NEXT: s_lshr_b32 s14, s4, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s4 -; GFX9-NEXT: s_add_i32 s11, s11, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s11 -; GFX9-NEXT: s_sext_i32_i16 s4, s1 -; GFX9-NEXT: s_ashr_i32 s11, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s14, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s11, s10 -; GFX9-NEXT: s_cselect_b32 s16, s11, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s16 -; GFX9-NEXT: s_lshr_b32 s16, s14, 16 -; GFX9-NEXT: s_sub_i32 s14, s8, s14 -; GFX9-NEXT: s_sub_i32 s16, s15, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s11, s10 -; GFX9-NEXT: s_cselect_b32 s11, s11, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s11 -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_sub_i32 s4, s9, s4 -; GFX9-NEXT: s_sub_i32 s11, s12, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s16 -; GFX9-NEXT: s_sext_i32_i16 s11, s4 -; GFX9-NEXT: s_sext_i32_i16 s16, s5 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_cmp_gt_i32 s11, s16 -; GFX9-NEXT: s_cselect_b32 s11, s11, s16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s11, s4 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s11, s14 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s14, s14, 16 -; GFX9-NEXT: s_cmp_lt_i32 s5, s11 -; GFX9-NEXT: s_cselect_b32 s5, s5, s11 -; GFX9-NEXT: s_cmp_lt_i32 s4, s14 -; GFX9-NEXT: s_cselect_b32 s4, s4, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_lshr_b32 s5, s1, 16 -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX9-NEXT: s_sext_i32_i16 s4, s2 -; GFX9-NEXT: s_ashr_i32 s5, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s11, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s14, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s14 -; GFX9-NEXT: s_lshr_b32 s14, s11, 16 -; GFX9-NEXT: s_sub_i32 s11, s8, s11 -; GFX9-NEXT: s_sub_i32 s14, s15, s14 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s5, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_sub_i32 s4, s9, s4 -; GFX9-NEXT: s_sub_i32 s5, s12, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s14 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s14, s6 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s14 -; GFX9-NEXT: s_cselect_b32 s5, s5, s14 -; GFX9-NEXT: s_cmp_gt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s6, s11 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s11, s11, 16 -; GFX9-NEXT: s_cmp_lt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_lt_i32 s4, s11 -; GFX9-NEXT: s_cselect_b32 s4, s4, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_add_i32 s2, s2, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_ashr_i32 s5, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s6, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s11, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s11 -; GFX9-NEXT: s_lshr_b32 s11, s6, 16 -; GFX9-NEXT: s_sub_i32 s6, s8, s6 -; GFX9-NEXT: s_sub_i32 s8, s15, s11 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s5, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_sub_i32 s4, s9, s4 -; GFX9-NEXT: s_sub_i32 s5, s12, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s8, s7 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s7, s7, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s8 -; GFX9-NEXT: s_cselect_b32 s5, s5, s8 -; GFX9-NEXT: s_cmp_gt_i32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s7, s6 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_lt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_add_i32 s3, s3, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_add_i16 v2, s2, v2 clamp +; GFX9-NEXT: v_pk_add_i16 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_saddsat_v8i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s8, 0, 0 -; GFX10-NEXT: s_sext_i32_i16 s9, s0 -; GFX10-NEXT: s_sext_i32_i16 s11, s8 -; GFX10-NEXT: s_ashr_i32 s10, s0, 16 -; GFX10-NEXT: s_ashr_i32 s8, s8, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s11 -; GFX10-NEXT: s_movk_i32 s13, 0x7fff -; GFX10-NEXT: s_cselect_b32 s12, s9, s11 -; GFX10-NEXT: s_cmp_gt_i32 s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s13, s13, s13 -; GFX10-NEXT: s_cselect_b32 s14, s10, s8 -; GFX10-NEXT: s_mov_b32 s16, 0xffff8000 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX10-NEXT: s_lshr_b32 s14, s13, 16 -; GFX10-NEXT: s_lshr_b32 s15, s12, 16 -; GFX10-NEXT: s_sub_i32 s12, s13, s12 -; GFX10-NEXT: s_sub_i32 s15, s14, s15 -; GFX10-NEXT: s_cmp_lt_i32 s9, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s16, s16, s16 -; GFX10-NEXT: s_cselect_b32 s9, s9, s11 -; GFX10-NEXT: s_cmp_lt_i32 s10, s8 -; GFX10-NEXT: s_sext_i32_i16 s18, s4 -; GFX10-NEXT: s_cselect_b32 s10, s10, s8 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX10-NEXT: s_lshr_b32 s10, s16, 16 -; GFX10-NEXT: s_lshr_b32 s17, s9, 16 -; GFX10-NEXT: s_sub_i32 s9, s16, s9 -; GFX10-NEXT: s_sub_i32 s17, s10, s17 +; GFX10-NEXT: v_pk_add_i16 v0, s0, s4 clamp +; GFX10-NEXT: v_pk_add_i16 v1, s1, s5 clamp +; GFX10-NEXT: v_pk_add_i16 v2, s2, s6 clamp +; GFX10-NEXT: v_pk_add_i16 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s17 -; GFX10-NEXT: s_sext_i32_i16 s17, s9 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_cmp_gt_i32 s17, s18 -; GFX10-NEXT: s_cselect_b32 s17, s17, s18 -; GFX10-NEXT: s_cmp_gt_i32 s9, s4 -; GFX10-NEXT: s_sext_i32_i16 s18, s5 -; GFX10-NEXT: s_cselect_b32 s4, s9, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s12, s15 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s17, s4 -; GFX10-NEXT: s_sext_i32_i16 s15, s9 -; GFX10-NEXT: s_sext_i32_i16 s12, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_cmp_lt_i32 s12, s15 -; GFX10-NEXT: s_cselect_b32 s12, s12, s15 -; GFX10-NEXT: s_cmp_lt_i32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s9 -; GFX10-NEXT: s_lshr_b32 s9, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX10-NEXT: s_lshr_b32 s12, s4, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s1 -; GFX10-NEXT: s_add_i32 s9, s9, s12 -; GFX10-NEXT: s_ashr_i32 s12, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s4, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s9 -; GFX10-NEXT: s_cselect_b32 s15, s4, s11 -; GFX10-NEXT: s_cmp_gt_i32 s12, s8 -; GFX10-NEXT: s_cselect_b32 s17, s12, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s15, s15, s17 -; GFX10-NEXT: s_lshr_b32 s17, s15, 16 -; GFX10-NEXT: s_sub_i32 s15, s13, s15 -; GFX10-NEXT: s_sub_i32 s17, s14, s17 -; GFX10-NEXT: s_cmp_lt_i32 s4, s11 -; GFX10-NEXT: s_cselect_b32 s4, s4, s11 -; GFX10-NEXT: s_cmp_lt_i32 s12, s8 -; GFX10-NEXT: s_cselect_b32 s12, s12, s8 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12 -; GFX10-NEXT: s_lshr_b32 s12, s4, 16 -; GFX10-NEXT: s_sub_i32 s4, s16, s4 -; GFX10-NEXT: s_sub_i32 s12, s10, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12 -; GFX10-NEXT: s_sext_i32_i16 s12, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_gt_i32 s12, s18 -; GFX10-NEXT: s_cselect_b32 s12, s12, s18 -; GFX10-NEXT: s_cmp_gt_i32 s4, s5 -; GFX10-NEXT: s_sext_i32_i16 s18, s6 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s15, s17 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX10-NEXT: s_sext_i32_i16 s15, s5 -; GFX10-NEXT: s_sext_i32_i16 s12, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_i32 s12, s15 -; GFX10-NEXT: s_cselect_b32 s12, s12, s15 -; GFX10-NEXT: s_cmp_lt_i32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_lshr_b32 s5, s1, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX10-NEXT: s_lshr_b32 s12, s4, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s2 -; GFX10-NEXT: s_add_i32 s5, s5, s12 -; GFX10-NEXT: s_ashr_i32 s12, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s4, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX10-NEXT: s_cselect_b32 s15, s4, s11 -; GFX10-NEXT: s_cmp_gt_i32 s12, s8 -; GFX10-NEXT: s_cselect_b32 s17, s12, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s15, s15, s17 -; GFX10-NEXT: s_lshr_b32 s17, s15, 16 -; GFX10-NEXT: s_sub_i32 s15, s13, s15 -; GFX10-NEXT: s_sub_i32 s17, s14, s17 -; GFX10-NEXT: s_cmp_lt_i32 s4, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s15, s15, s17 -; GFX10-NEXT: s_cselect_b32 s4, s4, s11 -; GFX10-NEXT: s_cmp_lt_i32 s12, s8 -; GFX10-NEXT: s_cselect_b32 s12, s12, s8 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12 -; GFX10-NEXT: s_lshr_b32 s12, s4, 16 -; GFX10-NEXT: s_sub_i32 s4, s16, s4 -; GFX10-NEXT: s_sub_i32 s12, s10, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12 -; GFX10-NEXT: s_sext_i32_i16 s12, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_gt_i32 s12, s18 -; GFX10-NEXT: s_cselect_b32 s12, s12, s18 -; GFX10-NEXT: s_cmp_gt_i32 s4, s6 -; GFX10-NEXT: s_cselect_b32 s4, s4, s6 -; GFX10-NEXT: s_sext_i32_i16 s6, s15 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX10-NEXT: s_ashr_i32 s12, s15, 16 -; GFX10-NEXT: s_sext_i32_i16 s15, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_i32 s15, s6 -; GFX10-NEXT: s_cselect_b32 s6, s15, s6 -; GFX10-NEXT: s_cmp_lt_i32 s4, s12 -; GFX10-NEXT: s_sext_i32_i16 s15, s3 -; GFX10-NEXT: s_cselect_b32 s4, s4, s12 -; GFX10-NEXT: s_lshr_b32 s12, s2, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s6, s4 -; GFX10-NEXT: s_ashr_i32 s6, s3, 16 -; GFX10-NEXT: s_lshr_b32 s17, s4, 16 -; GFX10-NEXT: s_add_i32 s2, s2, s4 -; GFX10-NEXT: s_add_i32 s12, s12, s17 -; GFX10-NEXT: s_cmp_gt_i32 s15, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s12 -; GFX10-NEXT: s_cselect_b32 s4, s15, s11 -; GFX10-NEXT: s_cmp_gt_i32 s6, s8 -; GFX10-NEXT: s_cselect_b32 s17, s6, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s17 -; GFX10-NEXT: s_lshr_b32 s17, s4, 16 -; GFX10-NEXT: s_sub_i32 s4, s13, s4 -; GFX10-NEXT: s_sub_i32 s13, s14, s17 -; GFX10-NEXT: s_cmp_lt_i32 s15, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s13 -; GFX10-NEXT: s_cselect_b32 s11, s15, s11 -; GFX10-NEXT: s_cmp_lt_i32 s6, s8 -; GFX10-NEXT: s_cselect_b32 s6, s6, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s11, s6 -; GFX10-NEXT: s_lshr_b32 s8, s6, 16 -; GFX10-NEXT: s_sub_i32 s6, s16, s6 -; GFX10-NEXT: s_sub_i32 s8, s10, s8 -; GFX10-NEXT: s_sext_i32_i16 s10, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_sext_i32_i16 s8, s6 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_gt_i32 s8, s10 -; GFX10-NEXT: s_cselect_b32 s8, s8, s10 -; GFX10-NEXT: s_cmp_gt_i32 s6, s7 -; GFX10-NEXT: s_cselect_b32 s6, s6, s7 -; GFX10-NEXT: s_sext_i32_i16 s7, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s8, s6 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_sext_i32_i16 s8, s6 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_lt_i32 s8, s7 -; GFX10-NEXT: s_cselect_b32 s7, s8, s7 -; GFX10-NEXT: s_cmp_lt_i32 s6, s4 -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s7, s4 -; GFX10-NEXT: s_lshr_b32 s6, s4, 16 -; GFX10-NEXT: s_add_i32 s3, s3, s4 -; GFX10-NEXT: s_add_i32 s5, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x i32> Index: llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll @@ -40,15 +40,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0 -; GFX9-NEXT: s_mov_b32 s4, 0xffff -; GFX9-NEXT: v_max_i16_e32 v2, s4, v0 -; GFX9-NEXT: v_min_i16_e32 v3, s4, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_max_i16_e32 v1, v2, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v3 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -57,16 +50,9 @@ ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0 -; GFX10-NEXT: s_mov_b32 s4, 0xffff ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_max_i16_e64 v2, v0, s4 -; GFX10-NEXT: v_min_i16_e64 v3, v0, s4 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff -; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs) @@ -121,54 +107,23 @@ ; GFX9-LABEL: s_ssubsat_i7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_sext_i32_i16 s3, s0 -; GFX9-NEXT: s_sext_i32_i16 s4, 0xffff -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s5, s3, s4 -; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s3, s3, 0x8000 -; GFX9-NEXT: s_sext_i32_i16 s4, s5 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s4, s1 -; GFX9-NEXT: s_cselect_b32 s1, s4, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s3, s3 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_sext_i32_i16 s0, s0 -; GFX9-NEXT: s_ashr_i32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_i7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX10-NEXT: s_sext_i32_i16 s4, 0xffff +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s3, s4 -; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s5 -; GFX10-NEXT: s_sub_i32 s3, s3, 0x8000 -; GFX10-NEXT: s_cmp_gt_i32 s4, s1 -; GFX10-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-NEXT: s_cselect_b32 s1, s4, s1 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_sext_i32_i16 s0, s0 -; GFX10-NEXT: s_ashr_i32 s0, s0, s2 +; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs) ret i7 %result @@ -210,15 +165,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 -; GFX9-NEXT: s_mov_b32 s4, 0xffff -; GFX9-NEXT: v_max_i16_e32 v2, s4, v0 -; GFX9-NEXT: v_min_i16_e32 v3, s4, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_max_i16_e32 v1, v2, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v3 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -227,16 +175,9 @@ ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 -; GFX10-NEXT: s_mov_b32 s4, 0xffff ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_max_i16_e64 v2, v0, s4 -; GFX10-NEXT: v_min_i16_e64 v3, v0, s4 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff -; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) @@ -291,54 +232,23 @@ ; GFX9-LABEL: s_ssubsat_i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_sext_i32_i16 s3, s0 -; GFX9-NEXT: s_sext_i32_i16 s4, 0xffff -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s5, s3, s4 -; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s3, s3, 0x8000 -; GFX9-NEXT: s_sext_i32_i16 s4, s5 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s4, s1 -; GFX9-NEXT: s_cselect_b32 s1, s4, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s3, s3 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_sext_i32_i16 s0, s0 -; GFX9-NEXT: s_ashr_i32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_i8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX10-NEXT: s_sext_i32_i16 s4, 0xffff +; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s3, s4 -; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sext_i32_i16 s4, s5 -; GFX10-NEXT: s_sub_i32 s3, s3, 0x8000 -; GFX10-NEXT: s_cmp_gt_i32 s4, s1 -; GFX10-NEXT: s_sext_i32_i16 s3, s3 -; GFX10-NEXT: s_cselect_b32 s1, s4, s1 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_sext_i32_i16 s0, s0 -; GFX10-NEXT: s_ashr_i32 s0, s0, s2 +; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs) ret i8 %result @@ -380,14 +290,8 @@ ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0 -; GFX9-NEXT: v_max_i32_e32 v2, -1, v0 -; GFX9-NEXT: v_min_i32_e32 v3, -1, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_subrev_u32_e32 v2, 0x7fffffff, v2 -; GFX9-NEXT: v_subrev_u32_e32 v3, 0x80000000, v3 -; GFX9-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX9-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -398,13 +302,7 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_max_i32_e32 v2, -1, v0 -; GFX10-NEXT: v_min_i32_e32 v3, -1, v0 -; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x7fffffff, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 0x80000000, v3 -; GFX10-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs) @@ -451,39 +349,22 @@ ; ; GFX9-LABEL: s_ssubsat_i24: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshl_b32 s0, s0, 8 ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s2, s0, -1 -; GFX9-NEXT: s_sub_i32 s2, s2, 0x7fffffff -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s3, s0, -1 -; GFX9-NEXT: s_sub_i32 s3, s3, 0x80000000 -; GFX9-NEXT: s_cmp_gt_i32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_ashr_i32 s0, s0, 8 +; GFX9-NEXT: s_lshl_b32 s0, s0, 8 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_i24: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_lshl_b32 s0, s0, 8 ; GFX10-NEXT: s_lshl_b32 s1, s1, 8 -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s0, -1 -; GFX10-NEXT: s_sub_i32 s2, s2, 0x7fffffff -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 -; GFX10-NEXT: s_cselect_b32 s3, s0, -1 -; GFX10-NEXT: s_sub_i32 s3, s3, 0x80000000 -; GFX10-NEXT: s_cmp_gt_i32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_ashr_i32 s0, s0, 8 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp +; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs) ret i24 %result @@ -517,27 +398,15 @@ ; GFX9-LABEL: v_ssubsat_i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_max_i32_e32 v2, -1, v0 -; GFX9-NEXT: v_min_i32_e32 v3, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v2, 0x7fffffff, v2 -; GFX9-NEXT: v_subrev_u32_e32 v3, 0x80000000, v3 -; GFX9-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX9-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v2, -1, v0 -; GFX10-NEXT: v_min_i32_e32 v3, -1, v0 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x7fffffff, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 0x80000000, v3 -; GFX10-NEXT: v_max_i32_e32 v1, v2, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -576,33 +445,16 @@ ; ; GFX9-LABEL: s_ssubsat_i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s2, s0, -1 -; GFX9-NEXT: s_sub_i32 s2, s2, 0x7fffffff -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s3, s0, -1 -; GFX9-NEXT: s_sub_i32 s3, s3, 0x80000000 -; GFX9-NEXT: s_cmp_gt_i32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s0, -1 -; GFX10-NEXT: s_sub_i32 s2, s2, 0x7fffffff -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 -; GFX10-NEXT: s_cselect_b32 s3, s0, -1 -; GFX10-NEXT: s_sub_i32 s3, s3, 0x80000000 -; GFX10-NEXT: s_cmp_gt_i32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -637,29 +489,13 @@ ; ; GFX9-LABEL: ssubsat_i32_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s1, s0, -1 -; GFX9-NEXT: s_sub_i32 s1, s1, 0x7fffffff -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_cselect_b32 s2, s0, -1 -; GFX9-NEXT: s_sub_i32 s2, s2, 0x80000000 -; GFX9-NEXT: v_max_i32_e32 v0, s1, v0 -; GFX9-NEXT: v_min_i32_e32 v0, s2, v0 -; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_i32_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s1, s0, -1 -; GFX10-NEXT: s_sub_i32 s1, s1, 0x7fffffff -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 -; GFX10-NEXT: v_max_i32_e32 v0, s1, v0 -; GFX10-NEXT: s_cselect_b32 s1, s0, -1 -; GFX10-NEXT: s_sub_i32 s1, s1, 0x80000000 -; GFX10-NEXT: v_min_i32_e32 v0, s1, v0 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -691,25 +527,13 @@ ; ; GFX9-LABEL: ssubsat_i32_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_max_i32_e32 v1, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v1, 0x7fffffff, v1 -; GFX9-NEXT: v_min_i32_e32 v2, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v2, 0x80000000, v2 -; GFX9-NEXT: v_max_i32_e32 v1, s0, v1 -; GFX9-NEXT: v_min_i32_e32 v1, v1, v2 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i32 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_i32_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_max_i32_e32 v1, -1, v0 -; GFX10-NEXT: v_min_i32_e32 v2, -1, v0 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 0x7fffffff, v1 -; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x80000000, v2 -; GFX10-NEXT: v_max_i32_e32 v1, s0, v1 -; GFX10-NEXT: v_min_i32_e32 v1, v1, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -762,45 +586,17 @@ ; GFX9-LABEL: v_ssubsat_v2i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v4, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v5, -1, v0 -; GFX9-NEXT: v_max_i32_e32 v2, v4, v2 -; GFX9-NEXT: v_subrev_u32_e32 v5, s5, v5 -; GFX9-NEXT: v_min_i32_e32 v2, v2, v5 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2 -; GFX9-NEXT: v_max_i32_e32 v2, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2 -; GFX9-NEXT: v_min_i32_e32 v4, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v4 -; GFX9-NEXT: v_max_i32_e32 v2, v2, v3 -; GFX9-NEXT: v_min_i32_e32 v2, v2, v4 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v2i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v4, -1, v0 -; GFX10-NEXT: v_max_i32_e32 v5, -1, v1 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_min_i32_e32 v6, -1, v0 -; GFX10-NEXT: v_min_i32_e32 v7, -1, v1 -; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s4, v4 -; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s4, v5 -; GFX10-NEXT: s_mov_b32 s4, 0x80000000 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s4, v6 -; GFX10-NEXT: v_max_i32_e32 v11, v4, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s4, v7 -; GFX10-NEXT: v_max_i32_e32 v10, v5, v3 -; GFX10-NEXT: v_min_i32_e32 v2, v11, v6 -; GFX10-NEXT: v_min_i32_e32 v3, v10, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -865,59 +661,21 @@ ; ; GFX9-LABEL: s_ssubsat_v2i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: s_cselect_b32 s6, s0, -1 -; GFX9-NEXT: s_sub_i32 s6, s6, s4 -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s7, s0, -1 -; GFX9-NEXT: s_sub_i32 s7, s7, s5 -; GFX9-NEXT: s_cmp_gt_i32 s6, s2 -; GFX9-NEXT: s_cselect_b32 s2, s6, s2 -; GFX9-NEXT: s_cmp_lt_i32 s2, s7 -; GFX9-NEXT: s_cselect_b32 s2, s2, s7 -; GFX9-NEXT: s_sub_i32 s0, s0, s2 -; GFX9-NEXT: s_cmp_gt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s2, s1, -1 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_cmp_lt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s4, s1, -1 -; GFX9-NEXT: s_sub_i32 s4, s4, s5 -; GFX9-NEXT: s_cmp_gt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_cmp_lt_i32 s2, s4 -; GFX9-NEXT: s_cselect_b32 s2, s2, s4 -; GFX9-NEXT: s_sub_i32 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v2i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: s_cselect_b32 s5, s0, -1 -; GFX10-NEXT: s_mov_b32 s6, 0x80000000 -; GFX10-NEXT: s_sub_i32 s5, s5, s4 -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s2 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s7, s0, -1 -; GFX10-NEXT: s_sub_i32 s7, s7, s6 -; GFX10-NEXT: s_cmp_gt_i32 s5, s2 -; GFX10-NEXT: s_cselect_b32 s2, s5, s2 -; GFX10-NEXT: s_cmp_lt_i32 s2, s7 -; GFX10-NEXT: s_cselect_b32 s2, s2, s7 -; GFX10-NEXT: s_sub_i32 s0, s0, s2 -; GFX10-NEXT: s_cmp_gt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s2, s1, -1 -; GFX10-NEXT: s_sub_i32 s2, s2, s4 -; GFX10-NEXT: s_cmp_lt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s4, s1, -1 -; GFX10-NEXT: s_sub_i32 s4, s4, s6 -; GFX10-NEXT: s_cmp_gt_i32 s2, s3 -; GFX10-NEXT: s_cselect_b32 s2, s2, s3 -; GFX10-NEXT: s_cmp_lt_i32 s2, s4 -; GFX10-NEXT: s_cselect_b32 s2, s2, s4 -; GFX10-NEXT: s_sub_i32 s1, s1, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -983,59 +741,19 @@ ; GFX9-LABEL: v_ssubsat_v3i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v6, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v6, s4, v6 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v7, -1, v0 -; GFX9-NEXT: v_max_i32_e32 v3, v6, v3 -; GFX9-NEXT: v_subrev_u32_e32 v7, s5, v7 -; GFX9-NEXT: v_min_i32_e32 v3, v3, v7 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 -; GFX9-NEXT: v_max_i32_e32 v3, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3 -; GFX9-NEXT: v_min_i32_e32 v6, -1, v1 -; GFX9-NEXT: v_max_i32_e32 v3, v3, v4 -; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v6 -; GFX9-NEXT: v_min_i32_e32 v3, v3, v6 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_max_i32_e32 v3, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3 -; GFX9-NEXT: v_min_i32_e32 v4, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v4 -; GFX9-NEXT: v_max_i32_e32 v3, v3, v5 -; GFX9-NEXT: v_min_i32_e32 v3, v3, v4 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v3i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v6, -1, v0 -; GFX10-NEXT: v_max_i32_e32 v8, -1, v1 -; GFX10-NEXT: v_max_i32_e32 v9, -1, v2 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_min_i32_e32 v7, -1, v0 -; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s4, v6 -; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s4, v8 -; GFX10-NEXT: v_subrev_nc_u32_e32 v19, s4, v9 -; GFX10-NEXT: v_min_i32_e32 v10, -1, v1 -; GFX10-NEXT: v_min_i32_e32 v11, -1, v2 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v14, v6, v3 -; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s5, v7 -; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s5, v10 -; GFX10-NEXT: v_max_i32_e32 v4, v15, v4 -; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s5, v11 -; GFX10-NEXT: v_max_i32_e32 v5, v19, v5 -; GFX10-NEXT: v_min_i32_e32 v3, v14, v7 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i32_e32 v4, v4, v6 -; GFX10-NEXT: v_min_i32_e32 v5, v5, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -1122,81 +840,26 @@ ; ; GFX9-LABEL: s_ssubsat_v3i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_brev_b32 s6, -2 -; GFX9-NEXT: s_cselect_b32 s8, s0, -1 -; GFX9-NEXT: s_sub_i32 s8, s8, s6 -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_mov_b32 s7, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s9, s0, -1 -; GFX9-NEXT: s_sub_i32 s9, s9, s7 -; GFX9-NEXT: s_cmp_gt_i32 s8, s3 -; GFX9-NEXT: s_cselect_b32 s3, s8, s3 -; GFX9-NEXT: s_cmp_lt_i32 s3, s9 -; GFX9-NEXT: s_cselect_b32 s3, s3, s9 -; GFX9-NEXT: s_sub_i32 s0, s0, s3 -; GFX9-NEXT: s_cmp_gt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s3, s1, -1 -; GFX9-NEXT: s_sub_i32 s3, s3, s6 -; GFX9-NEXT: s_cmp_lt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s8, s1, -1 -; GFX9-NEXT: s_sub_i32 s8, s8, s7 -; GFX9-NEXT: s_cmp_gt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_cmp_lt_i32 s3, s8 -; GFX9-NEXT: s_cselect_b32 s3, s3, s8 -; GFX9-NEXT: s_sub_i32 s1, s1, s3 -; GFX9-NEXT: s_cmp_gt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s3, s2, -1 -; GFX9-NEXT: s_sub_i32 s3, s3, s6 -; GFX9-NEXT: s_cmp_lt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s4, s2, -1 -; GFX9-NEXT: s_sub_i32 s4, s4, s7 -; GFX9-NEXT: s_cmp_gt_i32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s3, s3, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v3i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 -; GFX10-NEXT: s_brev_b32 s6, -2 -; GFX10-NEXT: s_cselect_b32 s7, s0, -1 -; GFX10-NEXT: s_mov_b32 s8, 0x80000000 -; GFX10-NEXT: s_sub_i32 s7, s7, s6 -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s3 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, s1, s4 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s9, s0, -1 -; GFX10-NEXT: s_sub_i32 s9, s9, s8 -; GFX10-NEXT: s_cmp_gt_i32 s7, s3 -; GFX10-NEXT: s_cselect_b32 s3, s7, s3 -; GFX10-NEXT: s_cmp_lt_i32 s3, s9 -; GFX10-NEXT: s_cselect_b32 s3, s3, s9 -; GFX10-NEXT: s_sub_i32 s0, s0, s3 -; GFX10-NEXT: s_cmp_gt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s3, s1, -1 -; GFX10-NEXT: s_sub_i32 s3, s3, s6 -; GFX10-NEXT: s_cmp_lt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s7, s1, -1 -; GFX10-NEXT: s_sub_i32 s7, s7, s8 -; GFX10-NEXT: s_cmp_gt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, s7 -; GFX10-NEXT: s_cselect_b32 s3, s3, s7 -; GFX10-NEXT: s_sub_i32 s1, s1, s3 -; GFX10-NEXT: s_cmp_gt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s3, s2, -1 -; GFX10-NEXT: s_sub_i32 s3, s3, s6 -; GFX10-NEXT: s_cmp_lt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s4, s2, -1 -; GFX10-NEXT: s_sub_i32 s4, s4, s8 -; GFX10-NEXT: s_cmp_gt_i32 s3, s5 -; GFX10-NEXT: s_cselect_b32 s3, s3, s5 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_sub_i32 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -1276,73 +939,21 @@ ; GFX9-LABEL: v_ssubsat_v4i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v8, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v8, s4, v8 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v9, -1, v0 -; GFX9-NEXT: v_max_i32_e32 v4, v8, v4 -; GFX9-NEXT: v_subrev_u32_e32 v9, s5, v9 -; GFX9-NEXT: v_min_i32_e32 v4, v4, v9 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4 -; GFX9-NEXT: v_max_i32_e32 v4, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4 -; GFX9-NEXT: v_min_i32_e32 v8, -1, v1 -; GFX9-NEXT: v_max_i32_e32 v4, v4, v5 -; GFX9-NEXT: v_subrev_u32_e32 v8, s5, v8 -; GFX9-NEXT: v_min_i32_e32 v4, v4, v8 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v4 -; GFX9-NEXT: v_max_i32_e32 v4, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4 -; GFX9-NEXT: v_min_i32_e32 v5, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v5, s5, v5 -; GFX9-NEXT: v_max_i32_e32 v4, v4, v6 -; GFX9-NEXT: v_min_i32_e32 v4, v4, v5 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_max_i32_e32 v4, -1, v3 -; GFX9-NEXT: v_subrev_u32_e32 v4, 0x7fffffff, v4 -; GFX9-NEXT: v_min_i32_e32 v5, -1, v3 -; GFX9-NEXT: v_subrev_u32_e32 v5, 0x80000000, v5 -; GFX9-NEXT: v_max_i32_e32 v4, v4, v7 -; GFX9-NEXT: v_min_i32_e32 v4, v4, v5 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v4 +; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v4i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v8, -1, v0 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_max_i32_e32 v10, -1, v1 -; GFX10-NEXT: v_max_i32_e32 v12, -1, v3 -; GFX10-NEXT: v_min_i32_e32 v9, -1, v0 -; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s4, v8 -; GFX10-NEXT: v_max_i32_e32 v8, -1, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10 -; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 0x7fffffff, v12 -; GFX10-NEXT: v_min_i32_e32 v11, -1, v1 -; GFX10-NEXT: v_min_i32_e32 v13, -1, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s4, v8 -; GFX10-NEXT: v_min_i32_e32 v14, -1, v3 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v4, v15, v4 -; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s5, v9 -; GFX10-NEXT: v_max_i32_e32 v5, v10, v5 -; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s5, v11 -; GFX10-NEXT: v_max_i32_e32 v15, v8, v6 -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s5, v13 -; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 0x80000000, v14 -; GFX10-NEXT: v_max_i32_e32 v7, v12, v7 -; GFX10-NEXT: v_min_i32_e32 v19, v4, v9 -; GFX10-NEXT: v_min_i32_e32 v11, v5, v11 -; GFX10-NEXT: v_min_i32_e32 v15, v15, v10 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_i32_e32 v6, v7, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v19 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v15 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -1451,103 +1062,31 @@ ; ; GFX9-LABEL: s_ssubsat_v4i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_brev_b32 s8, -2 -; GFX9-NEXT: s_cselect_b32 s10, s0, -1 -; GFX9-NEXT: s_sub_i32 s10, s10, s8 -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_mov_b32 s9, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s11, s0, -1 -; GFX9-NEXT: s_sub_i32 s11, s11, s9 -; GFX9-NEXT: s_cmp_gt_i32 s10, s4 -; GFX9-NEXT: s_cselect_b32 s4, s10, s4 -; GFX9-NEXT: s_cmp_lt_i32 s4, s11 -; GFX9-NEXT: s_cselect_b32 s4, s4, s11 -; GFX9-NEXT: s_sub_i32 s0, s0, s4 -; GFX9-NEXT: s_cmp_gt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s4, s1, -1 -; GFX9-NEXT: s_sub_i32 s4, s4, s8 -; GFX9-NEXT: s_cmp_lt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s10, s1, -1 -; GFX9-NEXT: s_sub_i32 s10, s10, s9 -; GFX9-NEXT: s_cmp_gt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_i32 s4, s10 -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 -; GFX9-NEXT: s_sub_i32 s1, s1, s4 -; GFX9-NEXT: s_cmp_gt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s4, s2, -1 -; GFX9-NEXT: s_sub_i32 s4, s4, s8 -; GFX9-NEXT: s_cmp_lt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s5, s2, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s9 -; GFX9-NEXT: s_cmp_gt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_cmp_lt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_cmp_gt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s4, s3, -1 -; GFX9-NEXT: s_sub_i32 s4, s4, s8 -; GFX9-NEXT: s_cmp_lt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s5, s3, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s9 -; GFX9-NEXT: s_cmp_gt_i32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_cmp_lt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_sub_i32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v4i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 -; GFX10-NEXT: s_brev_b32 s8, -2 -; GFX10-NEXT: s_cselect_b32 s9, s0, -1 -; GFX10-NEXT: s_mov_b32 s10, 0x80000000 -; GFX10-NEXT: s_sub_i32 s9, s9, s8 -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s4 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, s1, s5 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, s2, s6 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s11, s0, -1 -; GFX10-NEXT: s_sub_i32 s11, s11, s10 -; GFX10-NEXT: s_cmp_gt_i32 s9, s4 -; GFX10-NEXT: s_cselect_b32 s4, s9, s4 -; GFX10-NEXT: s_cmp_lt_i32 s4, s11 -; GFX10-NEXT: s_cselect_b32 s4, s4, s11 -; GFX10-NEXT: s_sub_i32 s0, s0, s4 -; GFX10-NEXT: s_cmp_gt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s4, s1, -1 -; GFX10-NEXT: s_sub_i32 s4, s4, s8 -; GFX10-NEXT: s_cmp_lt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s9, s1, -1 -; GFX10-NEXT: s_sub_i32 s9, s9, s10 -; GFX10-NEXT: s_cmp_gt_i32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_cmp_lt_i32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s9 -; GFX10-NEXT: s_sub_i32 s1, s1, s4 -; GFX10-NEXT: s_cmp_gt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s4, s2, -1 -; GFX10-NEXT: s_sub_i32 s4, s4, s8 -; GFX10-NEXT: s_cmp_lt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s5, s2, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_gt_i32 s4, s6 -; GFX10-NEXT: s_cselect_b32 s4, s4, s6 -; GFX10-NEXT: s_cmp_lt_i32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_sub_i32 s2, s2, s4 -; GFX10-NEXT: s_cmp_gt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s4, s3, -1 -; GFX10-NEXT: s_sub_i32 s4, s4, s8 -; GFX10-NEXT: s_cmp_lt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s5, s3, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_gt_i32 s4, s7 -; GFX10-NEXT: s_cselect_b32 s4, s4, s7 -; GFX10-NEXT: s_cmp_lt_i32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s5 -; GFX10-NEXT: s_sub_i32 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -1645,90 +1184,22 @@ ; GFX9-LABEL: v_ssubsat_v5i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v10, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v10, s4, v10 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v12, -1, v0 -; GFX9-NEXT: v_max_i32_e32 v5, v10, v5 -; GFX9-NEXT: v_subrev_u32_e32 v12, s5, v12 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v12 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v5 -; GFX9-NEXT: v_max_i32_e32 v5, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v5 -; GFX9-NEXT: v_min_i32_e32 v10, -1, v1 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v6 -; GFX9-NEXT: v_subrev_u32_e32 v10, s5, v10 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v10 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5 -; GFX9-NEXT: v_max_i32_e32 v5, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v5 -; GFX9-NEXT: v_min_i32_e32 v6, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v6 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v7 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v6 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_bfrev_b32_e32 v11, -2 -; GFX9-NEXT: v_max_i32_e32 v5, -1, v3 -; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11 -; GFX9-NEXT: v_mov_b32_e32 v13, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v6, -1, v3 -; GFX9-NEXT: v_sub_u32_e32 v6, v6, v13 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v8 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v6 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_max_i32_e32 v5, -1, v4 -; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11 -; GFX9-NEXT: v_min_i32_e32 v6, -1, v4 -; GFX9-NEXT: v_sub_u32_e32 v6, v6, v13 -; GFX9-NEXT: v_max_i32_e32 v5, v5, v9 -; GFX9-NEXT: v_min_i32_e32 v5, v5, v6 -; GFX9-NEXT: v_sub_u32_e32 v4, v4, v5 +; GFX9-NEXT: v_sub_i32 v0, v0, v5 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v6 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v7 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v8 clamp +; GFX9-NEXT: v_sub_i32 v4, v4, v9 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v5i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v10, -1, v0 -; GFX10-NEXT: v_max_i32_e32 v13, -1, v1 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_bfrev_b32_e32 v11, -2 -; GFX10-NEXT: v_max_i32_e32 v17, -1, v4 -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10 -; GFX10-NEXT: v_subrev_nc_u32_e32 v13, s4, v13 -; GFX10-NEXT: v_min_i32_e32 v12, -1, v0 -; GFX10-NEXT: v_mov_b32_e32 v14, 0x80000000 -; GFX10-NEXT: v_min_i32_e32 v15, -1, v1 -; GFX10-NEXT: v_max_i32_e32 v5, v10, v5 -; GFX10-NEXT: v_max_i32_e32 v10, -1, v2 -; GFX10-NEXT: v_max_i32_e32 v6, v13, v6 -; GFX10-NEXT: v_max_i32_e32 v13, -1, v3 -; GFX10-NEXT: v_min_i32_e32 v16, -1, v2 -; GFX10-NEXT: v_min_i32_e32 v23, -1, v3 -; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10 -; GFX10-NEXT: v_min_i32_e32 v19, -1, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, v17, v11 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v7, v10, v7 -; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s5, v12 -; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s5, v15 -; GFX10-NEXT: v_subrev_nc_u32_e32 v16, s5, v16 -; GFX10-NEXT: v_max_i32_e32 v8, v13, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, v23, v14 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, v19, v14 -; GFX10-NEXT: v_max_i32_e32 v11, v11, v9 -; GFX10-NEXT: v_min_i32_e32 v5, v5, v12 -; GFX10-NEXT: v_min_i32_e32 v6, v6, v15 -; GFX10-NEXT: v_min_i32_e32 v7, v7, v16 -; GFX10-NEXT: v_min_i32_e32 v8, v8, v10 -; GFX10-NEXT: v_min_i32_e32 v9, v11, v13 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v5 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v6 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v9 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v5 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, v1, v6 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, v2, v7 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, v3, v8 clamp +; GFX10-NEXT: v_sub_nc_i32 v4, v4, v9 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) @@ -1860,125 +1331,36 @@ ; ; GFX9-LABEL: s_ssubsat_v5i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_brev_b32 s10, -2 -; GFX9-NEXT: s_cselect_b32 s12, s0, -1 -; GFX9-NEXT: s_sub_i32 s12, s12, s10 -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_mov_b32 s11, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s13, s0, -1 -; GFX9-NEXT: s_sub_i32 s13, s13, s11 -; GFX9-NEXT: s_cmp_gt_i32 s12, s5 -; GFX9-NEXT: s_cselect_b32 s5, s12, s5 -; GFX9-NEXT: s_cmp_lt_i32 s5, s13 -; GFX9-NEXT: s_cselect_b32 s5, s5, s13 -; GFX9-NEXT: s_sub_i32 s0, s0, s5 -; GFX9-NEXT: s_cmp_gt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s5, s1, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s10 -; GFX9-NEXT: s_cmp_lt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s12, s1, -1 -; GFX9-NEXT: s_sub_i32 s12, s12, s11 -; GFX9-NEXT: s_cmp_gt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_lt_i32 s5, s12 -; GFX9-NEXT: s_cselect_b32 s5, s5, s12 -; GFX9-NEXT: s_sub_i32 s1, s1, s5 -; GFX9-NEXT: s_cmp_gt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s5, s2, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s10 -; GFX9-NEXT: s_cmp_lt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s6, s2, -1 -; GFX9-NEXT: s_sub_i32 s6, s6, s11 -; GFX9-NEXT: s_cmp_gt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_sub_i32 s2, s2, s5 -; GFX9-NEXT: s_cmp_gt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s5, s3, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s10 -; GFX9-NEXT: s_cmp_lt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s6, s3, -1 -; GFX9-NEXT: s_sub_i32 s6, s6, s11 -; GFX9-NEXT: s_cmp_gt_i32 s5, s8 -; GFX9-NEXT: s_cselect_b32 s5, s5, s8 -; GFX9-NEXT: s_cmp_lt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_sub_i32 s3, s3, s5 -; GFX9-NEXT: s_cmp_gt_i32 s4, -1 -; GFX9-NEXT: s_cselect_b32 s5, s4, -1 -; GFX9-NEXT: s_sub_i32 s5, s5, s10 -; GFX9-NEXT: s_cmp_lt_i32 s4, -1 -; GFX9-NEXT: s_cselect_b32 s6, s4, -1 -; GFX9-NEXT: s_sub_i32 s6, s6, s11 -; GFX9-NEXT: s_cmp_gt_i32 s5, s9 -; GFX9-NEXT: s_cselect_b32 s5, s5, s9 -; GFX9-NEXT: s_cmp_lt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_sub_i32 s4, s4, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s5 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 +; GFX9-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v5i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 -; GFX10-NEXT: s_brev_b32 s10, -2 -; GFX10-NEXT: s_cselect_b32 s11, s0, -1 -; GFX10-NEXT: s_mov_b32 s12, 0x80000000 -; GFX10-NEXT: s_sub_i32 s11, s11, s10 -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s5 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, s1, s6 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, s2, s7 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, s3, s8 clamp +; GFX10-NEXT: v_sub_nc_i32 v4, s4, s9 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s13, s0, -1 -; GFX10-NEXT: s_sub_i32 s13, s13, s12 -; GFX10-NEXT: s_cmp_gt_i32 s11, s5 -; GFX10-NEXT: s_cselect_b32 s5, s11, s5 -; GFX10-NEXT: s_cmp_lt_i32 s5, s13 -; GFX10-NEXT: s_cselect_b32 s5, s5, s13 -; GFX10-NEXT: s_sub_i32 s0, s0, s5 -; GFX10-NEXT: s_cmp_gt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s5, s1, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_lt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s11, s1, -1 -; GFX10-NEXT: s_sub_i32 s11, s11, s12 -; GFX10-NEXT: s_cmp_gt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_cmp_lt_i32 s5, s11 -; GFX10-NEXT: s_cselect_b32 s5, s5, s11 -; GFX10-NEXT: s_sub_i32 s1, s1, s5 -; GFX10-NEXT: s_cmp_gt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s5, s2, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_lt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s6, s2, -1 -; GFX10-NEXT: s_sub_i32 s6, s6, s12 -; GFX10-NEXT: s_cmp_gt_i32 s5, s7 -; GFX10-NEXT: s_cselect_b32 s5, s5, s7 -; GFX10-NEXT: s_cmp_lt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_sub_i32 s2, s2, s5 -; GFX10-NEXT: s_cmp_gt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s5, s3, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_lt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s6, s3, -1 -; GFX10-NEXT: s_sub_i32 s6, s6, s12 -; GFX10-NEXT: s_cmp_gt_i32 s5, s8 -; GFX10-NEXT: s_cselect_b32 s5, s5, s8 -; GFX10-NEXT: s_cmp_lt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_sub_i32 s3, s3, s5 -; GFX10-NEXT: s_cmp_gt_i32 s4, -1 -; GFX10-NEXT: s_cselect_b32 s5, s4, -1 -; GFX10-NEXT: s_sub_i32 s5, s5, s10 -; GFX10-NEXT: s_cmp_lt_i32 s4, -1 -; GFX10-NEXT: s_cselect_b32 s6, s4, -1 -; GFX10-NEXT: s_sub_i32 s6, s6, s12 -; GFX10-NEXT: s_cmp_gt_i32 s5, s9 -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_cmp_lt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_sub_i32 s4, s4, s5 ; GFX10-NEXT: ; return to shader part epilog %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) ret <5 x i32> %result @@ -2230,244 +1612,44 @@ ; GFX9-LABEL: v_ssubsat_v16i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_brev_b32 s4, -2 -; GFX9-NEXT: v_max_i32_e32 v32, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v32, s4, v32 -; GFX9-NEXT: v_max_i32_e32 v16, v32, v16 -; GFX9-NEXT: s_mov_b32 s5, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v32, -1, v0 -; GFX9-NEXT: v_subrev_u32_e32 v32, s5, v32 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v32 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v16 -; GFX9-NEXT: v_max_i32_e32 v16, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v16, s4, v16 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_min_i32_e32 v17, -1, v1 -; GFX9-NEXT: v_subrev_u32_e32 v17, s5, v17 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v16 -; GFX9-NEXT: v_max_i32_e32 v16, -1, v2 -; GFX9-NEXT: v_subrev_u32_e32 v16, s4, v16 -; GFX9-NEXT: v_min_i32_e32 v17, -1, v2 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v18 -; GFX9-NEXT: v_subrev_u32_e32 v17, s5, v17 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v16 -; GFX9-NEXT: v_bfrev_b32_e32 v16, -2 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v3 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_mov_b32_e32 v18, 0x80000000 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v3 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v4 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v4 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v20 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v4, v4, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v5 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v5 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v21 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v5, v5, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v6 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v6 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v22 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v6, v6, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v7 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v7 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v23 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v7, v7, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v8 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v8 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v24 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v8, v8, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v9 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v9 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v25 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v9, v9, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v10 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v10 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v26 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v10, v10, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v11 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v11 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v27 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v11, v11, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v12 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v12 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v28 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v12, v12, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v13 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v13 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v29 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v13, v13, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v14 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v19, -1, v14 -; GFX9-NEXT: v_max_i32_e32 v17, v17, v30 -; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18 -; GFX9-NEXT: v_min_i32_e32 v17, v17, v19 -; GFX9-NEXT: v_sub_u32_e32 v14, v14, v17 -; GFX9-NEXT: v_max_i32_e32 v17, -1, v15 -; GFX9-NEXT: v_sub_u32_e32 v16, v17, v16 -; GFX9-NEXT: v_min_i32_e32 v17, -1, v15 -; GFX9-NEXT: v_sub_u32_e32 v17, v17, v18 -; GFX9-NEXT: v_max_i32_e32 v16, v16, v31 -; GFX9-NEXT: v_min_i32_e32 v16, v16, v17 -; GFX9-NEXT: v_sub_u32_e32 v15, v15, v16 +; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp +; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp +; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp +; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp +; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp +; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp +; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp +; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp +; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp +; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp +; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp +; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp +; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp +; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp +; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp +; GFX9-NEXT: v_sub_i32 v15, v15, v31 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v16i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_max_i32_e32 v32, -1, v0 -; GFX10-NEXT: s_brev_b32 s4, -2 -; GFX10-NEXT: v_min_i32_e32 v33, -1, v0 -; GFX10-NEXT: s_mov_b32 s5, 0x80000000 -; GFX10-NEXT: v_max_i32_e32 v36, -1, v2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v35, s4, v32 -; GFX10-NEXT: v_max_i32_e32 v32, -1, v1 -; GFX10-NEXT: v_subrev_nc_u32_e32 v33, s5, v33 -; GFX10-NEXT: v_bfrev_b32_e32 v34, -2 -; GFX10-NEXT: v_subrev_nc_u32_e32 v36, s4, v36 -; GFX10-NEXT: v_max_i32_e32 v16, v35, v16 -; GFX10-NEXT: v_subrev_nc_u32_e32 v32, s4, v32 -; GFX10-NEXT: v_max_i32_e32 v39, -1, v3 -; GFX10-NEXT: v_min_i32_e32 v37, -1, v1 -; GFX10-NEXT: v_max_i32_e32 v18, v36, v18 -; GFX10-NEXT: v_min_i32_e32 v16, v16, v33 -; GFX10-NEXT: v_min_i32_e32 v33, -1, v2 -; GFX10-NEXT: v_max_i32_e32 v38, v32, v17 -; GFX10-NEXT: v_max_i32_e32 v17, -1, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v36, v39, v34 -; GFX10-NEXT: v_mov_b32_e32 v35, 0x80000000 -; GFX10-NEXT: v_subrev_nc_u32_e32 v32, s5, v33 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v16 -; GFX10-NEXT: v_min_i32_e32 v33, -1, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v34 -; GFX10-NEXT: v_subrev_nc_u32_e32 v37, s5, v37 -; GFX10-NEXT: v_min_i32_e32 v16, v18, v32 -; GFX10-NEXT: v_max_i32_e32 v19, v36, v19 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v33, v35 -; GFX10-NEXT: v_max_i32_e32 v17, v17, v20 -; GFX10-NEXT: v_min_i32_e32 v39, v38, v37 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v16 -; GFX10-NEXT: v_min_i32_e32 v16, -1, v4 -; GFX10-NEXT: v_min_i32_e32 v18, v19, v18 -; GFX10-NEXT: v_max_i32_e32 v19, -1, v5 -; GFX10-NEXT: v_max_i32_e32 v32, -1, v6 -; GFX10-NEXT: v_min_i32_e32 v33, -1, v5 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v39 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v19, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v32, v32, v34 -; GFX10-NEXT: v_min_i32_e32 v36, -1, v6 -; GFX10-NEXT: v_min_i32_e32 v39, v17, v16 -; GFX10-NEXT: v_max_i32_e32 v17, -1, v7 -; GFX10-NEXT: v_min_i32_e32 v16, -1, v7 -; GFX10-NEXT: v_max_i32_e32 v19, v19, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v33, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v39 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v21, v36, v35 -; GFX10-NEXT: v_max_i32_e32 v22, v32, v22 -; GFX10-NEXT: v_min_i32_e32 v38, v19, v20 -; GFX10-NEXT: v_max_i32_e32 v20, -1, v9 -; GFX10-NEXT: v_max_i32_e32 v39, -1, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v35 -; GFX10-NEXT: v_max_i32_e32 v17, v17, v23 -; GFX10-NEXT: v_min_i32_e32 v19, v22, v21 -; GFX10-NEXT: v_min_i32_e32 v21, -1, v9 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v20, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v39, v34 -; GFX10-NEXT: v_max_i32_e32 v39, -1, v10 -; GFX10-NEXT: v_min_i32_e32 v16, v17, v16 -; GFX10-NEXT: v_min_i32_e32 v22, -1, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v38 -; GFX10-NEXT: v_sub_nc_u32_e32 v6, v6, v19 -; GFX10-NEXT: v_max_i32_e32 v18, v18, v24 -; GFX10-NEXT: v_max_i32_e32 v20, v20, v25 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v22, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v21, v21, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v7, v7, v16 -; GFX10-NEXT: v_max_i32_e32 v16, -1, v11 -; GFX10-NEXT: v_min_i32_e32 v38, -1, v10 -; GFX10-NEXT: v_sub_nc_u32_e32 v23, v39, v34 -; GFX10-NEXT: v_min_i32_e32 v17, v18, v19 -; GFX10-NEXT: v_min_i32_e32 v20, v20, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v38, v35 -; GFX10-NEXT: v_max_i32_e32 v19, v23, v26 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, v8, v17 -; GFX10-NEXT: v_sub_nc_u32_e32 v9, v9, v20 -; GFX10-NEXT: v_max_i32_e32 v20, -1, v13 -; GFX10-NEXT: v_max_i32_e32 v16, v16, v27 -; GFX10-NEXT: v_min_i32_e32 v17, v19, v18 -; GFX10-NEXT: v_max_i32_e32 v19, -1, v12 -; GFX10-NEXT: v_max_i32_e32 v27, -1, v14 -; GFX10-NEXT: v_max_i32_e32 v23, -1, v15 -; GFX10-NEXT: v_min_i32_e32 v18, -1, v11 -; GFX10-NEXT: v_min_i32_e32 v21, -1, v13 -; GFX10-NEXT: v_sub_nc_u32_e32 v19, v19, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v20, v20, v34 -; GFX10-NEXT: v_min_i32_e32 v24, -1, v14 -; GFX10-NEXT: v_min_i32_e32 v25, -1, v15 -; GFX10-NEXT: v_sub_nc_u32_e32 v26, v23, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, v10, v17 -; GFX10-NEXT: v_min_i32_e32 v17, -1, v12 -; GFX10-NEXT: v_sub_nc_u32_e32 v27, v27, v34 -; GFX10-NEXT: v_sub_nc_u32_e32 v18, v18, v35 -; GFX10-NEXT: v_max_i32_e32 v19, v19, v28 -; GFX10-NEXT: v_sub_nc_u32_e32 v21, v21, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v35 -; GFX10-NEXT: v_max_i32_e32 v20, v20, v29 -; GFX10-NEXT: v_sub_nc_u32_e32 v24, v24, v35 -; GFX10-NEXT: v_max_i32_e32 v22, v27, v30 -; GFX10-NEXT: v_sub_nc_u32_e32 v25, v25, v35 -; GFX10-NEXT: v_max_i32_e32 v23, v26, v31 -; GFX10-NEXT: v_min_i32_e32 v16, v16, v18 -; GFX10-NEXT: v_min_i32_e32 v17, v19, v17 -; GFX10-NEXT: v_min_i32_e32 v18, v20, v21 -; GFX10-NEXT: v_min_i32_e32 v19, v22, v24 -; GFX10-NEXT: v_min_i32_e32 v20, v23, v25 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, v11, v16 -; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v17 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v14, v14, v19 -; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v20 +; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp +; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp +; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp +; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp +; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp +; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp +; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp +; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp +; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp +; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp +; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp +; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp +; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) @@ -2841,367 +2023,91 @@ ; ; GFX9-LABEL: s_ssubsat_v16i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_gt_i32 s0, -1 -; GFX9-NEXT: s_brev_b32 s32, -2 -; GFX9-NEXT: s_cselect_b32 s34, s0, -1 -; GFX9-NEXT: s_sub_i32 s34, s34, s32 -; GFX9-NEXT: s_cmp_lt_i32 s0, -1 -; GFX9-NEXT: s_mov_b32 s33, 0x80000000 -; GFX9-NEXT: s_cselect_b32 s35, s0, -1 -; GFX9-NEXT: s_sub_i32 s35, s35, s33 -; GFX9-NEXT: s_cmp_gt_i32 s34, s16 -; GFX9-NEXT: s_cselect_b32 s16, s34, s16 -; GFX9-NEXT: s_cmp_lt_i32 s16, s35 -; GFX9-NEXT: s_cselect_b32 s16, s16, s35 -; GFX9-NEXT: s_sub_i32 s0, s0, s16 -; GFX9-NEXT: s_cmp_gt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s16, s1, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s1, -1 -; GFX9-NEXT: s_cselect_b32 s34, s1, -1 -; GFX9-NEXT: s_sub_i32 s34, s34, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_cmp_lt_i32 s16, s34 -; GFX9-NEXT: s_cselect_b32 s16, s16, s34 -; GFX9-NEXT: s_sub_i32 s1, s1, s16 -; GFX9-NEXT: s_cmp_gt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s16, s2, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s2, -1 -; GFX9-NEXT: s_cselect_b32 s17, s2, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s18 -; GFX9-NEXT: s_cselect_b32 s16, s16, s18 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s2, s2, s16 -; GFX9-NEXT: s_cmp_gt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s16, s3, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s3, -1 -; GFX9-NEXT: s_cselect_b32 s17, s3, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s19 -; GFX9-NEXT: s_cselect_b32 s16, s16, s19 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s3, s3, s16 -; GFX9-NEXT: s_cmp_gt_i32 s4, -1 -; GFX9-NEXT: s_cselect_b32 s16, s4, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s4, -1 -; GFX9-NEXT: s_cselect_b32 s17, s4, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s20 -; GFX9-NEXT: s_cselect_b32 s16, s16, s20 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s4, s4, s16 -; GFX9-NEXT: s_cmp_gt_i32 s5, -1 -; GFX9-NEXT: s_cselect_b32 s16, s5, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s5, -1 -; GFX9-NEXT: s_cselect_b32 s17, s5, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s21 -; GFX9-NEXT: s_cselect_b32 s16, s16, s21 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s5, s5, s16 -; GFX9-NEXT: s_cmp_gt_i32 s6, -1 -; GFX9-NEXT: s_cselect_b32 s16, s6, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s6, -1 -; GFX9-NEXT: s_cselect_b32 s17, s6, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s22 -; GFX9-NEXT: s_cselect_b32 s16, s16, s22 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s6, s6, s16 -; GFX9-NEXT: s_cmp_gt_i32 s7, -1 -; GFX9-NEXT: s_cselect_b32 s16, s7, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s7, -1 -; GFX9-NEXT: s_cselect_b32 s17, s7, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s23 -; GFX9-NEXT: s_cselect_b32 s16, s16, s23 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s7, s7, s16 -; GFX9-NEXT: s_cmp_gt_i32 s8, -1 -; GFX9-NEXT: s_cselect_b32 s16, s8, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s8, -1 -; GFX9-NEXT: s_cselect_b32 s17, s8, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s24 -; GFX9-NEXT: s_cselect_b32 s16, s16, s24 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s8, s8, s16 -; GFX9-NEXT: s_cmp_gt_i32 s9, -1 -; GFX9-NEXT: s_cselect_b32 s16, s9, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s9, -1 -; GFX9-NEXT: s_cselect_b32 s17, s9, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s25 -; GFX9-NEXT: s_cselect_b32 s16, s16, s25 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s9, s9, s16 -; GFX9-NEXT: s_cmp_gt_i32 s10, -1 -; GFX9-NEXT: s_cselect_b32 s16, s10, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s10, -1 -; GFX9-NEXT: s_cselect_b32 s17, s10, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s26 -; GFX9-NEXT: s_cselect_b32 s16, s16, s26 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s10, s10, s16 -; GFX9-NEXT: s_cmp_gt_i32 s11, -1 -; GFX9-NEXT: s_cselect_b32 s16, s11, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s11, -1 -; GFX9-NEXT: s_cselect_b32 s17, s11, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s27 -; GFX9-NEXT: s_cselect_b32 s16, s16, s27 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s11, s11, s16 -; GFX9-NEXT: s_cmp_gt_i32 s12, -1 -; GFX9-NEXT: s_cselect_b32 s16, s12, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s12, -1 -; GFX9-NEXT: s_cselect_b32 s17, s12, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s28 -; GFX9-NEXT: s_cselect_b32 s16, s16, s28 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s12, s12, s16 -; GFX9-NEXT: s_cmp_gt_i32 s13, -1 -; GFX9-NEXT: s_cselect_b32 s16, s13, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s13, -1 -; GFX9-NEXT: s_cselect_b32 s17, s13, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s29 -; GFX9-NEXT: s_cselect_b32 s16, s16, s29 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s13, s13, s16 -; GFX9-NEXT: s_cmp_gt_i32 s14, -1 -; GFX9-NEXT: s_cselect_b32 s16, s14, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s14, -1 -; GFX9-NEXT: s_cselect_b32 s17, s14, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s30 -; GFX9-NEXT: s_cselect_b32 s16, s16, s30 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s14, s14, s16 -; GFX9-NEXT: s_cmp_gt_i32 s15, -1 -; GFX9-NEXT: s_cselect_b32 s16, s15, -1 -; GFX9-NEXT: s_sub_i32 s16, s16, s32 -; GFX9-NEXT: s_cmp_lt_i32 s15, -1 -; GFX9-NEXT: s_cselect_b32 s17, s15, -1 -; GFX9-NEXT: s_sub_i32 s17, s17, s33 -; GFX9-NEXT: s_cmp_gt_i32 s16, s31 -; GFX9-NEXT: s_cselect_b32 s16, s16, s31 -; GFX9-NEXT: s_cmp_lt_i32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_sub_i32 s15, s15, s16 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: v_mov_b32_e32 v14, s30 +; GFX9-NEXT: v_mov_b32_e32 v15, s31 +; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp +; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp +; GFX9-NEXT: v_sub_i32 v5, s5, v5 clamp +; GFX9-NEXT: v_sub_i32 v6, s6, v6 clamp +; GFX9-NEXT: v_sub_i32 v7, s7, v7 clamp +; GFX9-NEXT: v_sub_i32 v8, s8, v8 clamp +; GFX9-NEXT: v_sub_i32 v9, s9, v9 clamp +; GFX9-NEXT: v_sub_i32 v10, s10, v10 clamp +; GFX9-NEXT: v_sub_i32 v11, s11, v11 clamp +; GFX9-NEXT: v_sub_i32 v12, s12, v12 clamp +; GFX9-NEXT: v_sub_i32 v13, s13, v13 clamp +; GFX9-NEXT: v_sub_i32 v14, s14, v14 clamp +; GFX9-NEXT: v_sub_i32 v15, s15, v15 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 +; GFX9-NEXT: v_readfirstlane_b32 s5, v5 +; GFX9-NEXT: v_readfirstlane_b32 s6, v6 +; GFX9-NEXT: v_readfirstlane_b32 s7, v7 +; GFX9-NEXT: v_readfirstlane_b32 s8, v8 +; GFX9-NEXT: v_readfirstlane_b32 s9, v9 +; GFX9-NEXT: v_readfirstlane_b32 s10, v10 +; GFX9-NEXT: v_readfirstlane_b32 s11, v11 +; GFX9-NEXT: v_readfirstlane_b32 s12, v12 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v16i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_gt_i32 s0, -1 -; GFX10-NEXT: s_brev_b32 s46, -2 -; GFX10-NEXT: s_cselect_b32 s33, s0, -1 -; GFX10-NEXT: s_mov_b32 s34, 0x80000000 -; GFX10-NEXT: s_sub_i32 s47, s33, s46 -; GFX10-NEXT: s_cmp_lt_i32 s0, -1 +; GFX10-NEXT: v_sub_nc_i32 v0, s0, s16 clamp +; GFX10-NEXT: v_sub_nc_i32 v1, s1, s17 clamp +; GFX10-NEXT: v_sub_nc_i32 v2, s2, s18 clamp +; GFX10-NEXT: v_sub_nc_i32 v3, s3, s19 clamp +; GFX10-NEXT: v_sub_nc_i32 v4, s4, s20 clamp +; GFX10-NEXT: v_sub_nc_i32 v5, s5, s21 clamp +; GFX10-NEXT: v_sub_nc_i32 v6, s6, s22 clamp +; GFX10-NEXT: v_sub_nc_i32 v7, s7, s23 clamp +; GFX10-NEXT: v_sub_nc_i32 v8, s8, s24 clamp +; GFX10-NEXT: v_sub_nc_i32 v9, s9, s25 clamp +; GFX10-NEXT: v_sub_nc_i32 v10, s10, s26 clamp +; GFX10-NEXT: v_sub_nc_i32 v11, s11, s27 clamp +; GFX10-NEXT: v_sub_nc_i32 v12, s12, s28 clamp +; GFX10-NEXT: v_sub_nc_i32 v13, s13, s29 clamp +; GFX10-NEXT: v_sub_nc_i32 v14, s14, s30 clamp +; GFX10-NEXT: v_sub_nc_i32 v15, s15, s31 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 +; GFX10-NEXT: v_readfirstlane_b32 s5, v5 +; GFX10-NEXT: v_readfirstlane_b32 s6, v6 +; GFX10-NEXT: v_readfirstlane_b32 s7, v7 +; GFX10-NEXT: v_readfirstlane_b32 s8, v8 +; GFX10-NEXT: v_readfirstlane_b32 s9, v9 +; GFX10-NEXT: v_readfirstlane_b32 s10, v10 +; GFX10-NEXT: v_readfirstlane_b32 s11, v11 +; GFX10-NEXT: v_readfirstlane_b32 s12, v12 +; GFX10-NEXT: v_readfirstlane_b32 s13, v13 +; GFX10-NEXT: v_readfirstlane_b32 s14, v14 +; GFX10-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s35, s0, -1 -; GFX10-NEXT: s_sub_i32 s35, s35, s34 -; GFX10-NEXT: s_cmp_gt_i32 s47, s16 -; GFX10-NEXT: s_cselect_b32 s16, s47, s16 -; GFX10-NEXT: s_cmp_lt_i32 s16, s35 -; GFX10-NEXT: s_cselect_b32 s47, s16, s35 -; GFX10-NEXT: s_sub_i32 s0, s0, s47 -; GFX10-NEXT: s_cmp_gt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s16, s1, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s1, -1 -; GFX10-NEXT: s_cselect_b32 s33, s1, -1 -; GFX10-NEXT: s_sub_i32 s47, s33, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_cmp_lt_i32 s16, s47 -; GFX10-NEXT: s_cselect_b32 s47, s16, s47 -; GFX10-NEXT: s_sub_i32 s1, s1, s47 -; GFX10-NEXT: s_cmp_gt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s16, s2, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s2, -1 -; GFX10-NEXT: s_cselect_b32 s17, s2, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s18 -; GFX10-NEXT: s_cselect_b32 s16, s16, s18 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s2, s2, s16 -; GFX10-NEXT: s_cmp_gt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s16, s3, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s3, -1 -; GFX10-NEXT: s_cselect_b32 s17, s3, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s19 -; GFX10-NEXT: s_cselect_b32 s16, s16, s19 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s3, s3, s16 -; GFX10-NEXT: s_cmp_gt_i32 s4, -1 -; GFX10-NEXT: s_cselect_b32 s16, s4, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s4, -1 -; GFX10-NEXT: s_cselect_b32 s17, s4, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s20 -; GFX10-NEXT: s_cselect_b32 s16, s16, s20 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s4, s4, s16 -; GFX10-NEXT: s_cmp_gt_i32 s5, -1 -; GFX10-NEXT: s_cselect_b32 s16, s5, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s5, -1 -; GFX10-NEXT: s_cselect_b32 s17, s5, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s21 -; GFX10-NEXT: s_cselect_b32 s16, s16, s21 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s5, s5, s16 -; GFX10-NEXT: s_cmp_gt_i32 s6, -1 -; GFX10-NEXT: s_cselect_b32 s16, s6, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s6, -1 -; GFX10-NEXT: s_cselect_b32 s17, s6, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s22 -; GFX10-NEXT: s_cselect_b32 s16, s16, s22 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s6, s6, s16 -; GFX10-NEXT: s_cmp_gt_i32 s7, -1 -; GFX10-NEXT: s_cselect_b32 s16, s7, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s7, -1 -; GFX10-NEXT: s_cselect_b32 s17, s7, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s23 -; GFX10-NEXT: s_cselect_b32 s16, s16, s23 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s7, s7, s16 -; GFX10-NEXT: s_cmp_gt_i32 s8, -1 -; GFX10-NEXT: s_cselect_b32 s16, s8, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s8, -1 -; GFX10-NEXT: s_cselect_b32 s17, s8, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s24 -; GFX10-NEXT: s_cselect_b32 s16, s16, s24 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s8, s8, s16 -; GFX10-NEXT: s_cmp_gt_i32 s9, -1 -; GFX10-NEXT: s_cselect_b32 s16, s9, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s9, -1 -; GFX10-NEXT: s_cselect_b32 s17, s9, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s25 -; GFX10-NEXT: s_cselect_b32 s16, s16, s25 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s9, s9, s16 -; GFX10-NEXT: s_cmp_gt_i32 s10, -1 -; GFX10-NEXT: s_cselect_b32 s16, s10, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s10, -1 -; GFX10-NEXT: s_cselect_b32 s17, s10, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s26 -; GFX10-NEXT: s_cselect_b32 s16, s16, s26 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s10, s10, s16 -; GFX10-NEXT: s_cmp_gt_i32 s11, -1 -; GFX10-NEXT: s_cselect_b32 s16, s11, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s11, -1 -; GFX10-NEXT: s_cselect_b32 s17, s11, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s27 -; GFX10-NEXT: s_cselect_b32 s16, s16, s27 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s11, s11, s16 -; GFX10-NEXT: s_cmp_gt_i32 s12, -1 -; GFX10-NEXT: s_cselect_b32 s16, s12, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s12, -1 -; GFX10-NEXT: s_cselect_b32 s17, s12, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s28 -; GFX10-NEXT: s_cselect_b32 s16, s16, s28 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s12, s12, s16 -; GFX10-NEXT: s_cmp_gt_i32 s13, -1 -; GFX10-NEXT: s_cselect_b32 s16, s13, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s13, -1 -; GFX10-NEXT: s_cselect_b32 s17, s13, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s29 -; GFX10-NEXT: s_cselect_b32 s16, s16, s29 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s13, s13, s16 -; GFX10-NEXT: s_cmp_gt_i32 s14, -1 -; GFX10-NEXT: s_cselect_b32 s16, s14, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s14, -1 -; GFX10-NEXT: s_cselect_b32 s17, s14, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s30 -; GFX10-NEXT: s_cselect_b32 s16, s16, s30 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s14, s14, s16 -; GFX10-NEXT: s_cmp_gt_i32 s15, -1 -; GFX10-NEXT: s_cselect_b32 s16, s15, -1 -; GFX10-NEXT: s_sub_i32 s16, s16, s46 -; GFX10-NEXT: s_cmp_lt_i32 s15, -1 -; GFX10-NEXT: s_cselect_b32 s17, s15, -1 -; GFX10-NEXT: s_sub_i32 s17, s17, s34 -; GFX10-NEXT: s_cmp_gt_i32 s16, s31 -; GFX10-NEXT: s_cselect_b32 s16, s16, s31 -; GFX10-NEXT: s_cmp_lt_i32 s16, s17 -; GFX10-NEXT: s_cselect_b32 s16, s16, s17 -; GFX10-NEXT: s_sub_i32 s15, s15, s16 ; GFX10-NEXT: ; return to shader part epilog %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) ret <16 x i32> %result @@ -3239,29 +2145,15 @@ ; GFX9-LABEL: v_ssubsat_i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_mov_b32 s4, 0xffff -; GFX9-NEXT: v_max_i16_e32 v2, s4, v0 -; GFX9-NEXT: v_min_i16_e32 v3, s4, v0 -; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3 -; GFX9-NEXT: v_max_i16_e32 v1, v2, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v3 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_mov_b32 s4, 0xffff +; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_max_i16_e64 v2, v0, s4 -; GFX10-NEXT: v_min_i16_e64 v3, v0, s4 -; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff -; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000 -; GFX10-NEXT: v_max_i16_e64 v1, v2, v1 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v3 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -3309,45 +2201,16 @@ ; ; GFX9-LABEL: s_ssubsat_i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sext_i32_i16 s2, s0 -; GFX9-NEXT: s_sext_i32_i16 s3, 0xffff -; GFX9-NEXT: s_cmp_gt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s4, s2, s3 -; GFX9-NEXT: s_sub_i32 s4, s4, 0x7fff -; GFX9-NEXT: s_cmp_lt_i32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_sub_i32 s2, s2, 0x8000 -; GFX9-NEXT: s_sext_i32_i16 s3, s4 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_cmp_gt_i32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_sext_i32_i16 s1, s1 -; GFX9-NEXT: s_sext_i32_i16 s2, s2 -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sext_i32_i16 s2, 0xffff -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_gt_i32 s3, s2 +; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s4, s3, s2 -; GFX10-NEXT: s_sub_i32 s4, s4, 0x7fff -; GFX10-NEXT: s_cmp_lt_i32 s3, s2 -; GFX10-NEXT: s_cselect_b32 s2, s3, s2 -; GFX10-NEXT: s_sext_i32_i16 s3, s4 -; GFX10-NEXT: s_sub_i32 s2, s2, 0x8000 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s2, s2 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s1, s1 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -3387,33 +2250,13 @@ ; ; GFX9-LABEL: ssubsat_i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_sext_i32_i16 s1, s0 -; GFX9-NEXT: s_sext_i32_i16 s2, 0xffff -; GFX9-NEXT: s_cmp_gt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s3, s1, s2 -; GFX9-NEXT: s_sub_i32 s3, s3, 0x7fff -; GFX9-NEXT: s_cmp_lt_i32 s1, s2 -; GFX9-NEXT: s_cselect_b32 s1, s1, s2 -; GFX9-NEXT: s_sub_i32 s1, s1, 0x8000 -; GFX9-NEXT: v_max_i16_e32 v0, s3, v0 -; GFX9-NEXT: v_min_i16_e32 v0, s1, v0 -; GFX9-NEXT: v_sub_u16_e32 v0, s0, v0 +; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_sext_i32_i16 s1, s0 -; GFX10-NEXT: s_sext_i32_i16 s2, 0xffff +; GFX10-NEXT: v_sub_nc_i16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_gt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s3, s1, s2 -; GFX10-NEXT: s_sub_i32 s3, s3, 0x7fff -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: v_max_i16_e64 v0, s3, v0 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_sub_i32 s1, s1, 0x8000 -; GFX10-NEXT: v_min_i16_e64 v0, v0, s1 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -3449,27 +2292,13 @@ ; ; GFX9-LABEL: ssubsat_i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s1, 0xffff -; GFX9-NEXT: v_max_i16_e32 v1, s1, v0 -; GFX9-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1 -; GFX9-NEXT: v_min_i16_e32 v2, s1, v0 -; GFX9-NEXT: v_subrev_u16_e32 v2, 0x8000, v2 -; GFX9-NEXT: v_max_i16_e32 v1, s0, v1 -; GFX9-NEXT: v_min_i16_e32 v1, v1, v2 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_i16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_mov_b32 s1, 0xffff +; GFX10-NEXT: v_sub_nc_i16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_max_i16_e64 v1, v0, s1 -; GFX10-NEXT: v_min_i16_e64 v2, v0, s1 -; GFX10-NEXT: v_sub_nc_u16_e64 v1, v1, 0x7fff -; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x8000 -; GFX10-NEXT: v_max_i16_e64 v1, v1, s0 -; GFX10-NEXT: v_min_i16_e64 v1, v1, v2 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -3531,37 +2360,15 @@ ; GFX9-LABEL: v_ssubsat_v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v2, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v3, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v3, v3, s5 -; GFX9-NEXT: v_pk_max_i16 v1, v2, v1 -; GFX9-NEXT: v_pk_min_i16 v1, v1, v3 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v2i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX10-NEXT: s_movk_i32 s5, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v2, v0, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX10-NEXT: v_pk_min_i16 v3, v0, s4 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 +; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v2, v2, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s6, s6 -; GFX10-NEXT: v_pk_sub_i16 v3, v3, s4 -; GFX10-NEXT: v_pk_max_i16 v1, v2, v1 -; GFX10-NEXT: v_pk_min_i16 v1, v1, v3 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) ret <2 x i16> %result @@ -3654,115 +2461,16 @@ ; ; GFX9-LABEL: s_ssubsat_v2i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: s_sext_i32_i16 s7, s4 -; GFX9-NEXT: s_sext_i32_i16 s5, s0 -; GFX9-NEXT: s_ashr_i32 s6, s0, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s8, s5, s7 -; GFX9-NEXT: s_cmp_gt_i32 s6, s4 -; GFX9-NEXT: s_movk_i32 s2, 0x7fff -; GFX9-NEXT: s_cselect_b32 s9, s6, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: s_lshr_b32 s10, s2, 16 -; GFX9-NEXT: s_lshr_b32 s9, s8, 16 -; GFX9-NEXT: s_sub_i32 s2, s8, s2 -; GFX9-NEXT: s_sub_i32 s8, s9, s10 -; GFX9-NEXT: s_cmp_lt_i32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_i32 s6, s4 -; GFX9-NEXT: s_mov_b32 s3, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s4, s6, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s3 -; GFX9-NEXT: s_lshr_b32 s6, s3, 16 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_sub_i32 s3, s4, s3 -; GFX9-NEXT: s_sub_i32 s4, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s2 -; GFX9-NEXT: s_sext_i32_i16 s5, s1 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_ashr_i32 s1, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_gt_i32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s1 -; GFX9-NEXT: s_sext_i32_i16 s2, s1 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_ashr_i32 s1, s1, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_lt_i32 s2, s4 -; GFX9-NEXT: s_cselect_b32 s2, s2, s4 -; GFX9-NEXT: s_cmp_lt_i32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s1, s1, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX9-NEXT: s_lshr_b32 s2, s0, 16 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_sub_i32 s1, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v2i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s2, -1, -1 -; GFX10-NEXT: s_sext_i32_i16 s3, s0 -; GFX10-NEXT: s_sext_i32_i16 s5, s2 -; GFX10-NEXT: s_ashr_i32 s4, s0, 16 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s3, s5 -; GFX10-NEXT: s_movk_i32 s8, 0x7fff -; GFX10-NEXT: s_cselect_b32 s6, s3, s5 -; GFX10-NEXT: s_cmp_gt_i32 s4, s2 +; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s7, s4, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s8, s8 -; GFX10-NEXT: s_lshr_b32 s8, s6, 16 -; GFX10-NEXT: s_lshr_b32 s9, s7, 16 -; GFX10-NEXT: s_sub_i32 s6, s6, s7 -; GFX10-NEXT: s_sub_i32 s7, s8, s9 -; GFX10-NEXT: s_cmp_lt_i32 s3, s5 -; GFX10-NEXT: s_cselect_b32 s3, s3, s5 -; GFX10-NEXT: s_cmp_lt_i32 s4, s2 -; GFX10-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s2, s4, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s6, s7 -; GFX10-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-NEXT: s_lshr_b32 s6, s4, 16 -; GFX10-NEXT: s_sub_i32 s2, s2, s4 -; GFX10-NEXT: s_sub_i32 s4, s5, s6 -; GFX10-NEXT: s_sext_i32_i16 s5, s3 -; GFX10-NEXT: s_sext_i32_i16 s6, s1 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 -; GFX10-NEXT: s_sext_i32_i16 s4, s2 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s5, s1 -; GFX10-NEXT: s_sext_i32_i16 s3, s1 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_cmp_lt_i32 s1, s2 -; GFX10-NEXT: s_cselect_b32 s1, s1, s2 -; GFX10-NEXT: s_lshr_b32 s2, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_sub_i32 s1, s2, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to i32 @@ -3838,75 +2546,13 @@ ; ; GFX9-LABEL: ssubsat_v2i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s3, -1, -1 -; GFX9-NEXT: s_sext_i32_i16 s6, s3 -; GFX9-NEXT: s_sext_i32_i16 s4, s0 -; GFX9-NEXT: s_ashr_i32 s5, s0, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s7, s4, s6 -; GFX9-NEXT: s_cmp_gt_i32 s5, s3 -; GFX9-NEXT: s_movk_i32 s1, 0x7fff -; GFX9-NEXT: s_cselect_b32 s8, s5, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s1 -; GFX9-NEXT: s_lshr_b32 s9, s1, 16 -; GFX9-NEXT: s_lshr_b32 s8, s7, 16 -; GFX9-NEXT: s_sub_i32 s1, s7, s1 -; GFX9-NEXT: s_sub_i32 s7, s8, s9 -; GFX9-NEXT: s_cmp_lt_i32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_cmp_lt_i32 s5, s3 -; GFX9-NEXT: s_mov_b32 s2, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s3, s5, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s7 -; GFX9-NEXT: s_sub_i32 s2, s3, s2 -; GFX9-NEXT: s_sub_i32 s3, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 -; GFX9-NEXT: v_pk_max_i16 v0, s1, v0 -; GFX9-NEXT: v_pk_min_i16 v0, v0, s2 -; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 +; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_v2i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, -1, -1 -; GFX10-NEXT: s_sext_i32_i16 s2, s0 -; GFX10-NEXT: s_sext_i32_i16 s4, s1 -; GFX10-NEXT: s_ashr_i32 s3, s0, 16 -; GFX10-NEXT: s_ashr_i32 s1, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s2, s4 -; GFX10-NEXT: s_movk_i32 s7, 0x7fff -; GFX10-NEXT: s_cselect_b32 s5, s2, s4 -; GFX10-NEXT: s_cmp_gt_i32 s3, s1 +; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s6, s3, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s7, s7 -; GFX10-NEXT: s_lshr_b32 s7, s5, 16 -; GFX10-NEXT: s_lshr_b32 s8, s6, 16 -; GFX10-NEXT: s_sub_i32 s5, s5, s6 -; GFX10-NEXT: s_sub_i32 s6, s7, s8 -; GFX10-NEXT: s_cmp_lt_i32 s2, s4 -; GFX10-NEXT: s_cselect_b32 s2, s2, s4 -; GFX10-NEXT: s_cmp_lt_i32 s3, s1 -; GFX10-NEXT: s_mov_b32 s4, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s5, s6 -; GFX10-NEXT: s_lshr_b32 s4, s1, 16 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: v_pk_max_i16 v0, s2, v0 -; GFX10-NEXT: s_sub_i32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s2, s4, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2 -; GFX10-NEXT: v_pk_min_i16 v0, v0, s1 -; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -3971,35 +2617,13 @@ ; ; GFX9-LABEL: ssubsat_v2i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_movk_i32 s1, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s3, -1, -1 -; GFX9-NEXT: s_mov_b32 s2, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s1 -; GFX9-NEXT: v_pk_max_i16 v1, v0, s3 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, s1 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX9-NEXT: v_pk_min_i16 v2, v0, s3 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, s2 -; GFX9-NEXT: v_pk_max_i16 v1, v1, s0 -; GFX9-NEXT: v_pk_min_i16 v1, v1, v2 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 +; GFX9-NEXT: v_pk_sub_i16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: ssubsat_v2i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, -1, -1 -; GFX10-NEXT: s_movk_i32 s2, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v1, v0, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s2 -; GFX10-NEXT: v_pk_min_i16 v2, v0, s1 -; GFX10-NEXT: s_mov_b32 s3, 0xffff8000 +; GFX10-NEXT: v_pk_sub_i16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v1, v1, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s3 -; GFX10-NEXT: v_pk_sub_i16 v2, v2, s1 -; GFX10-NEXT: v_pk_max_i16 v1, v1, s0 -; GFX10-NEXT: v_pk_min_i16 v1, v1, v2 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -4119,51 +2743,17 @@ ; GFX9-LABEL: v_ssubsat_v4i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v4, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v5, v0, s6 -; GFX9-NEXT: v_pk_max_i16 v2, v4, v2 -; GFX9-NEXT: v_pk_sub_i16 v5, v5, s5 -; GFX9-NEXT: v_pk_min_i16 v2, v2, v5 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 -; GFX9-NEXT: v_pk_max_i16 v2, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, s4 -; GFX9-NEXT: v_pk_min_i16 v4, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s5 -; GFX9-NEXT: v_pk_max_i16 v2, v2, v3 -; GFX9-NEXT: v_pk_min_i16 v2, v2, v4 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2 +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v4i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, -1, -1 -; GFX10-NEXT: s_movk_i32 s4, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v4, v0, s5 -; GFX10-NEXT: v_pk_max_i16 v5, v1, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX10-NEXT: v_pk_min_i16 v6, v0, s5 -; GFX10-NEXT: v_pk_min_i16 v7, v1, s5 -; GFX10-NEXT: v_pk_sub_i16 v4, v4, s4 -; GFX10-NEXT: v_pk_sub_i16 v5, v5, s4 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 +; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v11, v4, v2 -; GFX10-NEXT: v_pk_sub_i16 v6, v6, s6 -; GFX10-NEXT: v_pk_sub_i16 v4, v7, s6 -; GFX10-NEXT: v_pk_max_i16 v3, v5, v3 -; GFX10-NEXT: v_pk_min_i16 v2, v11, v6 -; GFX10-NEXT: v_pk_min_i16 v3, v3, v4 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x float> @@ -4327,201 +2917,21 @@ ; ; GFX9-LABEL: s_ssubsat_v4i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_sext_i32_i16 s9, s6 -; GFX9-NEXT: s_sext_i32_i16 s7, s0 -; GFX9-NEXT: s_ashr_i32 s8, s0, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_gt_i32 s7, s9 -; GFX9-NEXT: s_cselect_b32 s10, s7, s9 -; GFX9-NEXT: s_cmp_gt_i32 s8, s6 -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_cselect_b32 s11, s8, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: s_lshr_b32 s11, s10, 16 -; GFX9-NEXT: s_lshr_b32 s12, s4, 16 -; GFX9-NEXT: s_sub_i32 s10, s10, s4 -; GFX9-NEXT: s_sub_i32 s11, s11, s12 -; GFX9-NEXT: s_cmp_lt_i32 s7, s9 -; GFX9-NEXT: s_cselect_b32 s7, s7, s9 -; GFX9-NEXT: s_cmp_lt_i32 s8, s6 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s8, s8, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11 -; GFX9-NEXT: s_lshr_b32 s8, s7, 16 -; GFX9-NEXT: s_lshr_b32 s11, s5, 16 -; GFX9-NEXT: s_sub_i32 s7, s7, s5 -; GFX9-NEXT: s_sub_i32 s8, s8, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX9-NEXT: s_sext_i32_i16 s8, s10 -; GFX9-NEXT: s_sext_i32_i16 s13, s2 -; GFX9-NEXT: s_ashr_i32 s10, s10, 16 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s8, s13 -; GFX9-NEXT: s_cselect_b32 s8, s8, s13 -; GFX9-NEXT: s_cmp_gt_i32 s10, s2 -; GFX9-NEXT: s_cselect_b32 s2, s10, s2 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s8, s2 -; GFX9-NEXT: s_sext_i32_i16 s8, s2 -; GFX9-NEXT: s_sext_i32_i16 s10, s7 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_ashr_i32 s7, s7, 16 -; GFX9-NEXT: s_cmp_lt_i32 s8, s10 -; GFX9-NEXT: s_cselect_b32 s8, s8, s10 -; GFX9-NEXT: s_cmp_lt_i32 s2, s7 -; GFX9-NEXT: s_cselect_b32 s2, s2, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s8, s2 -; GFX9-NEXT: s_lshr_b32 s7, s0, 16 -; GFX9-NEXT: s_lshr_b32 s8, s2, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s2 -; GFX9-NEXT: s_sub_i32 s2, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX9-NEXT: s_sext_i32_i16 s2, s1 -; GFX9-NEXT: s_ashr_i32 s7, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s2, s9 -; GFX9-NEXT: s_cselect_b32 s8, s2, s9 -; GFX9-NEXT: s_cmp_gt_i32 s7, s6 -; GFX9-NEXT: s_cselect_b32 s10, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s10 -; GFX9-NEXT: s_lshr_b32 s10, s8, 16 -; GFX9-NEXT: s_sub_i32 s4, s8, s4 -; GFX9-NEXT: s_sub_i32 s8, s10, s12 -; GFX9-NEXT: s_cmp_lt_i32 s2, s9 -; GFX9-NEXT: s_cselect_b32 s2, s2, s9 -; GFX9-NEXT: s_cmp_lt_i32 s7, s6 -; GFX9-NEXT: s_cselect_b32 s6, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX9-NEXT: s_lshr_b32 s6, s2, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s5 -; GFX9-NEXT: s_sub_i32 s5, s6, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s6, s3 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_gt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s5, s3 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_sext_i32_i16 s5, s2 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s2, s2, 16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_i32 s3, s2 -; GFX9-NEXT: s_cselect_b32 s2, s3, s2 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s2 -; GFX9-NEXT: s_sub_i32 s2, s3, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v4i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX10-NEXT: s_sext_i32_i16 s5, s0 -; GFX10-NEXT: s_sext_i32_i16 s7, s4 -; GFX10-NEXT: s_ashr_i32 s6, s0, 16 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_gt_i32 s5, s7 -; GFX10-NEXT: s_movk_i32 s10, 0x7fff -; GFX10-NEXT: s_cselect_b32 s8, s5, s7 -; GFX10-NEXT: s_cmp_gt_i32 s6, s4 -; GFX10-NEXT: s_mov_b32 s12, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s9, s6, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s10, s10 -; GFX10-NEXT: s_lshr_b32 s10, s8, 16 -; GFX10-NEXT: s_lshr_b32 s11, s9, 16 -; GFX10-NEXT: s_sub_i32 s8, s8, s9 -; GFX10-NEXT: s_sub_i32 s10, s10, s11 -; GFX10-NEXT: s_cmp_lt_i32 s5, s7 -; GFX10-NEXT: s_sext_i32_i16 s14, s2 -; GFX10-NEXT: s_cselect_b32 s5, s5, s7 -; GFX10-NEXT: s_cmp_lt_i32 s6, s4 +; GFX10-NEXT: v_pk_sub_i16 v0, s0, s2 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s6, s6, s4 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s8, s10 -; GFX10-NEXT: s_lshr_b32 s8, s5, 16 -; GFX10-NEXT: s_lshr_b32 s10, s12, 16 -; GFX10-NEXT: s_sext_i32_i16 s13, s6 -; GFX10-NEXT: s_sub_i32 s5, s5, s12 -; GFX10-NEXT: s_sub_i32 s8, s8, s10 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_gt_i32 s13, s14 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s8 -; GFX10-NEXT: s_cselect_b32 s13, s13, s14 -; GFX10-NEXT: s_cmp_gt_i32 s6, s2 -; GFX10-NEXT: s_sext_i32_i16 s8, s5 -; GFX10-NEXT: s_cselect_b32 s2, s6, s2 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s13, s2 -; GFX10-NEXT: s_sext_i32_i16 s6, s2 -; GFX10-NEXT: s_ashr_i32 s2, s2, 16 -; GFX10-NEXT: s_cmp_lt_i32 s6, s8 -; GFX10-NEXT: s_cselect_b32 s6, s6, s8 -; GFX10-NEXT: s_cmp_lt_i32 s2, s5 -; GFX10-NEXT: s_cselect_b32 s2, s2, s5 -; GFX10-NEXT: s_lshr_b32 s5, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2 -; GFX10-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s2 -; GFX10-NEXT: s_sub_i32 s2, s5, s6 -; GFX10-NEXT: s_sext_i32_i16 s5, s1 -; GFX10-NEXT: s_ashr_i32 s6, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s5, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX10-NEXT: s_cselect_b32 s8, s5, s7 -; GFX10-NEXT: s_cmp_gt_i32 s6, s4 -; GFX10-NEXT: s_cselect_b32 s13, s6, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s13 -; GFX10-NEXT: s_lshr_b32 s13, s8, 16 -; GFX10-NEXT: s_sub_i32 s8, s8, s9 -; GFX10-NEXT: s_sub_i32 s9, s13, s11 -; GFX10-NEXT: s_cmp_lt_i32 s5, s7 -; GFX10-NEXT: s_cselect_b32 s5, s5, s7 -; GFX10-NEXT: s_cmp_lt_i32 s6, s4 -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s8, s9 -; GFX10-NEXT: s_lshr_b32 s6, s4, 16 -; GFX10-NEXT: s_sext_i32_i16 s7, s5 -; GFX10-NEXT: s_sext_i32_i16 s8, s3 -; GFX10-NEXT: s_sub_i32 s4, s4, s12 -; GFX10-NEXT: s_sub_i32 s6, s6, s10 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6 -; GFX10-NEXT: s_cselect_b32 s7, s7, s8 -; GFX10-NEXT: s_cmp_gt_i32 s5, s3 -; GFX10-NEXT: s_sext_i32_i16 s6, s4 -; GFX10-NEXT: s_cselect_b32 s3, s5, s3 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s7, s3 -; GFX10-NEXT: s_sext_i32_i16 s5, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_cmp_lt_i32 s3, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s4 -; GFX10-NEXT: s_lshr_b32 s4, s1, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s3, s4, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x i32> @@ -4684,65 +3094,19 @@ ; GFX9-LABEL: v_ssubsat_v6i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v6, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v6, v6, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v7, v0, s6 -; GFX9-NEXT: v_pk_max_i16 v3, v6, v3 -; GFX9-NEXT: v_pk_sub_i16 v7, v7, s5 -; GFX9-NEXT: v_pk_min_i16 v3, v3, v7 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 -; GFX9-NEXT: v_pk_max_i16 v3, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v3, v3, s4 -; GFX9-NEXT: v_pk_min_i16 v6, v1, s6 -; GFX9-NEXT: v_pk_max_i16 v3, v3, v4 -; GFX9-NEXT: v_pk_sub_i16 v6, v6, s5 -; GFX9-NEXT: v_pk_min_i16 v3, v3, v6 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 -; GFX9-NEXT: v_pk_max_i16 v3, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v3, v3, s4 -; GFX9-NEXT: v_pk_min_i16 v4, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s5 -; GFX9-NEXT: v_pk_max_i16 v3, v3, v5 -; GFX9-NEXT: v_pk_min_i16 v3, v3, v4 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3 +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 clamp +; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v6i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, -1, -1 -; GFX10-NEXT: s_movk_i32 s4, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v6, v0, s5 -; GFX10-NEXT: v_pk_max_i16 v8, v1, s5 -; GFX10-NEXT: v_pk_max_i16 v9, v2, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX10-NEXT: v_pk_min_i16 v7, v0, s5 -; GFX10-NEXT: v_pk_sub_i16 v6, v6, s4 -; GFX10-NEXT: v_pk_sub_i16 v15, v8, s4 -; GFX10-NEXT: v_pk_sub_i16 v19, v9, s4 -; GFX10-NEXT: v_pk_min_i16 v10, v1, s5 -; GFX10-NEXT: v_pk_min_i16 v11, v2, s5 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 -; GFX10-NEXT: v_pk_max_i16 v14, v6, v3 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v4, v15, v4 -; GFX10-NEXT: v_pk_sub_i16 v7, v7, s6 -; GFX10-NEXT: v_pk_sub_i16 v6, v10, s6 -; GFX10-NEXT: v_pk_sub_i16 v8, v11, s6 -; GFX10-NEXT: v_pk_max_i16 v5, v19, v5 +; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 clamp +; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_min_i16 v3, v14, v7 -; GFX10-NEXT: v_pk_min_i16 v4, v4, v6 -; GFX10-NEXT: v_pk_min_i16 v5, v5, v8 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 -; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x float> @@ -4976,287 +3340,26 @@ ; ; GFX9-LABEL: s_ssubsat_v6i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s8, -1, -1 -; GFX9-NEXT: s_sext_i32_i16 s11, s8 -; GFX9-NEXT: s_sext_i32_i16 s9, s0 -; GFX9-NEXT: s_ashr_i32 s10, s0, 16 -; GFX9-NEXT: s_ashr_i32 s8, s8, 16 -; GFX9-NEXT: s_cmp_gt_i32 s9, s11 -; GFX9-NEXT: s_cselect_b32 s12, s9, s11 -; GFX9-NEXT: s_cmp_gt_i32 s10, s8 -; GFX9-NEXT: s_movk_i32 s6, 0x7fff -; GFX9-NEXT: s_cselect_b32 s13, s10, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX9-NEXT: s_lshr_b32 s13, s12, 16 -; GFX9-NEXT: s_lshr_b32 s14, s6, 16 -; GFX9-NEXT: s_sub_i32 s12, s12, s6 -; GFX9-NEXT: s_sub_i32 s13, s13, s14 -; GFX9-NEXT: s_cmp_lt_i32 s9, s11 -; GFX9-NEXT: s_cselect_b32 s9, s9, s11 -; GFX9-NEXT: s_cmp_lt_i32 s10, s8 -; GFX9-NEXT: s_mov_b32 s7, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s10, s10, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s13 -; GFX9-NEXT: s_lshr_b32 s10, s9, 16 -; GFX9-NEXT: s_lshr_b32 s13, s7, 16 -; GFX9-NEXT: s_sub_i32 s9, s9, s7 -; GFX9-NEXT: s_sub_i32 s10, s10, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX9-NEXT: s_sext_i32_i16 s10, s12 -; GFX9-NEXT: s_sext_i32_i16 s15, s3 -; GFX9-NEXT: s_ashr_i32 s12, s12, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s10, s15 -; GFX9-NEXT: s_cselect_b32 s10, s10, s15 -; GFX9-NEXT: s_cmp_gt_i32 s12, s3 -; GFX9-NEXT: s_cselect_b32 s3, s12, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s10, s3 -; GFX9-NEXT: s_sext_i32_i16 s10, s3 -; GFX9-NEXT: s_sext_i32_i16 s12, s9 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_ashr_i32 s9, s9, 16 -; GFX9-NEXT: s_cmp_lt_i32 s10, s12 -; GFX9-NEXT: s_cselect_b32 s10, s10, s12 -; GFX9-NEXT: s_cmp_lt_i32 s3, s9 -; GFX9-NEXT: s_cselect_b32 s3, s3, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s10, s3 -; GFX9-NEXT: s_lshr_b32 s9, s0, 16 -; GFX9-NEXT: s_lshr_b32 s10, s3, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s3 -; GFX9-NEXT: s_sub_i32 s3, s9, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3 -; GFX9-NEXT: s_sext_i32_i16 s3, s1 -; GFX9-NEXT: s_ashr_i32 s9, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s10, s3, s11 -; GFX9-NEXT: s_cmp_gt_i32 s9, s8 -; GFX9-NEXT: s_cselect_b32 s12, s9, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s12 -; GFX9-NEXT: s_lshr_b32 s12, s10, 16 -; GFX9-NEXT: s_sub_i32 s10, s10, s6 -; GFX9-NEXT: s_sub_i32 s12, s12, s14 -; GFX9-NEXT: s_cmp_lt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s3, s3, s11 -; GFX9-NEXT: s_cmp_lt_i32 s9, s8 -; GFX9-NEXT: s_cselect_b32 s9, s9, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s9 -; GFX9-NEXT: s_lshr_b32 s9, s3, 16 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s12 -; GFX9-NEXT: s_sub_i32 s3, s3, s7 -; GFX9-NEXT: s_sub_i32 s9, s9, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s9 -; GFX9-NEXT: s_sext_i32_i16 s9, s10 -; GFX9-NEXT: s_sext_i32_i16 s12, s4 -; GFX9-NEXT: s_ashr_i32 s10, s10, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s9, s12 -; GFX9-NEXT: s_cselect_b32 s9, s9, s12 -; GFX9-NEXT: s_cmp_gt_i32 s10, s4 -; GFX9-NEXT: s_cselect_b32 s4, s10, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s9, s4 -; GFX9-NEXT: s_sext_i32_i16 s9, s4 -; GFX9-NEXT: s_sext_i32_i16 s10, s3 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_lt_i32 s9, s10 -; GFX9-NEXT: s_cselect_b32 s9, s9, s10 -; GFX9-NEXT: s_cmp_lt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s9, s3 -; GFX9-NEXT: s_lshr_b32 s4, s1, 16 -; GFX9-NEXT: s_lshr_b32 s9, s3, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s3, s4, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3 -; GFX9-NEXT: s_sext_i32_i16 s3, s2 -; GFX9-NEXT: s_ashr_i32 s4, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s9, s3, s11 -; GFX9-NEXT: s_cmp_gt_i32 s4, s8 -; GFX9-NEXT: s_cselect_b32 s10, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX9-NEXT: s_lshr_b32 s10, s9, 16 -; GFX9-NEXT: s_sub_i32 s6, s9, s6 -; GFX9-NEXT: s_sub_i32 s9, s10, s14 -; GFX9-NEXT: s_cmp_lt_i32 s3, s11 -; GFX9-NEXT: s_cselect_b32 s3, s3, s11 -; GFX9-NEXT: s_cmp_lt_i32 s4, s8 -; GFX9-NEXT: s_cselect_b32 s4, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_sub_i32 s3, s3, s7 -; GFX9-NEXT: s_sub_i32 s4, s4, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s6 -; GFX9-NEXT: s_sext_i32_i16 s7, s5 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_cmp_gt_i32 s6, s5 -; GFX9-NEXT: s_cselect_b32 s5, s6, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_sext_i32_i16 s5, s4 -; GFX9-NEXT: s_sext_i32_i16 s6, s3 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s3, s3, 16 -; GFX9-NEXT: s_cmp_lt_i32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_lt_i32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s5, s3 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s3 -; GFX9-NEXT: s_sub_i32 s3, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v6i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX10-NEXT: s_sext_i32_i16 s7, s0 -; GFX10-NEXT: s_sext_i32_i16 s9, s6 -; GFX10-NEXT: s_ashr_i32 s8, s0, 16 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s9 -; GFX10-NEXT: s_movk_i32 s12, 0x7fff -; GFX10-NEXT: s_cselect_b32 s10, s7, s9 -; GFX10-NEXT: s_cmp_gt_i32 s8, s6 -; GFX10-NEXT: s_mov_b32 s14, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s11, s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s14, s14, s14 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s10, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s11, s12, s12 -; GFX10-NEXT: s_lshr_b32 s12, s10, 16 -; GFX10-NEXT: s_lshr_b32 s13, s11, 16 -; GFX10-NEXT: s_sub_i32 s10, s10, s11 -; GFX10-NEXT: s_sub_i32 s12, s12, s13 -; GFX10-NEXT: s_cmp_lt_i32 s7, s9 -; GFX10-NEXT: s_sext_i32_i16 s16, s3 -; GFX10-NEXT: s_cselect_b32 s7, s7, s9 -; GFX10-NEXT: s_cmp_lt_i32 s8, s6 +; GFX10-NEXT: v_pk_sub_i16 v0, s0, s3 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, s1, s4 clamp +; GFX10-NEXT: v_pk_sub_i16 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s8, s8, s6 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s10, s12 -; GFX10-NEXT: s_lshr_b32 s10, s7, 16 -; GFX10-NEXT: s_lshr_b32 s12, s14, 16 -; GFX10-NEXT: s_sext_i32_i16 s15, s8 -; GFX10-NEXT: s_sub_i32 s7, s7, s14 -; GFX10-NEXT: s_sub_i32 s10, s10, s12 -; GFX10-NEXT: s_ashr_i32 s8, s8, 16 -; GFX10-NEXT: s_cmp_gt_i32 s15, s16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s10 -; GFX10-NEXT: s_cselect_b32 s15, s15, s16 -; GFX10-NEXT: s_cmp_gt_i32 s8, s3 -; GFX10-NEXT: s_sext_i32_i16 s10, s7 -; GFX10-NEXT: s_cselect_b32 s3, s8, s3 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s15, s3 -; GFX10-NEXT: s_sext_i32_i16 s16, s4 -; GFX10-NEXT: s_sext_i32_i16 s8, s3 -; GFX10-NEXT: s_ashr_i32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_i32 s8, s10 -; GFX10-NEXT: s_cselect_b32 s8, s8, s10 -; GFX10-NEXT: s_cmp_lt_i32 s3, s7 -; GFX10-NEXT: s_cselect_b32 s3, s3, s7 -; GFX10-NEXT: s_lshr_b32 s7, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s8, s3 -; GFX10-NEXT: s_lshr_b32 s8, s3, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s3 -; GFX10-NEXT: s_sub_i32 s3, s7, s8 -; GFX10-NEXT: s_sext_i32_i16 s7, s1 -; GFX10-NEXT: s_ashr_i32 s8, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3 -; GFX10-NEXT: s_cselect_b32 s10, s7, s9 -; GFX10-NEXT: s_cmp_gt_i32 s8, s6 -; GFX10-NEXT: s_cselect_b32 s15, s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s10, s15 -; GFX10-NEXT: s_lshr_b32 s15, s10, 16 -; GFX10-NEXT: s_sub_i32 s10, s10, s11 -; GFX10-NEXT: s_sub_i32 s15, s15, s13 -; GFX10-NEXT: s_cmp_lt_i32 s7, s9 -; GFX10-NEXT: s_cselect_b32 s7, s7, s9 -; GFX10-NEXT: s_cmp_lt_i32 s8, s6 -; GFX10-NEXT: s_cselect_b32 s8, s8, s6 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s10, s15 -; GFX10-NEXT: s_lshr_b32 s10, s7, 16 -; GFX10-NEXT: s_sext_i32_i16 s15, s8 -; GFX10-NEXT: s_sub_i32 s7, s7, s14 -; GFX10-NEXT: s_sub_i32 s10, s10, s12 -; GFX10-NEXT: s_ashr_i32 s8, s8, 16 -; GFX10-NEXT: s_cmp_gt_i32 s15, s16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s10 -; GFX10-NEXT: s_cselect_b32 s15, s15, s16 -; GFX10-NEXT: s_cmp_gt_i32 s8, s4 -; GFX10-NEXT: s_sext_i32_i16 s10, s7 -; GFX10-NEXT: s_cselect_b32 s4, s8, s4 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s15, s4 -; GFX10-NEXT: s_sext_i32_i16 s8, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_i32 s8, s10 -; GFX10-NEXT: s_cselect_b32 s8, s8, s10 -; GFX10-NEXT: s_cmp_lt_i32 s4, s7 -; GFX10-NEXT: s_cselect_b32 s4, s4, s7 -; GFX10-NEXT: s_lshr_b32 s7, s1, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s4 -; GFX10-NEXT: s_lshr_b32 s8, s4, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s4 -; GFX10-NEXT: s_sub_i32 s4, s7, s8 -; GFX10-NEXT: s_sext_i32_i16 s7, s2 -; GFX10-NEXT: s_ashr_i32 s8, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s7, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX10-NEXT: s_cselect_b32 s10, s7, s9 -; GFX10-NEXT: s_cmp_gt_i32 s8, s6 -; GFX10-NEXT: s_cselect_b32 s15, s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s10, s15 -; GFX10-NEXT: s_lshr_b32 s15, s10, 16 -; GFX10-NEXT: s_sub_i32 s10, s10, s11 -; GFX10-NEXT: s_sub_i32 s11, s15, s13 -; GFX10-NEXT: s_cmp_lt_i32 s7, s9 -; GFX10-NEXT: s_cselect_b32 s7, s7, s9 -; GFX10-NEXT: s_cmp_lt_i32 s8, s6 -; GFX10-NEXT: s_cselect_b32 s6, s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s7, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s10, s11 -; GFX10-NEXT: s_lshr_b32 s8, s6, 16 -; GFX10-NEXT: s_sext_i32_i16 s9, s7 -; GFX10-NEXT: s_sext_i32_i16 s10, s5 -; GFX10-NEXT: s_sub_i32 s6, s6, s14 -; GFX10-NEXT: s_sub_i32 s8, s8, s12 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8 -; GFX10-NEXT: s_cselect_b32 s9, s9, s10 -; GFX10-NEXT: s_cmp_gt_i32 s7, s5 -; GFX10-NEXT: s_sext_i32_i16 s8, s6 -; GFX10-NEXT: s_cselect_b32 s5, s7, s5 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s9, s5 -; GFX10-NEXT: s_sext_i32_i16 s7, s5 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_i32 s7, s8 -; GFX10-NEXT: s_cselect_b32 s7, s7, s8 -; GFX10-NEXT: s_cmp_lt_i32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s5, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s7, s5 -; GFX10-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-NEXT: s_lshr_b32 s6, s3, 16 -; GFX10-NEXT: s_sub_i32 s2, s2, s3 -; GFX10-NEXT: s_sub_i32 s3, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x i32> @@ -5448,79 +3551,21 @@ ; GFX9-LABEL: v_ssubsat_v8i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_movk_i32 s4, 0x7fff -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_mov_b32 s5, 0xffff8000 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s4 -; GFX9-NEXT: v_pk_max_i16 v8, v0, s6 -; GFX9-NEXT: v_pk_sub_i16 v8, v8, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX9-NEXT: v_pk_min_i16 v9, v0, s6 -; GFX9-NEXT: v_pk_max_i16 v4, v8, v4 -; GFX9-NEXT: v_pk_sub_i16 v9, v9, s5 -; GFX9-NEXT: v_pk_min_i16 v4, v4, v9 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v1, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s4 -; GFX9-NEXT: v_pk_min_i16 v8, v1, s6 -; GFX9-NEXT: v_pk_max_i16 v4, v4, v5 -; GFX9-NEXT: v_pk_sub_i16 v8, v8, s5 -; GFX9-NEXT: v_pk_min_i16 v4, v4, v8 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s4 -; GFX9-NEXT: v_pk_min_i16 v5, v2, s6 -; GFX9-NEXT: v_pk_sub_i16 v5, v5, s5 -; GFX9-NEXT: v_pk_max_i16 v4, v4, v6 -; GFX9-NEXT: v_pk_min_i16 v4, v4, v5 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, v4 -; GFX9-NEXT: v_pk_max_i16 v4, v3, s6 -; GFX9-NEXT: v_pk_sub_i16 v4, v4, s4 -; GFX9-NEXT: v_pk_min_i16 v5, v3, s6 -; GFX9-NEXT: v_pk_sub_i16 v5, v5, s5 -; GFX9-NEXT: v_pk_max_i16 v4, v4, v7 -; GFX9-NEXT: v_pk_min_i16 v4, v4, v5 -; GFX9-NEXT: v_pk_sub_i16 v3, v3, v4 +; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, v1, v5 clamp +; GFX9-NEXT: v_pk_sub_i16 v2, v2, v6 clamp +; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_ssubsat_v8i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX10-NEXT: s_movk_i32 s5, 0x7fff -; GFX10-NEXT: v_pk_max_i16 v8, v0, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s5 -; GFX10-NEXT: v_pk_max_i16 v10, v1, s4 -; GFX10-NEXT: v_pk_max_i16 v12, v3, s4 -; GFX10-NEXT: v_pk_min_i16 v9, v0, s4 -; GFX10-NEXT: v_pk_sub_i16 v15, v8, s5 -; GFX10-NEXT: v_pk_max_i16 v8, v2, s4 -; GFX10-NEXT: v_pk_sub_i16 v10, v10, s5 -; GFX10-NEXT: v_pk_sub_i16 v12, v12, s5 -; GFX10-NEXT: v_pk_min_i16 v11, v1, s4 -; GFX10-NEXT: v_pk_min_i16 v13, v2, s4 -; GFX10-NEXT: v_pk_sub_i16 v8, v8, s5 -; GFX10-NEXT: v_pk_min_i16 v14, v3, s4 -; GFX10-NEXT: s_mov_b32 s6, 0xffff8000 -; GFX10-NEXT: v_pk_max_i16 v4, v15, v4 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s6 -; GFX10-NEXT: v_pk_max_i16 v5, v10, v5 -; GFX10-NEXT: v_pk_sub_i16 v11, v11, s6 -; GFX10-NEXT: v_pk_sub_i16 v9, v9, s6 -; GFX10-NEXT: v_pk_max_i16 v15, v8, v6 -; GFX10-NEXT: v_pk_sub_i16 v10, v13, s6 -; GFX10-NEXT: v_pk_sub_i16 v8, v14, s6 -; GFX10-NEXT: v_pk_max_i16 v7, v12, v7 -; GFX10-NEXT: v_pk_min_i16 v19, v4, v9 -; GFX10-NEXT: v_pk_min_i16 v11, v5, v11 -; GFX10-NEXT: v_pk_min_i16 v15, v15, v10 +; GFX10-NEXT: v_pk_sub_i16 v0, v0, v4 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, v1, v5 clamp +; GFX10-NEXT: v_pk_sub_i16 v2, v2, v6 clamp +; GFX10-NEXT: v_pk_sub_i16 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_min_i16 v6, v7, v8 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v19 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v11 -; GFX10-NEXT: v_pk_sub_i16 v2, v2, v15 -; GFX10-NEXT: v_pk_sub_i16 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x float> @@ -5824,373 +3869,31 @@ ; ; GFX9-LABEL: s_ssubsat_v8i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s10, -1, -1 -; GFX9-NEXT: s_sext_i32_i16 s13, s10 -; GFX9-NEXT: s_sext_i32_i16 s11, s0 -; GFX9-NEXT: s_ashr_i32 s12, s0, 16 -; GFX9-NEXT: s_ashr_i32 s10, s10, 16 -; GFX9-NEXT: s_cmp_gt_i32 s11, s13 -; GFX9-NEXT: s_cselect_b32 s14, s11, s13 -; GFX9-NEXT: s_cmp_gt_i32 s12, s10 -; GFX9-NEXT: s_movk_i32 s8, 0x7fff -; GFX9-NEXT: s_cselect_b32 s15, s12, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s8 -; GFX9-NEXT: s_lshr_b32 s15, s14, 16 -; GFX9-NEXT: s_lshr_b32 s16, s8, 16 -; GFX9-NEXT: s_sub_i32 s14, s14, s8 -; GFX9-NEXT: s_sub_i32 s15, s15, s16 -; GFX9-NEXT: s_cmp_lt_i32 s11, s13 -; GFX9-NEXT: s_cselect_b32 s11, s11, s13 -; GFX9-NEXT: s_cmp_lt_i32 s12, s10 -; GFX9-NEXT: s_mov_b32 s9, 0xffff8000 -; GFX9-NEXT: s_cselect_b32 s12, s12, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s15 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s15, s9, 16 -; GFX9-NEXT: s_sub_i32 s11, s11, s9 -; GFX9-NEXT: s_sub_i32 s12, s12, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 -; GFX9-NEXT: s_sext_i32_i16 s12, s14 -; GFX9-NEXT: s_sext_i32_i16 s17, s4 -; GFX9-NEXT: s_ashr_i32 s14, s14, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_gt_i32 s12, s17 -; GFX9-NEXT: s_cselect_b32 s12, s12, s17 -; GFX9-NEXT: s_cmp_gt_i32 s14, s4 -; GFX9-NEXT: s_cselect_b32 s4, s14, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX9-NEXT: s_sext_i32_i16 s12, s4 -; GFX9-NEXT: s_sext_i32_i16 s14, s11 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_ashr_i32 s11, s11, 16 -; GFX9-NEXT: s_cmp_lt_i32 s12, s14 -; GFX9-NEXT: s_cselect_b32 s12, s12, s14 -; GFX9-NEXT: s_cmp_lt_i32 s4, s11 -; GFX9-NEXT: s_cselect_b32 s4, s4, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s12, s4 -; GFX9-NEXT: s_lshr_b32 s11, s0, 16 -; GFX9-NEXT: s_lshr_b32 s12, s4, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s4 -; GFX9-NEXT: s_sub_i32 s4, s11, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s1 -; GFX9-NEXT: s_ashr_i32 s11, s1, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s12, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s11, s10 -; GFX9-NEXT: s_cselect_b32 s14, s11, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX9-NEXT: s_lshr_b32 s14, s12, 16 -; GFX9-NEXT: s_sub_i32 s12, s12, s8 -; GFX9-NEXT: s_sub_i32 s14, s14, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s11, s10 -; GFX9-NEXT: s_cselect_b32 s11, s11, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s11 -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s14 -; GFX9-NEXT: s_sub_i32 s4, s4, s9 -; GFX9-NEXT: s_sub_i32 s11, s11, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s11 -; GFX9-NEXT: s_sext_i32_i16 s11, s12 -; GFX9-NEXT: s_sext_i32_i16 s14, s5 -; GFX9-NEXT: s_ashr_i32 s12, s12, 16 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_cmp_gt_i32 s11, s14 -; GFX9-NEXT: s_cselect_b32 s11, s11, s14 -; GFX9-NEXT: s_cmp_gt_i32 s12, s5 -; GFX9-NEXT: s_cselect_b32 s5, s12, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s11, s5 -; GFX9-NEXT: s_sext_i32_i16 s11, s5 -; GFX9-NEXT: s_sext_i32_i16 s12, s4 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_lt_i32 s11, s12 -; GFX9-NEXT: s_cselect_b32 s11, s11, s12 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s11, s4 -; GFX9-NEXT: s_lshr_b32 s5, s1, 16 -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s4 -; GFX9-NEXT: s_sub_i32 s4, s5, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s2 -; GFX9-NEXT: s_ashr_i32 s5, s2, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s11, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s12, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_sub_i32 s11, s11, s8 -; GFX9-NEXT: s_sub_i32 s12, s12, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s5, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 -; GFX9-NEXT: s_sub_i32 s4, s4, s9 -; GFX9-NEXT: s_sub_i32 s5, s5, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_sext_i32_i16 s5, s11 -; GFX9-NEXT: s_sext_i32_i16 s12, s6 -; GFX9-NEXT: s_ashr_i32 s11, s11, 16 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s12 -; GFX9-NEXT: s_cselect_b32 s5, s5, s12 -; GFX9-NEXT: s_cmp_gt_i32 s11, s6 -; GFX9-NEXT: s_cselect_b32 s6, s11, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX9-NEXT: s_sext_i32_i16 s6, s5 -; GFX9-NEXT: s_sext_i32_i16 s11, s4 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_lt_i32 s6, s11 -; GFX9-NEXT: s_cselect_b32 s6, s6, s11 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s4 -; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_sub_i32 s4, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 -; GFX9-NEXT: s_sext_i32_i16 s4, s3 -; GFX9-NEXT: s_ashr_i32 s5, s3, 16 -; GFX9-NEXT: s_cmp_gt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s6, s4, s13 -; GFX9-NEXT: s_cmp_gt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s11, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s11 -; GFX9-NEXT: s_lshr_b32 s11, s6, 16 -; GFX9-NEXT: s_sub_i32 s6, s6, s8 -; GFX9-NEXT: s_sub_i32 s8, s11, s16 -; GFX9-NEXT: s_cmp_lt_i32 s4, s13 -; GFX9-NEXT: s_cselect_b32 s4, s4, s13 -; GFX9-NEXT: s_cmp_lt_i32 s5, s10 -; GFX9-NEXT: s_cselect_b32 s5, s5, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8 -; GFX9-NEXT: s_sub_i32 s4, s4, s9 -; GFX9-NEXT: s_sub_i32 s5, s5, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_sext_i32_i16 s5, s6 -; GFX9-NEXT: s_sext_i32_i16 s8, s7 -; GFX9-NEXT: s_ashr_i32 s6, s6, 16 -; GFX9-NEXT: s_ashr_i32 s7, s7, 16 -; GFX9-NEXT: s_cmp_gt_i32 s5, s8 -; GFX9-NEXT: s_cselect_b32 s5, s5, s8 -; GFX9-NEXT: s_cmp_gt_i32 s6, s7 -; GFX9-NEXT: s_cselect_b32 s6, s6, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX9-NEXT: s_sext_i32_i16 s6, s5 -; GFX9-NEXT: s_sext_i32_i16 s7, s4 -; GFX9-NEXT: s_ashr_i32 s5, s5, 16 -; GFX9-NEXT: s_ashr_i32 s4, s4, 16 -; GFX9-NEXT: s_cmp_lt_i32 s6, s7 -; GFX9-NEXT: s_cselect_b32 s6, s6, s7 -; GFX9-NEXT: s_cmp_lt_i32 s5, s4 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s4 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_sub_i32 s3, s3, s4 -; GFX9-NEXT: s_sub_i32 s4, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp +; GFX9-NEXT: v_pk_sub_i16 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_ssubsat_v8i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s8, -1, -1 -; GFX10-NEXT: s_sext_i32_i16 s9, s0 -; GFX10-NEXT: s_sext_i32_i16 s11, s8 -; GFX10-NEXT: s_ashr_i32 s10, s0, 16 -; GFX10-NEXT: s_ashr_i32 s8, s8, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s11 -; GFX10-NEXT: s_movk_i32 s14, 0x7fff -; GFX10-NEXT: s_cselect_b32 s12, s9, s11 -; GFX10-NEXT: s_cmp_gt_i32 s10, s8 -; GFX10-NEXT: s_mov_b32 s16, 0xffff8000 -; GFX10-NEXT: s_cselect_b32 s13, s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s16, s16, s16 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s13 -; GFX10-NEXT: s_pack_ll_b32_b16 s13, s14, s14 -; GFX10-NEXT: s_lshr_b32 s14, s12, 16 -; GFX10-NEXT: s_lshr_b32 s15, s13, 16 -; GFX10-NEXT: s_sub_i32 s12, s12, s13 -; GFX10-NEXT: s_sub_i32 s14, s14, s15 -; GFX10-NEXT: s_cmp_lt_i32 s9, s11 -; GFX10-NEXT: s_sext_i32_i16 s18, s4 -; GFX10-NEXT: s_cselect_b32 s9, s9, s11 -; GFX10-NEXT: s_cmp_lt_i32 s10, s8 +; GFX10-NEXT: v_pk_sub_i16 v0, s0, s4 clamp +; GFX10-NEXT: v_pk_sub_i16 v1, s1, s5 clamp +; GFX10-NEXT: v_pk_sub_i16 v2, s2, s6 clamp +; GFX10-NEXT: v_pk_sub_i16 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s10, s10, s8 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s12, s14 -; GFX10-NEXT: s_lshr_b32 s12, s9, 16 -; GFX10-NEXT: s_lshr_b32 s14, s16, 16 -; GFX10-NEXT: s_sext_i32_i16 s17, s10 -; GFX10-NEXT: s_sub_i32 s9, s9, s16 -; GFX10-NEXT: s_sub_i32 s12, s12, s14 -; GFX10-NEXT: s_ashr_i32 s10, s10, 16 -; GFX10-NEXT: s_cmp_gt_i32 s17, s18 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s12 -; GFX10-NEXT: s_cselect_b32 s17, s17, s18 -; GFX10-NEXT: s_cmp_gt_i32 s10, s4 -; GFX10-NEXT: s_sext_i32_i16 s12, s9 -; GFX10-NEXT: s_cselect_b32 s4, s10, s4 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s17, s4 -; GFX10-NEXT: s_sext_i32_i16 s18, s5 -; GFX10-NEXT: s_sext_i32_i16 s10, s4 -; GFX10-NEXT: s_ashr_i32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_i32 s10, s12 -; GFX10-NEXT: s_cselect_b32 s10, s10, s12 -; GFX10-NEXT: s_cmp_lt_i32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s9 -; GFX10-NEXT: s_lshr_b32 s9, s0, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s10, s4 -; GFX10-NEXT: s_lshr_b32 s10, s4, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s4 -; GFX10-NEXT: s_sub_i32 s4, s9, s10 -; GFX10-NEXT: s_sext_i32_i16 s9, s1 -; GFX10-NEXT: s_ashr_i32 s10, s1, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX10-NEXT: s_cselect_b32 s12, s9, s11 -; GFX10-NEXT: s_cmp_gt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s17, s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s17 -; GFX10-NEXT: s_lshr_b32 s17, s12, 16 -; GFX10-NEXT: s_sub_i32 s12, s12, s13 -; GFX10-NEXT: s_sub_i32 s17, s17, s15 -; GFX10-NEXT: s_cmp_lt_i32 s9, s11 -; GFX10-NEXT: s_cselect_b32 s9, s9, s11 -; GFX10-NEXT: s_cmp_lt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s10, s10, s8 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s12, s17 -; GFX10-NEXT: s_lshr_b32 s12, s9, 16 -; GFX10-NEXT: s_sext_i32_i16 s17, s10 -; GFX10-NEXT: s_sub_i32 s9, s9, s16 -; GFX10-NEXT: s_sub_i32 s12, s12, s14 -; GFX10-NEXT: s_ashr_i32 s10, s10, 16 -; GFX10-NEXT: s_cmp_gt_i32 s17, s18 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s12 -; GFX10-NEXT: s_cselect_b32 s17, s17, s18 -; GFX10-NEXT: s_cmp_gt_i32 s10, s5 -; GFX10-NEXT: s_sext_i32_i16 s12, s9 -; GFX10-NEXT: s_cselect_b32 s5, s10, s5 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s17, s5 -; GFX10-NEXT: s_sext_i32_i16 s18, s6 -; GFX10-NEXT: s_sext_i32_i16 s10, s5 -; GFX10-NEXT: s_ashr_i32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_i32 s10, s12 -; GFX10-NEXT: s_cselect_b32 s10, s10, s12 -; GFX10-NEXT: s_cmp_lt_i32 s5, s9 -; GFX10-NEXT: s_cselect_b32 s5, s5, s9 -; GFX10-NEXT: s_lshr_b32 s9, s1, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s10, s5 -; GFX10-NEXT: s_lshr_b32 s10, s5, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s5 -; GFX10-NEXT: s_sub_i32 s5, s9, s10 -; GFX10-NEXT: s_sext_i32_i16 s9, s2 -; GFX10-NEXT: s_ashr_i32 s10, s2, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX10-NEXT: s_cselect_b32 s12, s9, s11 -; GFX10-NEXT: s_cmp_gt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s17, s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s17 -; GFX10-NEXT: s_lshr_b32 s17, s12, 16 -; GFX10-NEXT: s_sub_i32 s12, s12, s13 -; GFX10-NEXT: s_sub_i32 s17, s17, s15 -; GFX10-NEXT: s_cmp_lt_i32 s9, s11 -; GFX10-NEXT: s_cselect_b32 s9, s9, s11 -; GFX10-NEXT: s_cmp_lt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s10, s10, s8 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s10, s12, s17 -; GFX10-NEXT: s_lshr_b32 s12, s9, 16 -; GFX10-NEXT: s_sext_i32_i16 s17, s10 -; GFX10-NEXT: s_sub_i32 s9, s9, s16 -; GFX10-NEXT: s_sub_i32 s12, s12, s14 -; GFX10-NEXT: s_ashr_i32 s10, s10, 16 -; GFX10-NEXT: s_cmp_gt_i32 s17, s18 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s12 -; GFX10-NEXT: s_cselect_b32 s17, s17, s18 -; GFX10-NEXT: s_cmp_gt_i32 s10, s6 -; GFX10-NEXT: s_sext_i32_i16 s12, s9 -; GFX10-NEXT: s_cselect_b32 s6, s10, s6 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s17, s6 -; GFX10-NEXT: s_sext_i32_i16 s10, s6 -; GFX10-NEXT: s_ashr_i32 s6, s6, 16 -; GFX10-NEXT: s_cmp_lt_i32 s10, s12 -; GFX10-NEXT: s_cselect_b32 s10, s10, s12 -; GFX10-NEXT: s_cmp_lt_i32 s6, s9 -; GFX10-NEXT: s_cselect_b32 s6, s6, s9 -; GFX10-NEXT: s_lshr_b32 s9, s2, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s10, s6 -; GFX10-NEXT: s_lshr_b32 s10, s6, 16 -; GFX10-NEXT: s_sub_i32 s2, s2, s6 -; GFX10-NEXT: s_sub_i32 s6, s9, s10 -; GFX10-NEXT: s_sext_i32_i16 s9, s3 -; GFX10-NEXT: s_ashr_i32 s10, s3, 16 -; GFX10-NEXT: s_cmp_gt_i32 s9, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX10-NEXT: s_cselect_b32 s12, s9, s11 -; GFX10-NEXT: s_cmp_gt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s17, s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s17 -; GFX10-NEXT: s_lshr_b32 s17, s12, 16 -; GFX10-NEXT: s_sub_i32 s12, s12, s13 -; GFX10-NEXT: s_sub_i32 s13, s17, s15 -; GFX10-NEXT: s_cmp_lt_i32 s9, s11 -; GFX10-NEXT: s_cselect_b32 s9, s9, s11 -; GFX10-NEXT: s_cmp_lt_i32 s10, s8 -; GFX10-NEXT: s_cselect_b32 s8, s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s9, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s9, s12, s13 -; GFX10-NEXT: s_lshr_b32 s10, s8, 16 -; GFX10-NEXT: s_sext_i32_i16 s11, s9 -; GFX10-NEXT: s_sext_i32_i16 s12, s7 -; GFX10-NEXT: s_sub_i32 s8, s8, s16 -; GFX10-NEXT: s_sub_i32 s10, s10, s14 -; GFX10-NEXT: s_ashr_i32 s9, s9, 16 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_cmp_gt_i32 s11, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10 -; GFX10-NEXT: s_cselect_b32 s11, s11, s12 -; GFX10-NEXT: s_cmp_gt_i32 s9, s7 -; GFX10-NEXT: s_sext_i32_i16 s10, s8 -; GFX10-NEXT: s_cselect_b32 s7, s9, s7 -; GFX10-NEXT: s_ashr_i32 s8, s8, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s7, s11, s7 -; GFX10-NEXT: s_sext_i32_i16 s9, s7 -; GFX10-NEXT: s_ashr_i32 s7, s7, 16 -; GFX10-NEXT: s_cmp_lt_i32 s9, s10 -; GFX10-NEXT: s_cselect_b32 s9, s9, s10 -; GFX10-NEXT: s_cmp_lt_i32 s7, s8 -; GFX10-NEXT: s_cselect_b32 s4, s7, s8 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s9, s4 -; GFX10-NEXT: s_lshr_b32 s7, s4, 16 -; GFX10-NEXT: s_sub_i32 s3, s3, s4 -; GFX10-NEXT: s_sub_i32 s4, s5, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x i32> Index: llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll @@ -21,9 +21,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX8-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -32,9 +30,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX9-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -45,9 +41,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX10-NEXT: v_min_u16_e64 v1, v2, v1 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs) @@ -69,31 +63,23 @@ ; GFX8-LABEL: s_uaddsat_i7: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 -; GFX8-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s1 -; GFX8-NEXT: s_cselect_b32 s1, s3, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshr_b32 s0, s0, s2 +; GFX8-NEXT: s_lshl_b32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_i7: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX9-NEXT: s_lshr_b32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_i7: @@ -102,14 +88,9 @@ ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX10-NEXT: s_cmp_lt_u32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX10-NEXT: s_lshr_b32 s0, s0, s2 +; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs) ret i7 %result @@ -132,9 +113,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX8-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -143,9 +122,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX9-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -156,9 +133,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX10-NEXT: v_min_u16_e64 v1, v2, v1 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs) @@ -180,31 +155,23 @@ ; GFX8-LABEL: s_uaddsat_i8: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX8-NEXT: s_lshl_b32 s0, s0, s2 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 -; GFX8-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s1 -; GFX8-NEXT: s_cselect_b32 s1, s3, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshr_b32 s0, s0, s2 +; GFX8-NEXT: s_lshl_b32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_i8: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 -; GFX9-NEXT: s_lshl_b32 s0, s0, s2 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 -; GFX9-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX9-NEXT: s_lshr_b32 s0, s0, s2 +; GFX9-NEXT: s_lshl_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_i8: @@ -213,14 +180,9 @@ ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 ; GFX10-NEXT: s_lshl_b32 s1, s1, s2 -; GFX10-NEXT: s_xor_b32 s3, s0, 0xffff -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX10-NEXT: s_cmp_lt_u32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX10-NEXT: s_lshr_b32 s0, s0, s2 +; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs) ret i8 %result @@ -243,9 +205,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -254,9 +214,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -267,9 +225,7 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0 -; GFX10-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs) @@ -290,36 +246,32 @@ ; ; GFX8-LABEL: s_uaddsat_i24: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshl_b32 s0, s0, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8 -; GFX8-NEXT: s_not_b32 s2, s0 -; GFX8-NEXT: s_cmp_lt_u32 s2, s1 -; GFX8-NEXT: s_cselect_b32 s1, s2, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 -; GFX8-NEXT: s_lshr_b32 s0, s0, 8 +; GFX8-NEXT: s_lshl_b32 s0, s0, 8 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_i24: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshl_b32 s0, s0, 8 ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 -; GFX9-NEXT: s_not_b32 s2, s0 -; GFX9-NEXT: s_cmp_lt_u32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_lshr_b32 s0, s0, 8 +; GFX9-NEXT: s_lshl_b32 s0, s0, 8 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_i24: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_lshl_b32 s0, s0, 8 ; GFX10-NEXT: s_lshl_b32 s1, s1, 8 -; GFX10-NEXT: s_not_b32 s2, s0 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs) ret i24 %result @@ -337,27 +289,21 @@ ; GFX8-LABEL: v_uaddsat_i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v1, v2, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -374,27 +320,23 @@ ; ; GFX8-LABEL: s_uaddsat_i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s2, s0 -; GFX8-NEXT: s_cmp_lt_u32 s2, s1 -; GFX8-NEXT: s_cselect_b32 s1, s2, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s2, s0 -; GFX9-NEXT: s_cmp_lt_u32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_add_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s2, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -410,24 +352,18 @@ ; ; GFX8-LABEL: uaddsat_i32_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s1, s0 -; GFX8-NEXT: v_min_u32_e32 v0, s1, v0 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_i32_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s1, s0 -; GFX9-NEXT: v_min_u32_e32 v0, s1, v0 -; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_i32_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s1, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v0, s1, v0 -; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -444,24 +380,18 @@ ; ; GFX8-LABEL: uaddsat_i32_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v1, s0, v1 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], v0, s0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_i32_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_xor_b32_e32 v1, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v1, s0, v1 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u32_e64 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_i32_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v1, s0, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -483,36 +413,24 @@ ; GFX8-LABEL: v_uaddsat_v2i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v4, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v2, v4, v2 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 -; GFX8-NEXT: v_xor_b32_e32 v2, -1, v1 -; GFX8-NEXT: v_min_u32_e32 v2, v2, v3 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v2 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v3 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v2i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v4, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v2, v4, v2 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 -; GFX9-NEXT: v_xor_b32_e32 v2, -1, v1 -; GFX9-NEXT: v_min_u32_e32 v2, v2, v3 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v2 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v2i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v4, -1, v0 -; GFX10-NEXT: v_xor_b32_e32 v5, -1, v1 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v2 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v2, v4, v2 -; GFX10-NEXT: v_min_u32_e32 v3, v5, v3 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -533,39 +451,31 @@ ; ; GFX8-LABEL: s_uaddsat_v2i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s4, s0 -; GFX8-NEXT: s_cmp_lt_u32 s4, s2 -; GFX8-NEXT: s_cselect_b32 s2, s4, s2 -; GFX8-NEXT: s_add_i32 s0, s0, s2 -; GFX8-NEXT: s_not_b32 s2, s1 -; GFX8-NEXT: s_cmp_lt_u32 s2, s3 -; GFX8-NEXT: s_cselect_b32 s2, s2, s3 -; GFX8-NEXT: s_add_i32 s1, s1, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], s0, v0 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v2i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s4, s0 -; GFX9-NEXT: s_cmp_lt_u32 s4, s2 -; GFX9-NEXT: s_cselect_b32 s2, s4, s2 -; GFX9-NEXT: s_add_i32 s0, s0, s2 -; GFX9-NEXT: s_not_b32 s2, s1 -; GFX9-NEXT: s_cmp_lt_u32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_add_i32 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v2i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s4, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s2 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s4, s2 -; GFX10-NEXT: s_cselect_b32 s2, s4, s2 -; GFX10-NEXT: s_not_b32 s4, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s2 -; GFX10-NEXT: s_cmp_lt_u32 s4, s3 -; GFX10-NEXT: s_cselect_b32 s2, s4, s3 -; GFX10-NEXT: s_add_i32 s1, s1, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -589,45 +499,27 @@ ; GFX8-LABEL: v_uaddsat_v3i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v6, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v3, v6, v3 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3 -; GFX8-NEXT: v_xor_b32_e32 v3, -1, v1 -; GFX8-NEXT: v_min_u32_e32 v3, v3, v4 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 -; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2 -; GFX8-NEXT: v_min_u32_e32 v3, v3, v5 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v3 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v4 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v5 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v3i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v6, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v3, v6, v3 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v3 -; GFX9-NEXT: v_xor_b32_e32 v3, -1, v1 -; GFX9-NEXT: v_min_u32_e32 v3, v3, v4 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_xor_b32_e32 v3, -1, v2 -; GFX9-NEXT: v_min_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v3 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v4 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v3i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v6, -1, v0 -; GFX10-NEXT: v_xor_b32_e32 v7, -1, v1 -; GFX10-NEXT: v_xor_b32_e32 v8, -1, v2 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v3 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v4 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v3, v6, v3 -; GFX10-NEXT: v_min_u32_e32 v4, v7, v4 -; GFX10-NEXT: v_min_u32_e32 v5, v8, v5 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v4 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -652,51 +544,39 @@ ; ; GFX8-LABEL: s_uaddsat_v3i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s6, s0 -; GFX8-NEXT: s_cmp_lt_u32 s6, s3 -; GFX8-NEXT: s_cselect_b32 s3, s6, s3 -; GFX8-NEXT: s_add_i32 s0, s0, s3 -; GFX8-NEXT: s_not_b32 s3, s1 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_add_i32 s1, s1, s3 -; GFX8-NEXT: s_not_b32 s3, s2 -; GFX8-NEXT: s_cmp_lt_u32 s3, s5 -; GFX8-NEXT: s_cselect_b32 s3, s3, s5 -; GFX8-NEXT: s_add_i32 s2, s2, s3 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_add_u32_e64 v0, s[6:7], s0, v0 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v3i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s6, s0 -; GFX9-NEXT: s_cmp_lt_u32 s6, s3 -; GFX9-NEXT: s_cselect_b32 s3, s6, s3 -; GFX9-NEXT: s_add_i32 s0, s0, s3 -; GFX9-NEXT: s_not_b32 s3, s1 -; GFX9-NEXT: s_cmp_lt_u32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_add_i32 s1, s1, s3 -; GFX9-NEXT: s_not_b32 s3, s2 -; GFX9-NEXT: s_cmp_lt_u32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s3, s3, s5 -; GFX9-NEXT: s_add_i32 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v3i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s6, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s3 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s4 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s6, s3 -; GFX10-NEXT: s_cselect_b32 s3, s6, s3 -; GFX10-NEXT: s_not_b32 s6, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s3 -; GFX10-NEXT: s_cmp_lt_u32 s6, s4 -; GFX10-NEXT: s_cselect_b32 s3, s6, s4 -; GFX10-NEXT: s_not_b32 s4, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s3 -; GFX10-NEXT: s_cmp_lt_u32 s4, s5 -; GFX10-NEXT: s_cselect_b32 s3, s4, s5 -; GFX10-NEXT: s_add_i32 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -723,54 +603,30 @@ ; GFX8-LABEL: v_uaddsat_v4i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v8, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v4, v8, v4 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4 -; GFX8-NEXT: v_xor_b32_e32 v4, -1, v1 -; GFX8-NEXT: v_min_u32_e32 v4, v4, v5 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4 -; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2 -; GFX8-NEXT: v_min_u32_e32 v4, v4, v6 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 -; GFX8-NEXT: v_xor_b32_e32 v4, -1, v3 -; GFX8-NEXT: v_min_u32_e32 v4, v4, v7 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v4 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v5 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v6 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v7 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v4i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v8, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v4, v8, v4 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, -1, v1 -; GFX9-NEXT: v_min_u32_e32 v4, v4, v5 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, -1, v2 -; GFX9-NEXT: v_min_u32_e32 v4, v4, v6 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, -1, v3 -; GFX9-NEXT: v_min_u32_e32 v4, v4, v7 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v4 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v4 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v5 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v6 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v4i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v15, -1, v0 -; GFX10-NEXT: v_xor_b32_e32 v19, -1, v1 -; GFX10-NEXT: v_xor_b32_e32 v23, -1, v2 -; GFX10-NEXT: v_xor_b32_e32 v10, -1, v3 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v4 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v5 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v6 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v11, v15, v4 -; GFX10-NEXT: v_min_u32_e32 v15, v19, v5 -; GFX10-NEXT: v_min_u32_e32 v19, v23, v6 -; GFX10-NEXT: v_min_u32_e32 v6, v10, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v11 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v15 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v19 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -799,63 +655,47 @@ ; ; GFX8-LABEL: s_uaddsat_v4i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s8, s0 -; GFX8-NEXT: s_cmp_lt_u32 s8, s4 -; GFX8-NEXT: s_cselect_b32 s4, s8, s4 -; GFX8-NEXT: s_add_i32 s0, s0, s4 -; GFX8-NEXT: s_not_b32 s4, s1 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s1, s1, s4 -; GFX8-NEXT: s_not_b32 s4, s2 -; GFX8-NEXT: s_cmp_lt_u32 s4, s6 -; GFX8-NEXT: s_cselect_b32 s4, s4, s6 -; GFX8-NEXT: s_add_i32 s2, s2, s4 -; GFX8-NEXT: s_not_b32 s4, s3 -; GFX8-NEXT: s_cmp_lt_u32 s4, s7 -; GFX8-NEXT: s_cselect_b32 s4, s4, s7 -; GFX8-NEXT: s_add_i32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_add_u32_e64 v0, s[8:9], s0, v0 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], s3, v3 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v4i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s8, s0 -; GFX9-NEXT: s_cmp_lt_u32 s8, s4 -; GFX9-NEXT: s_cselect_b32 s4, s8, s4 -; GFX9-NEXT: s_add_i32 s0, s0, s4 -; GFX9-NEXT: s_not_b32 s4, s1 -; GFX9-NEXT: s_cmp_lt_u32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_add_i32 s1, s1, s4 -; GFX9-NEXT: s_not_b32 s4, s2 -; GFX9-NEXT: s_cmp_lt_u32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_add_i32 s2, s2, s4 -; GFX9-NEXT: s_not_b32 s4, s3 -; GFX9-NEXT: s_cmp_lt_u32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_add_i32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v4i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s8, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s4 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s5 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s6 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s8, s4 -; GFX10-NEXT: s_cselect_b32 s4, s8, s4 -; GFX10-NEXT: s_not_b32 s8, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s4 -; GFX10-NEXT: s_cmp_lt_u32 s8, s5 -; GFX10-NEXT: s_cselect_b32 s4, s8, s5 -; GFX10-NEXT: s_not_b32 s5, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s4 -; GFX10-NEXT: s_cmp_lt_u32 s5, s6 -; GFX10-NEXT: s_cselect_b32 s4, s5, s6 -; GFX10-NEXT: s_not_b32 s5, s3 -; GFX10-NEXT: s_add_i32 s2, s2, s4 -; GFX10-NEXT: s_cmp_lt_u32 s5, s7 -; GFX10-NEXT: s_cselect_b32 s4, s5, s7 -; GFX10-NEXT: s_add_i32 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -885,62 +725,32 @@ ; GFX8-LABEL: v_uaddsat_v5i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v10, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v5, v10, v5 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5 -; GFX8-NEXT: v_xor_b32_e32 v5, -1, v1 -; GFX8-NEXT: v_min_u32_e32 v5, v5, v6 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5 -; GFX8-NEXT: v_xor_b32_e32 v5, -1, v2 -; GFX8-NEXT: v_min_u32_e32 v5, v5, v7 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5 -; GFX8-NEXT: v_xor_b32_e32 v5, -1, v3 -; GFX8-NEXT: v_min_u32_e32 v5, v5, v8 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 -; GFX8-NEXT: v_xor_b32_e32 v5, -1, v4 -; GFX8-NEXT: v_min_u32_e32 v5, v5, v9 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v5 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v6 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v7 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v8 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v9 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v5i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v10, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v5, v10, v5 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v5 -; GFX9-NEXT: v_xor_b32_e32 v5, -1, v1 -; GFX9-NEXT: v_min_u32_e32 v5, v5, v6 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v5 -; GFX9-NEXT: v_xor_b32_e32 v5, -1, v2 -; GFX9-NEXT: v_min_u32_e32 v5, v5, v7 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_xor_b32_e32 v5, -1, v3 -; GFX9-NEXT: v_min_u32_e32 v5, v5, v8 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_xor_b32_e32 v5, -1, v4 -; GFX9-NEXT: v_min_u32_e32 v5, v5, v9 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v5 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v5 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v6 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v7 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v8 clamp +; GFX9-NEXT: v_add_u32_e64 v4, v4, v9 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v5i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v10, -1, v0 -; GFX10-NEXT: v_xor_b32_e32 v11, -1, v1 -; GFX10-NEXT: v_xor_b32_e32 v12, -1, v2 -; GFX10-NEXT: v_xor_b32_e32 v13, -1, v3 -; GFX10-NEXT: v_xor_b32_e32 v14, -1, v4 -; GFX10-NEXT: v_min_u32_e32 v5, v10, v5 -; GFX10-NEXT: v_min_u32_e32 v6, v11, v6 -; GFX10-NEXT: v_min_u32_e32 v7, v12, v7 -; GFX10-NEXT: v_min_u32_e32 v8, v13, v8 -; GFX10-NEXT: v_min_u32_e32 v9, v14, v9 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v5 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v6 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v8 -; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v9 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v5 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v6 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v7 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v8 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v9 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) @@ -974,75 +784,55 @@ ; ; GFX8-LABEL: s_uaddsat_v5i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s10, s0 -; GFX8-NEXT: s_cmp_lt_u32 s10, s5 -; GFX8-NEXT: s_cselect_b32 s5, s10, s5 -; GFX8-NEXT: s_add_i32 s0, s0, s5 -; GFX8-NEXT: s_not_b32 s5, s1 -; GFX8-NEXT: s_cmp_lt_u32 s5, s6 -; GFX8-NEXT: s_cselect_b32 s5, s5, s6 -; GFX8-NEXT: s_add_i32 s1, s1, s5 -; GFX8-NEXT: s_not_b32 s5, s2 -; GFX8-NEXT: s_cmp_lt_u32 s5, s7 -; GFX8-NEXT: s_cselect_b32 s5, s5, s7 -; GFX8-NEXT: s_add_i32 s2, s2, s5 -; GFX8-NEXT: s_not_b32 s5, s3 -; GFX8-NEXT: s_cmp_lt_u32 s5, s8 -; GFX8-NEXT: s_cselect_b32 s5, s5, s8 -; GFX8-NEXT: s_add_i32 s3, s3, s5 -; GFX8-NEXT: s_not_b32 s5, s4 -; GFX8-NEXT: s_cmp_lt_u32 s5, s9 -; GFX8-NEXT: s_cselect_b32 s5, s5, s9 -; GFX8-NEXT: s_add_i32 s4, s4, s5 +; GFX8-NEXT: v_mov_b32_e32 v0, s5 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: v_mov_b32_e32 v4, s9 +; GFX8-NEXT: v_add_u32_e64 v0, s[10:11], s0, v0 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], s3, v3 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], s4, v4 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v4 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v5i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s10, s0 -; GFX9-NEXT: s_cmp_lt_u32 s10, s5 -; GFX9-NEXT: s_cselect_b32 s5, s10, s5 -; GFX9-NEXT: s_add_i32 s0, s0, s5 -; GFX9-NEXT: s_not_b32 s5, s1 -; GFX9-NEXT: s_cmp_lt_u32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_add_i32 s1, s1, s5 -; GFX9-NEXT: s_not_b32 s5, s2 -; GFX9-NEXT: s_cmp_lt_u32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_add_i32 s2, s2, s5 -; GFX9-NEXT: s_not_b32 s5, s3 -; GFX9-NEXT: s_cmp_lt_u32 s5, s8 -; GFX9-NEXT: s_cselect_b32 s5, s5, s8 -; GFX9-NEXT: s_add_i32 s3, s3, s5 -; GFX9-NEXT: s_not_b32 s5, s4 -; GFX9-NEXT: s_cmp_lt_u32 s5, s9 -; GFX9-NEXT: s_cselect_b32 s5, s5, s9 -; GFX9-NEXT: s_add_i32 s4, s4, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s5 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 +; GFX9-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v5i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s10, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s10, s5 -; GFX10-NEXT: s_cselect_b32 s5, s10, s5 -; GFX10-NEXT: s_not_b32 s10, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s5 -; GFX10-NEXT: s_cmp_lt_u32 s10, s6 -; GFX10-NEXT: s_cselect_b32 s5, s10, s6 -; GFX10-NEXT: s_not_b32 s6, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s5 -; GFX10-NEXT: s_cmp_lt_u32 s6, s7 -; GFX10-NEXT: s_cselect_b32 s5, s6, s7 -; GFX10-NEXT: s_not_b32 s6, s3 -; GFX10-NEXT: s_add_i32 s2, s2, s5 -; GFX10-NEXT: s_cmp_lt_u32 s6, s8 -; GFX10-NEXT: s_cselect_b32 s5, s6, s8 -; GFX10-NEXT: s_not_b32 s6, s4 -; GFX10-NEXT: s_add_i32 s3, s3, s5 -; GFX10-NEXT: s_cmp_lt_u32 s6, s9 -; GFX10-NEXT: s_cselect_b32 s5, s6, s9 -; GFX10-NEXT: s_add_i32 s4, s4, s5 ; GFX10-NEXT: ; return to shader part epilog %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) ret <5 x i32> %result @@ -1105,162 +895,66 @@ ; GFX8-LABEL: v_uaddsat_v16i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v32, -1, v0 -; GFX8-NEXT: v_min_u32_e32 v16, v32, v16 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v1 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v17 -; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v2 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v18 -; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v3 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v19 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v4 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v20 -; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v5 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v21 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v6 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v22 -; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v7 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v23 -; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v8 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v24 -; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v9 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v25 -; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v10 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v26 -; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v11 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v27 -; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v12 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v28 -; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v13 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v29 -; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v14 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v30 -; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v16 -; GFX8-NEXT: v_xor_b32_e32 v16, -1, v15 -; GFX8-NEXT: v_min_u32_e32 v16, v16, v31 -; GFX8-NEXT: v_add_u32_e32 v15, vcc, v15, v16 +; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v16 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v17 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v18 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v19 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v20 clamp +; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v21 clamp +; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v22 clamp +; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v23 clamp +; GFX8-NEXT: v_add_u32_e64 v8, s[4:5], v8, v24 clamp +; GFX8-NEXT: v_add_u32_e64 v9, s[4:5], v9, v25 clamp +; GFX8-NEXT: v_add_u32_e64 v10, s[4:5], v10, v26 clamp +; GFX8-NEXT: v_add_u32_e64 v11, s[4:5], v11, v27 clamp +; GFX8-NEXT: v_add_u32_e64 v12, s[4:5], v12, v28 clamp +; GFX8-NEXT: v_add_u32_e64 v13, s[4:5], v13, v29 clamp +; GFX8-NEXT: v_add_u32_e64 v14, s[4:5], v14, v30 clamp +; GFX8-NEXT: v_add_u32_e64 v15, s[4:5], v15, v31 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v16i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v32, -1, v0 -; GFX9-NEXT: v_min_u32_e32 v16, v32, v16 -; GFX9-NEXT: v_add_u32_e32 v0, v0, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v1 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v17 -; GFX9-NEXT: v_add_u32_e32 v1, v1, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v2 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v18 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v3 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v19 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v4 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v20 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v5 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v21 -; GFX9-NEXT: v_add_u32_e32 v5, v5, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v6 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v22 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v7 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v23 -; GFX9-NEXT: v_add_u32_e32 v7, v7, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v8 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v24 -; GFX9-NEXT: v_add_u32_e32 v8, v8, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v9 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v25 -; GFX9-NEXT: v_add_u32_e32 v9, v9, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v10 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v26 -; GFX9-NEXT: v_add_u32_e32 v10, v10, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v11 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v27 -; GFX9-NEXT: v_add_u32_e32 v11, v11, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v12 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v28 -; GFX9-NEXT: v_add_u32_e32 v12, v12, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v13 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v29 -; GFX9-NEXT: v_add_u32_e32 v13, v13, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v14 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v30 -; GFX9-NEXT: v_add_u32_e32 v14, v14, v16 -; GFX9-NEXT: v_xor_b32_e32 v16, -1, v15 -; GFX9-NEXT: v_min_u32_e32 v16, v16, v31 -; GFX9-NEXT: v_add_u32_e32 v15, v15, v16 +; GFX9-NEXT: v_add_u32_e64 v0, v0, v16 clamp +; GFX9-NEXT: v_add_u32_e64 v1, v1, v17 clamp +; GFX9-NEXT: v_add_u32_e64 v2, v2, v18 clamp +; GFX9-NEXT: v_add_u32_e64 v3, v3, v19 clamp +; GFX9-NEXT: v_add_u32_e64 v4, v4, v20 clamp +; GFX9-NEXT: v_add_u32_e64 v5, v5, v21 clamp +; GFX9-NEXT: v_add_u32_e64 v6, v6, v22 clamp +; GFX9-NEXT: v_add_u32_e64 v7, v7, v23 clamp +; GFX9-NEXT: v_add_u32_e64 v8, v8, v24 clamp +; GFX9-NEXT: v_add_u32_e64 v9, v9, v25 clamp +; GFX9-NEXT: v_add_u32_e64 v10, v10, v26 clamp +; GFX9-NEXT: v_add_u32_e64 v11, v11, v27 clamp +; GFX9-NEXT: v_add_u32_e64 v12, v12, v28 clamp +; GFX9-NEXT: v_add_u32_e64 v13, v13, v29 clamp +; GFX9-NEXT: v_add_u32_e64 v14, v14, v30 clamp +; GFX9-NEXT: v_add_u32_e64 v15, v15, v31 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v16i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v35, -1, v0 -; GFX10-NEXT: v_xor_b32_e32 v32, -1, v2 -; GFX10-NEXT: v_xor_b32_e32 v33, -1, v3 -; GFX10-NEXT: v_xor_b32_e32 v34, -1, v4 +; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v35, v35, v16 -; GFX10-NEXT: v_xor_b32_e32 v16, -1, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v35 -; GFX10-NEXT: v_xor_b32_e32 v35, -1, v5 -; GFX10-NEXT: v_min_u32_e32 v16, v16, v17 -; GFX10-NEXT: v_min_u32_e32 v17, v32, v18 -; GFX10-NEXT: v_min_u32_e32 v18, v33, v19 -; GFX10-NEXT: v_min_u32_e32 v19, v34, v20 -; GFX10-NEXT: v_min_u32_e32 v20, v35, v21 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v16 -; GFX10-NEXT: v_xor_b32_e32 v16, -1, v6 -; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v17 -; GFX10-NEXT: v_xor_b32_e32 v17, -1, v7 -; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v18 -; GFX10-NEXT: v_xor_b32_e32 v18, -1, v8 -; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v19 -; GFX10-NEXT: v_xor_b32_e32 v19, -1, v9 -; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v20 -; GFX10-NEXT: v_xor_b32_e32 v20, -1, v10 -; GFX10-NEXT: v_min_u32_e32 v16, v16, v22 -; GFX10-NEXT: v_min_u32_e32 v17, v17, v23 -; GFX10-NEXT: v_min_u32_e32 v18, v18, v24 -; GFX10-NEXT: v_min_u32_e32 v19, v19, v25 -; GFX10-NEXT: v_min_u32_e32 v20, v20, v26 -; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v16 -; GFX10-NEXT: v_xor_b32_e32 v16, -1, v11 -; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v17 -; GFX10-NEXT: v_xor_b32_e32 v17, -1, v12 -; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v18 -; GFX10-NEXT: v_xor_b32_e32 v18, -1, v13 -; GFX10-NEXT: v_add_nc_u32_e32 v9, v9, v19 -; GFX10-NEXT: v_xor_b32_e32 v19, -1, v14 -; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v20 -; GFX10-NEXT: v_xor_b32_e32 v20, -1, v15 -; GFX10-NEXT: v_min_u32_e32 v16, v16, v27 -; GFX10-NEXT: v_min_u32_e32 v17, v17, v28 -; GFX10-NEXT: v_min_u32_e32 v18, v18, v29 -; GFX10-NEXT: v_min_u32_e32 v19, v19, v30 -; GFX10-NEXT: v_min_u32_e32 v20, v20, v31 -; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v16 -; GFX10-NEXT: v_add_nc_u32_e32 v12, v12, v17 -; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v18 -; GFX10-NEXT: v_add_nc_u32_e32 v14, v14, v19 -; GFX10-NEXT: v_add_nc_u32_e32 v15, v15, v20 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) ret <16 x i32> %result @@ -1337,207 +1031,143 @@ ; ; GFX8-LABEL: s_uaddsat_v16i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_not_b32 s32, s0 -; GFX8-NEXT: s_cmp_lt_u32 s32, s16 -; GFX8-NEXT: s_cselect_b32 s16, s32, s16 -; GFX8-NEXT: s_add_i32 s0, s0, s16 -; GFX8-NEXT: s_not_b32 s16, s1 -; GFX8-NEXT: s_cmp_lt_u32 s16, s17 -; GFX8-NEXT: s_cselect_b32 s16, s16, s17 -; GFX8-NEXT: s_add_i32 s1, s1, s16 -; GFX8-NEXT: s_not_b32 s16, s2 -; GFX8-NEXT: s_cmp_lt_u32 s16, s18 -; GFX8-NEXT: s_cselect_b32 s16, s16, s18 -; GFX8-NEXT: s_add_i32 s2, s2, s16 -; GFX8-NEXT: s_not_b32 s16, s3 -; GFX8-NEXT: s_cmp_lt_u32 s16, s19 -; GFX8-NEXT: s_cselect_b32 s16, s16, s19 -; GFX8-NEXT: s_add_i32 s3, s3, s16 -; GFX8-NEXT: s_not_b32 s16, s4 -; GFX8-NEXT: s_cmp_lt_u32 s16, s20 -; GFX8-NEXT: s_cselect_b32 s16, s16, s20 -; GFX8-NEXT: s_add_i32 s4, s4, s16 -; GFX8-NEXT: s_not_b32 s16, s5 -; GFX8-NEXT: s_cmp_lt_u32 s16, s21 -; GFX8-NEXT: s_cselect_b32 s16, s16, s21 -; GFX8-NEXT: s_add_i32 s5, s5, s16 -; GFX8-NEXT: s_not_b32 s16, s6 -; GFX8-NEXT: s_cmp_lt_u32 s16, s22 -; GFX8-NEXT: s_cselect_b32 s16, s16, s22 -; GFX8-NEXT: s_add_i32 s6, s6, s16 -; GFX8-NEXT: s_not_b32 s16, s7 -; GFX8-NEXT: s_cmp_lt_u32 s16, s23 -; GFX8-NEXT: s_cselect_b32 s16, s16, s23 -; GFX8-NEXT: s_add_i32 s7, s7, s16 -; GFX8-NEXT: s_not_b32 s16, s8 -; GFX8-NEXT: s_cmp_lt_u32 s16, s24 -; GFX8-NEXT: s_cselect_b32 s16, s16, s24 -; GFX8-NEXT: s_add_i32 s8, s8, s16 -; GFX8-NEXT: s_not_b32 s16, s9 -; GFX8-NEXT: s_cmp_lt_u32 s16, s25 -; GFX8-NEXT: s_cselect_b32 s16, s16, s25 -; GFX8-NEXT: s_add_i32 s9, s9, s16 -; GFX8-NEXT: s_not_b32 s16, s10 -; GFX8-NEXT: s_cmp_lt_u32 s16, s26 -; GFX8-NEXT: s_cselect_b32 s16, s16, s26 -; GFX8-NEXT: s_add_i32 s10, s10, s16 -; GFX8-NEXT: s_not_b32 s16, s11 -; GFX8-NEXT: s_cmp_lt_u32 s16, s27 -; GFX8-NEXT: s_cselect_b32 s16, s16, s27 -; GFX8-NEXT: s_add_i32 s11, s11, s16 -; GFX8-NEXT: s_not_b32 s16, s12 -; GFX8-NEXT: s_cmp_lt_u32 s16, s28 -; GFX8-NEXT: s_cselect_b32 s16, s16, s28 -; GFX8-NEXT: s_add_i32 s12, s12, s16 -; GFX8-NEXT: s_not_b32 s16, s13 -; GFX8-NEXT: s_cmp_lt_u32 s16, s29 -; GFX8-NEXT: s_cselect_b32 s16, s16, s29 -; GFX8-NEXT: s_add_i32 s13, s13, s16 -; GFX8-NEXT: s_not_b32 s16, s14 -; GFX8-NEXT: s_cmp_lt_u32 s16, s30 -; GFX8-NEXT: s_cselect_b32 s16, s16, s30 -; GFX8-NEXT: s_add_i32 s14, s14, s16 -; GFX8-NEXT: s_not_b32 s16, s15 -; GFX8-NEXT: s_cmp_lt_u32 s16, s31 -; GFX8-NEXT: s_cselect_b32 s16, s16, s31 -; GFX8-NEXT: s_add_i32 s15, s15, s16 +; GFX8-NEXT: v_mov_b32_e32 v0, s16 +; GFX8-NEXT: v_mov_b32_e32 v1, s17 +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v5, s21 +; GFX8-NEXT: v_mov_b32_e32 v6, s22 +; GFX8-NEXT: v_mov_b32_e32 v7, s23 +; GFX8-NEXT: v_mov_b32_e32 v8, s24 +; GFX8-NEXT: v_mov_b32_e32 v9, s25 +; GFX8-NEXT: v_mov_b32_e32 v10, s26 +; GFX8-NEXT: v_mov_b32_e32 v11, s27 +; GFX8-NEXT: v_mov_b32_e32 v12, s28 +; GFX8-NEXT: v_mov_b32_e32 v13, s29 +; GFX8-NEXT: v_mov_b32_e32 v14, s30 +; GFX8-NEXT: v_mov_b32_e32 v15, s31 +; GFX8-NEXT: v_add_u32_e64 v0, s[32:33], s0, v0 clamp +; GFX8-NEXT: v_add_u32_e64 v1, s[16:17], s1, v1 clamp +; GFX8-NEXT: v_add_u32_e64 v2, s[16:17], s2, v2 clamp +; GFX8-NEXT: v_add_u32_e64 v3, s[2:3], s3, v3 clamp +; GFX8-NEXT: v_add_u32_e64 v4, s[2:3], s4, v4 clamp +; GFX8-NEXT: v_add_u32_e64 v5, s[2:3], s5, v5 clamp +; GFX8-NEXT: v_add_u32_e64 v6, s[2:3], s6, v6 clamp +; GFX8-NEXT: v_add_u32_e64 v7, s[2:3], s7, v7 clamp +; GFX8-NEXT: v_add_u32_e64 v8, s[2:3], s8, v8 clamp +; GFX8-NEXT: v_add_u32_e64 v9, s[2:3], s9, v9 clamp +; GFX8-NEXT: v_add_u32_e64 v10, s[2:3], s10, v10 clamp +; GFX8-NEXT: v_add_u32_e64 v11, s[2:3], s11, v11 clamp +; GFX8-NEXT: v_add_u32_e64 v12, s[2:3], s12, v12 clamp +; GFX8-NEXT: v_add_u32_e64 v13, s[2:3], s13, v13 clamp +; GFX8-NEXT: v_add_u32_e64 v14, s[2:3], s14, v14 clamp +; GFX8-NEXT: v_add_u32_e64 v15, s[2:3], s15, v15 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v4 +; GFX8-NEXT: v_readfirstlane_b32 s5, v5 +; GFX8-NEXT: v_readfirstlane_b32 s6, v6 +; GFX8-NEXT: v_readfirstlane_b32 s7, v7 +; GFX8-NEXT: v_readfirstlane_b32 s8, v8 +; GFX8-NEXT: v_readfirstlane_b32 s9, v9 +; GFX8-NEXT: v_readfirstlane_b32 s10, v10 +; GFX8-NEXT: v_readfirstlane_b32 s11, v11 +; GFX8-NEXT: v_readfirstlane_b32 s12, v12 +; GFX8-NEXT: v_readfirstlane_b32 s13, v13 +; GFX8-NEXT: v_readfirstlane_b32 s14, v14 +; GFX8-NEXT: v_readfirstlane_b32 s15, v15 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v16i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_not_b32 s32, s0 -; GFX9-NEXT: s_cmp_lt_u32 s32, s16 -; GFX9-NEXT: s_cselect_b32 s16, s32, s16 -; GFX9-NEXT: s_add_i32 s0, s0, s16 -; GFX9-NEXT: s_not_b32 s16, s1 -; GFX9-NEXT: s_cmp_lt_u32 s16, s17 -; GFX9-NEXT: s_cselect_b32 s16, s16, s17 -; GFX9-NEXT: s_add_i32 s1, s1, s16 -; GFX9-NEXT: s_not_b32 s16, s2 -; GFX9-NEXT: s_cmp_lt_u32 s16, s18 -; GFX9-NEXT: s_cselect_b32 s16, s16, s18 -; GFX9-NEXT: s_add_i32 s2, s2, s16 -; GFX9-NEXT: s_not_b32 s16, s3 -; GFX9-NEXT: s_cmp_lt_u32 s16, s19 -; GFX9-NEXT: s_cselect_b32 s16, s16, s19 -; GFX9-NEXT: s_add_i32 s3, s3, s16 -; GFX9-NEXT: s_not_b32 s16, s4 -; GFX9-NEXT: s_cmp_lt_u32 s16, s20 -; GFX9-NEXT: s_cselect_b32 s16, s16, s20 -; GFX9-NEXT: s_add_i32 s4, s4, s16 -; GFX9-NEXT: s_not_b32 s16, s5 -; GFX9-NEXT: s_cmp_lt_u32 s16, s21 -; GFX9-NEXT: s_cselect_b32 s16, s16, s21 -; GFX9-NEXT: s_add_i32 s5, s5, s16 -; GFX9-NEXT: s_not_b32 s16, s6 -; GFX9-NEXT: s_cmp_lt_u32 s16, s22 -; GFX9-NEXT: s_cselect_b32 s16, s16, s22 -; GFX9-NEXT: s_add_i32 s6, s6, s16 -; GFX9-NEXT: s_not_b32 s16, s7 -; GFX9-NEXT: s_cmp_lt_u32 s16, s23 -; GFX9-NEXT: s_cselect_b32 s16, s16, s23 -; GFX9-NEXT: s_add_i32 s7, s7, s16 -; GFX9-NEXT: s_not_b32 s16, s8 -; GFX9-NEXT: s_cmp_lt_u32 s16, s24 -; GFX9-NEXT: s_cselect_b32 s16, s16, s24 -; GFX9-NEXT: s_add_i32 s8, s8, s16 -; GFX9-NEXT: s_not_b32 s16, s9 -; GFX9-NEXT: s_cmp_lt_u32 s16, s25 -; GFX9-NEXT: s_cselect_b32 s16, s16, s25 -; GFX9-NEXT: s_add_i32 s9, s9, s16 -; GFX9-NEXT: s_not_b32 s16, s10 -; GFX9-NEXT: s_cmp_lt_u32 s16, s26 -; GFX9-NEXT: s_cselect_b32 s16, s16, s26 -; GFX9-NEXT: s_add_i32 s10, s10, s16 -; GFX9-NEXT: s_not_b32 s16, s11 -; GFX9-NEXT: s_cmp_lt_u32 s16, s27 -; GFX9-NEXT: s_cselect_b32 s16, s16, s27 -; GFX9-NEXT: s_add_i32 s11, s11, s16 -; GFX9-NEXT: s_not_b32 s16, s12 -; GFX9-NEXT: s_cmp_lt_u32 s16, s28 -; GFX9-NEXT: s_cselect_b32 s16, s16, s28 -; GFX9-NEXT: s_add_i32 s12, s12, s16 -; GFX9-NEXT: s_not_b32 s16, s13 -; GFX9-NEXT: s_cmp_lt_u32 s16, s29 -; GFX9-NEXT: s_cselect_b32 s16, s16, s29 -; GFX9-NEXT: s_add_i32 s13, s13, s16 -; GFX9-NEXT: s_not_b32 s16, s14 -; GFX9-NEXT: s_cmp_lt_u32 s16, s30 -; GFX9-NEXT: s_cselect_b32 s16, s16, s30 -; GFX9-NEXT: s_add_i32 s14, s14, s16 -; GFX9-NEXT: s_not_b32 s16, s15 -; GFX9-NEXT: s_cmp_lt_u32 s16, s31 -; GFX9-NEXT: s_cselect_b32 s16, s16, s31 -; GFX9-NEXT: s_add_i32 s15, s15, s16 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: v_mov_b32_e32 v14, s30 +; GFX9-NEXT: v_mov_b32_e32 v15, s31 +; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp +; GFX9-NEXT: v_add_u32_e64 v5, s5, v5 clamp +; GFX9-NEXT: v_add_u32_e64 v6, s6, v6 clamp +; GFX9-NEXT: v_add_u32_e64 v7, s7, v7 clamp +; GFX9-NEXT: v_add_u32_e64 v8, s8, v8 clamp +; GFX9-NEXT: v_add_u32_e64 v9, s9, v9 clamp +; GFX9-NEXT: v_add_u32_e64 v10, s10, v10 clamp +; GFX9-NEXT: v_add_u32_e64 v11, s11, v11 clamp +; GFX9-NEXT: v_add_u32_e64 v12, s12, v12 clamp +; GFX9-NEXT: v_add_u32_e64 v13, s13, v13 clamp +; GFX9-NEXT: v_add_u32_e64 v14, s14, v14 clamp +; GFX9-NEXT: v_add_u32_e64 v15, s15, v15 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 +; GFX9-NEXT: v_readfirstlane_b32 s5, v5 +; GFX9-NEXT: v_readfirstlane_b32 s6, v6 +; GFX9-NEXT: v_readfirstlane_b32 s7, v7 +; GFX9-NEXT: v_readfirstlane_b32 s8, v8 +; GFX9-NEXT: v_readfirstlane_b32 s9, v9 +; GFX9-NEXT: v_readfirstlane_b32 s10, v10 +; GFX9-NEXT: v_readfirstlane_b32 s11, v11 +; GFX9-NEXT: v_readfirstlane_b32 s12, v12 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v16i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_not_b32 s46, s0 +; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp +; GFX10-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 +; GFX10-NEXT: v_readfirstlane_b32 s5, v5 +; GFX10-NEXT: v_readfirstlane_b32 s6, v6 +; GFX10-NEXT: v_readfirstlane_b32 s7, v7 +; GFX10-NEXT: v_readfirstlane_b32 s8, v8 +; GFX10-NEXT: v_readfirstlane_b32 s9, v9 +; GFX10-NEXT: v_readfirstlane_b32 s10, v10 +; GFX10-NEXT: v_readfirstlane_b32 s11, v11 +; GFX10-NEXT: v_readfirstlane_b32 s12, v12 +; GFX10-NEXT: v_readfirstlane_b32 s13, v13 +; GFX10-NEXT: v_readfirstlane_b32 s14, v14 +; GFX10-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s46, s16 -; GFX10-NEXT: s_cselect_b32 s46, s46, s16 -; GFX10-NEXT: s_not_b32 s47, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s46 -; GFX10-NEXT: s_cmp_lt_u32 s47, s17 -; GFX10-NEXT: s_cselect_b32 s46, s47, s17 -; GFX10-NEXT: s_not_b32 s17, s2 -; GFX10-NEXT: s_add_i32 s1, s1, s46 -; GFX10-NEXT: s_cmp_lt_u32 s17, s18 -; GFX10-NEXT: s_cselect_b32 s16, s17, s18 -; GFX10-NEXT: s_not_b32 s17, s3 -; GFX10-NEXT: s_add_i32 s2, s2, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s19 -; GFX10-NEXT: s_cselect_b32 s16, s17, s19 -; GFX10-NEXT: s_not_b32 s17, s4 -; GFX10-NEXT: s_add_i32 s3, s3, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s20 -; GFX10-NEXT: s_cselect_b32 s16, s17, s20 -; GFX10-NEXT: s_not_b32 s17, s5 -; GFX10-NEXT: s_add_i32 s4, s4, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s21 -; GFX10-NEXT: s_cselect_b32 s16, s17, s21 -; GFX10-NEXT: s_not_b32 s17, s6 -; GFX10-NEXT: s_add_i32 s5, s5, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s22 -; GFX10-NEXT: s_cselect_b32 s16, s17, s22 -; GFX10-NEXT: s_not_b32 s17, s7 -; GFX10-NEXT: s_add_i32 s6, s6, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s23 -; GFX10-NEXT: s_cselect_b32 s16, s17, s23 -; GFX10-NEXT: s_not_b32 s17, s8 -; GFX10-NEXT: s_add_i32 s7, s7, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s24 -; GFX10-NEXT: s_cselect_b32 s16, s17, s24 -; GFX10-NEXT: s_not_b32 s17, s9 -; GFX10-NEXT: s_add_i32 s8, s8, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s25 -; GFX10-NEXT: s_cselect_b32 s16, s17, s25 -; GFX10-NEXT: s_not_b32 s17, s10 -; GFX10-NEXT: s_add_i32 s9, s9, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s26 -; GFX10-NEXT: s_cselect_b32 s16, s17, s26 -; GFX10-NEXT: s_not_b32 s17, s11 -; GFX10-NEXT: s_add_i32 s10, s10, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s27 -; GFX10-NEXT: s_cselect_b32 s16, s17, s27 -; GFX10-NEXT: s_not_b32 s17, s12 -; GFX10-NEXT: s_add_i32 s11, s11, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s28 -; GFX10-NEXT: s_cselect_b32 s16, s17, s28 -; GFX10-NEXT: s_not_b32 s17, s13 -; GFX10-NEXT: s_add_i32 s12, s12, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s29 -; GFX10-NEXT: s_cselect_b32 s16, s17, s29 -; GFX10-NEXT: s_not_b32 s17, s14 -; GFX10-NEXT: s_add_i32 s13, s13, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s30 -; GFX10-NEXT: s_cselect_b32 s16, s17, s30 -; GFX10-NEXT: s_not_b32 s17, s15 -; GFX10-NEXT: s_add_i32 s14, s14, s16 -; GFX10-NEXT: s_cmp_lt_u32 s17, s31 -; GFX10-NEXT: s_cselect_b32 s16, s17, s31 -; GFX10-NEXT: s_add_i32 s15, s15, s16 ; GFX10-NEXT: ; return to shader part epilog %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) ret <16 x i32> %result @@ -1558,27 +1188,21 @@ ; GFX8-LABEL: v_uaddsat_i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX8-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_xor_b32_e32 v2, 0xffff, v0 -; GFX9-NEXT: v_min_u16_e32 v1, v2, v1 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_xor_b32_e32 v2, 0xffff, v0 +; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u16_e64 v1, v2, v1 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -1598,33 +1222,23 @@ ; ; GFX8-LABEL: s_uaddsat_i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_xor_b32 s2, s0, 0xffff -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s1 -; GFX8-NEXT: s_cselect_b32 s1, s2, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_xor_b32 s2, s0, 0xffff -; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_add_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_xor_b32 s2, s0, 0xffff -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000 +; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_add_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -1643,24 +1257,18 @@ ; ; GFX8-LABEL: uaddsat_i16_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_xor_b32 s1, s0, 0xffff -; GFX8-NEXT: v_min_u16_e32 v0, s1, v0 -; GFX8-NEXT: v_add_u16_e32 v0, s0, v0 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_xor_b32 s1, s0, 0xffff -; GFX9-NEXT: v_min_u16_e32 v0, s1, v0 -; GFX9-NEXT: v_add_u16_e32 v0, s0, v0 +; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_xor_b32 s1, s0, 0xffff +; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u16_e64 v0, s1, v0 -; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -1680,24 +1288,18 @@ ; ; GFX8-LABEL: uaddsat_i16_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff, v0 -; GFX8-NEXT: v_min_u16_e32 v1, s0, v1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_add_u16_e64 v0, v0, s0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_xor_b32_e32 v1, 0xffff, v0 -; GFX9-NEXT: v_min_u16_e32 v1, s0, v1 -; GFX9-NEXT: v_add_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_add_u16_e64 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor_b32_e32 v1, 0xffff, v0 +; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u16_e64 v1, v1, s0 -; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -1725,35 +1327,25 @@ ; GFX8-LABEL: v_uaddsat_v2i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_mov_b32 s4, 0xffff -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX8-NEXT: v_xor_b32_e32 v3, s4, v0 -; GFX8-NEXT: v_xor_b32_e32 v4, s4, v2 -; GFX8-NEXT: v_min_u16_e32 v3, v3, v1 -; GFX8-NEXT: v_min_u16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v3 -; GFX8-NEXT: v_add_u16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: v_xor_b32_e32 v2, s4, v0 -; GFX9-NEXT: v_pk_min_u16 v1, v2, v1 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 +; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v2i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v2, s4, v0 -; GFX10-NEXT: v_pk_min_u16 v1, v2, v1 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) ret <2 x i16> %result @@ -1785,68 +1377,30 @@ ; ; GFX8-LABEL: s_uaddsat_v2i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s4, 0xffff -; GFX8-NEXT: s_xor_b32 s5, s0, s4 ; GFX8-NEXT: s_lshr_b32 s3, s1, 16 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16 -; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s5, s1 -; GFX8-NEXT: s_cselect_b32 s1, s5, s1 -; GFX8-NEXT: s_add_i32 s0, s0, s1 -; GFX8-NEXT: s_xor_b32 s1, s2, s4 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s1, s3 -; GFX8-NEXT: s_cselect_b32 s1, s1, s3 -; GFX8-NEXT: s_add_i32 s2, s2, s1 -; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s1, s1, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_add_u16_e64 v1, s2, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v2i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s2, -1, -1 -; GFX9-NEXT: s_xor_b32 s2, s0, s2 -; GFX9-NEXT: s_mov_b32 s4, 0xffff -; GFX9-NEXT: s_lshr_b32 s3, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s1, 16 -; GFX9-NEXT: s_and_b32 s2, s2, s4 -; GFX9-NEXT: s_and_b32 s1, s1, s4 -; GFX9-NEXT: s_cmp_lt_u32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_cmp_lt_u32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s2, s3, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 -; GFX9-NEXT: s_lshr_b32 s2, s0, 16 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s1 -; GFX9-NEXT: s_add_i32 s2, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v2i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s2, -1, -1 -; GFX10-NEXT: s_mov_b32 s3, 0xffff -; GFX10-NEXT: s_xor_b32 s2, s0, s2 +; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_and_b32 s2, s2, s3 -; GFX10-NEXT: s_and_b32 s3, s1, s3 -; GFX10-NEXT: s_lshr_b32 s1, s1, 16 -; GFX10-NEXT: s_cmp_lt_u32 s2, s3 -; GFX10-NEXT: s_cselect_b32 s2, s2, s3 -; GFX10-NEXT: s_cmp_lt_u32 s4, s1 -; GFX10-NEXT: s_cselect_b32 s1, s4, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX10-NEXT: s_lshr_b32 s2, s0, 16 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s1 -; GFX10-NEXT: s_add_i32 s2, s2, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to i32 @@ -1877,34 +1431,24 @@ ; ; GFX8-LABEL: uaddsat_v2i16_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s2, 0xffff ; GFX8-NEXT: s_lshr_b32 s1, s0, 16 -; GFX8-NEXT: s_xor_b32 s3, s0, s2 -; GFX8-NEXT: s_xor_b32 s2, s1, s2 -; GFX8-NEXT: v_mov_b32_e32 v2, s2 -; GFX8-NEXT: v_min_u16_e32 v1, s3, v0 -; GFX8-NEXT: v_min_u16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_add_u16_e32 v1, s0, v1 -; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX8-NEXT: v_add_u16_e64 v1, s0, v0 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_v2i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s1, -1, -1 -; GFX9-NEXT: s_xor_b32 s1, s0, s1 -; GFX9-NEXT: v_pk_min_u16 v0, s1, v0 -; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 +; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_v2i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_xor_b32 s1, s0, s1 -; GFX10-NEXT: v_pk_min_u16 v0, s1, v0 -; GFX10-NEXT: v_pk_add_u16 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -1935,33 +1479,24 @@ ; ; GFX8-LABEL: uaddsat_v2i16_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s2, 0xffff -; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0 -; GFX8-NEXT: v_xor_b32_e32 v2, s2, v0 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16 -; GFX8-NEXT: v_xor_b32_e32 v3, s2, v1 -; GFX8-NEXT: v_min_u16_e32 v2, s0, v2 -; GFX8-NEXT: v_min_u16_e32 v3, s1, v3 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v2 -; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_add_u16_e64 v1, v0, s0 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: uaddsat_v2i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s1, -1, -1 -; GFX9-NEXT: v_xor_b32_e32 v1, s1, v0 -; GFX9-NEXT: v_pk_min_u16 v1, v1, s0 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 +; GFX9-NEXT: v_pk_add_u16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: uaddsat_v2i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s1, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v1, s1, v0 -; GFX10-NEXT: v_pk_min_u16 v1, v1, s0 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -2021,49 +1556,31 @@ ; GFX8-LABEL: v_uaddsat_v4i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_mov_b32 s4, 0xffff -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_xor_b32_e32 v6, s4, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_xor_b32_e32 v7, s4, v4 -; GFX8-NEXT: v_min_u16_e32 v6, v6, v2 -; GFX8-NEXT: v_min_u16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v7, s4, v1 -; GFX8-NEXT: v_xor_b32_e32 v8, s4, v5 -; GFX8-NEXT: v_min_u16_e32 v7, v7, v3 -; GFX8-NEXT: v_min_u16_sdwa v3, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v6 -; GFX8-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX8-NEXT: v_add_u16_e32 v1, v1, v7 -; GFX8-NEXT: v_add_u16_sdwa v2, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_add_u16_e64 v4, v0, v2 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v2, v1, v3 clamp +; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v3, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v4i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: v_xor_b32_e32 v4, s4, v0 -; GFX9-NEXT: v_pk_min_u16 v2, v4, v2 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 -; GFX9-NEXT: v_xor_b32_e32 v2, s4, v1 -; GFX9-NEXT: v_pk_min_u16 v2, v2, v3 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v2 +; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v4i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 clamp +; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v4, s4, v0 -; GFX10-NEXT: v_xor_b32_e32 v5, s4, v1 -; GFX10-NEXT: v_pk_min_u16 v2, v4, v2 -; GFX10-NEXT: v_pk_min_u16 v3, v5, v3 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x float> @@ -2114,116 +1631,44 @@ ; ; GFX8-LABEL: s_uaddsat_v4i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s8, 0xffff -; GFX8-NEXT: s_xor_b32 s9, s0, s8 ; GFX8-NEXT: s_lshr_b32 s6, s2, 16 +; GFX8-NEXT: s_lshr_b32 s7, s3, 16 ; GFX8-NEXT: s_lshr_b32 s4, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: s_lshr_b32 s5, s1, 16 -; GFX8-NEXT: s_lshr_b32 s7, s3, 16 -; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s9, s2 -; GFX8-NEXT: s_cselect_b32 s2, s9, s2 -; GFX8-NEXT: s_add_i32 s0, s0, s2 -; GFX8-NEXT: s_xor_b32 s2, s4, s8 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s6 -; GFX8-NEXT: s_cselect_b32 s2, s2, s6 -; GFX8-NEXT: s_add_i32 s4, s4, s2 -; GFX8-NEXT: s_xor_b32 s2, s1, s8 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s3 -; GFX8-NEXT: s_cselect_b32 s2, s2, s3 -; GFX8-NEXT: s_add_i32 s1, s1, s2 -; GFX8-NEXT: s_xor_b32 s2, s5, s8 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s3 -; GFX8-NEXT: s_cselect_b32 s2, s2, s3 -; GFX8-NEXT: s_add_i32 s5, s5, s2 -; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s2, s2, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s2 -; GFX8-NEXT: s_bfe_u32 s2, s5, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s2, s2, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_add_u16_e64 v1, s4, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v3, s5, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v4i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: s_xor_b32 s5, s0, s4 -; GFX9-NEXT: s_mov_b32 s7, 0xffff -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: s_lshr_b32 s8, s2, 16 -; GFX9-NEXT: s_and_b32 s5, s5, s7 -; GFX9-NEXT: s_and_b32 s2, s2, s7 -; GFX9-NEXT: s_cmp_lt_u32 s5, s2 -; GFX9-NEXT: s_cselect_b32 s2, s5, s2 -; GFX9-NEXT: s_cmp_lt_u32 s6, s8 -; GFX9-NEXT: s_cselect_b32 s5, s6, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX9-NEXT: s_lshr_b32 s5, s0, 16 -; GFX9-NEXT: s_lshr_b32 s6, s2, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s2 -; GFX9-NEXT: s_xor_b32 s2, s1, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s5 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_and_b32 s2, s2, s7 -; GFX9-NEXT: s_and_b32 s3, s3, s7 -; GFX9-NEXT: s_cmp_lt_u32 s2, s3 -; GFX9-NEXT: s_cselect_b32 s2, s2, s3 -; GFX9-NEXT: s_cmp_lt_u32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s3, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s2 -; GFX9-NEXT: s_add_i32 s3, s3, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v4i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX10-NEXT: s_mov_b32 s6, 0xffff -; GFX10-NEXT: s_xor_b32 s5, s0, s4 -; GFX10-NEXT: s_and_b32 s8, s2, s6 -; GFX10-NEXT: s_lshr_b32 s7, s5, 16 -; GFX10-NEXT: s_and_b32 s5, s5, s6 -; GFX10-NEXT: s_lshr_b32 s2, s2, 16 -; GFX10-NEXT: s_cmp_lt_u32 s5, s8 +; GFX10-NEXT: v_pk_add_u16 v0, s0, s2 clamp +; GFX10-NEXT: v_pk_add_u16 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s5, s8 -; GFX10-NEXT: s_cmp_lt_u32 s7, s2 -; GFX10-NEXT: s_cselect_b32 s2, s7, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s5, s2 -; GFX10-NEXT: s_lshr_b32 s5, s0, 16 -; GFX10-NEXT: s_lshr_b32 s7, s2, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s2 -; GFX10-NEXT: s_xor_b32 s2, s1, s4 -; GFX10-NEXT: s_add_i32 s5, s5, s7 -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_and_b32 s2, s2, s6 -; GFX10-NEXT: s_and_b32 s6, s3, s6 -; GFX10-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_u32 s2, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s5 -; GFX10-NEXT: s_cselect_b32 s2, s2, s6 -; GFX10-NEXT: s_cmp_lt_u32 s4, s3 -; GFX10-NEXT: s_cselect_b32 s3, s4, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3 -; GFX10-NEXT: s_lshr_b32 s3, s1, 16 -; GFX10-NEXT: s_lshr_b32 s4, s2, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s2 -; GFX10-NEXT: s_add_i32 s3, s3, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x i32> @@ -2299,63 +1744,38 @@ ; GFX8-LABEL: v_uaddsat_v6i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_mov_b32 s4, 0xffff -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_xor_b32_e32 v9, s4, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1 -; GFX8-NEXT: v_xor_b32_e32 v10, s4, v6 -; GFX8-NEXT: v_min_u16_e32 v9, v9, v3 -; GFX8-NEXT: v_min_u16_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v10, s4, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX8-NEXT: v_xor_b32_e32 v11, s4, v7 -; GFX8-NEXT: v_min_u16_e32 v10, v10, v4 -; GFX8-NEXT: v_min_u16_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v11, s4, v2 -; GFX8-NEXT: v_xor_b32_e32 v12, s4, v8 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v9 -; GFX8-NEXT: v_add_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v11, v11, v5 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v3 -; GFX8-NEXT: v_min_u16_sdwa v5, v12, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v1, v1, v10 -; GFX8-NEXT: v_add_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX8-NEXT: v_add_u16_e32 v2, v2, v11 -; GFX8-NEXT: v_add_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: v_add_u16_e64 v6, v0, v3 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v0, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v3, v1, v4 clamp +; GFX8-NEXT: v_add_u16_sdwa v1, v1, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v4, v2, v5 clamp +; GFX8-NEXT: v_add_u16_sdwa v2, v2, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v5, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v3, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v6i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: v_xor_b32_e32 v6, s4, v0 -; GFX9-NEXT: v_pk_min_u16 v3, v6, v3 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v3 -; GFX9-NEXT: v_xor_b32_e32 v3, s4, v1 -; GFX9-NEXT: v_pk_min_u16 v3, v3, v4 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 -; GFX9-NEXT: v_xor_b32_e32 v3, s4, v2 -; GFX9-NEXT: v_pk_min_u16 v3, v3, v5 -; GFX9-NEXT: v_pk_add_u16 v2, v2, v3 +; GFX9-NEXT: v_pk_add_u16 v0, v0, v3 clamp +; GFX9-NEXT: v_pk_add_u16 v1, v1, v4 clamp +; GFX9-NEXT: v_pk_add_u16 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v6i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, v0, v3 clamp +; GFX10-NEXT: v_pk_add_u16 v1, v1, v4 clamp +; GFX10-NEXT: v_pk_add_u16 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v6, s4, v0 -; GFX10-NEXT: v_xor_b32_e32 v7, s4, v1 -; GFX10-NEXT: v_xor_b32_e32 v8, s4, v2 -; GFX10-NEXT: v_pk_min_u16 v3, v6, v3 -; GFX10-NEXT: v_pk_min_u16 v4, v7, v4 -; GFX10-NEXT: v_pk_min_u16 v5, v8, v5 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v3 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v4 -; GFX10-NEXT: v_pk_add_u16 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x float> @@ -2424,164 +1844,58 @@ ; ; GFX8-LABEL: s_uaddsat_v6i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s12, 0xffff -; GFX8-NEXT: s_xor_b32 s13, s0, s12 ; GFX8-NEXT: s_lshr_b32 s9, s3, 16 +; GFX8-NEXT: s_lshr_b32 s10, s4, 16 ; GFX8-NEXT: s_lshr_b32 s6, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s9 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_lshr_b32 s11, s5, 16 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16 +; GFX8-NEXT: v_mov_b32_e32 v3, s10 +; GFX8-NEXT: v_add_u16_e64 v1, s6, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v6, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: s_lshr_b32 s8, s2, 16 -; GFX8-NEXT: s_lshr_b32 s10, s4, 16 -; GFX8-NEXT: s_lshr_b32 s11, s5, 16 -; GFX8-NEXT: s_bfe_u32 s13, s13, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s13, s3 -; GFX8-NEXT: s_cselect_b32 s3, s13, s3 -; GFX8-NEXT: s_add_i32 s0, s0, s3 -; GFX8-NEXT: s_xor_b32 s3, s6, s12 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s9 -; GFX8-NEXT: s_cselect_b32 s3, s3, s9 -; GFX8-NEXT: s_add_i32 s6, s6, s3 -; GFX8-NEXT: s_xor_b32 s3, s1, s12 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_add_i32 s1, s1, s3 -; GFX8-NEXT: s_xor_b32 s3, s7, s12 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s10, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_add_i32 s7, s7, s3 -; GFX8-NEXT: s_xor_b32 s3, s2, s12 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_add_i32 s2, s2, s3 -; GFX8-NEXT: s_xor_b32 s3, s8, s12 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s11, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_add_i32 s8, s8, s3 -; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s3 -; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s3 -; GFX8-NEXT: s_bfe_u32 s3, s8, 0x100000 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s2, s2, s3 +; GFX8-NEXT: v_mov_b32_e32 v5, s11 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v3, s7, v3 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v5, s8, v5 clamp +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_add_u16_e64 v4, s2, v4 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v6i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX9-NEXT: s_xor_b32 s7, s0, s6 -; GFX9-NEXT: s_mov_b32 s9, 0xffff -; GFX9-NEXT: s_lshr_b32 s8, s7, 16 -; GFX9-NEXT: s_lshr_b32 s10, s3, 16 -; GFX9-NEXT: s_and_b32 s7, s7, s9 -; GFX9-NEXT: s_and_b32 s3, s3, s9 -; GFX9-NEXT: s_cmp_lt_u32 s7, s3 -; GFX9-NEXT: s_cselect_b32 s3, s7, s3 -; GFX9-NEXT: s_cmp_lt_u32 s8, s10 -; GFX9-NEXT: s_cselect_b32 s7, s8, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s7 -; GFX9-NEXT: s_lshr_b32 s7, s0, 16 -; GFX9-NEXT: s_lshr_b32 s8, s3, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s3 -; GFX9-NEXT: s_add_i32 s7, s7, s8 -; GFX9-NEXT: s_xor_b32 s3, s1, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s7 -; GFX9-NEXT: s_lshr_b32 s7, s3, 16 -; GFX9-NEXT: s_lshr_b32 s8, s4, 16 -; GFX9-NEXT: s_and_b32 s3, s3, s9 -; GFX9-NEXT: s_and_b32 s4, s4, s9 -; GFX9-NEXT: s_cmp_lt_u32 s3, s4 -; GFX9-NEXT: s_cselect_b32 s3, s3, s4 -; GFX9-NEXT: s_cmp_lt_u32 s7, s8 -; GFX9-NEXT: s_cselect_b32 s4, s7, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_lshr_b32 s4, s1, 16 -; GFX9-NEXT: s_lshr_b32 s7, s3, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s7 -; GFX9-NEXT: s_xor_b32 s3, s2, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: s_and_b32 s3, s3, s9 -; GFX9-NEXT: s_and_b32 s5, s5, s9 -; GFX9-NEXT: s_cmp_lt_u32 s3, s5 -; GFX9-NEXT: s_cselect_b32 s3, s3, s5 -; GFX9-NEXT: s_cmp_lt_u32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_add_i32 s2, s2, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_add_u16 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v6i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s6, -1, -1 -; GFX10-NEXT: s_mov_b32 s8, 0xffff -; GFX10-NEXT: s_xor_b32 s7, s0, s6 -; GFX10-NEXT: s_and_b32 s10, s3, s8 -; GFX10-NEXT: s_lshr_b32 s9, s7, 16 -; GFX10-NEXT: s_and_b32 s7, s7, s8 -; GFX10-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_u32 s7, s10 +; GFX10-NEXT: v_pk_add_u16 v0, s0, s3 clamp +; GFX10-NEXT: v_pk_add_u16 v1, s1, s4 clamp +; GFX10-NEXT: v_pk_add_u16 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s7, s7, s10 -; GFX10-NEXT: s_cmp_lt_u32 s9, s3 -; GFX10-NEXT: s_cselect_b32 s3, s9, s3 -; GFX10-NEXT: s_and_b32 s10, s4, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s7, s3 -; GFX10-NEXT: s_lshr_b32 s7, s0, 16 -; GFX10-NEXT: s_lshr_b32 s9, s3, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s3 -; GFX10-NEXT: s_xor_b32 s3, s1, s6 -; GFX10-NEXT: s_add_i32 s7, s7, s9 -; GFX10-NEXT: s_lshr_b32 s9, s3, 16 -; GFX10-NEXT: s_and_b32 s3, s3, s8 -; GFX10-NEXT: s_lshr_b32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_u32 s3, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s7 -; GFX10-NEXT: s_cselect_b32 s3, s3, s10 -; GFX10-NEXT: s_cmp_lt_u32 s9, s4 -; GFX10-NEXT: s_cselect_b32 s4, s9, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX10-NEXT: s_lshr_b32 s4, s1, 16 -; GFX10-NEXT: s_lshr_b32 s9, s3, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s3 -; GFX10-NEXT: s_xor_b32 s3, s2, s6 -; GFX10-NEXT: s_add_i32 s4, s4, s9 -; GFX10-NEXT: s_lshr_b32 s6, s3, 16 -; GFX10-NEXT: s_and_b32 s3, s3, s8 -; GFX10-NEXT: s_and_b32 s8, s5, s8 -; GFX10-NEXT: s_lshr_b32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_u32 s3, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX10-NEXT: s_cselect_b32 s3, s3, s8 -; GFX10-NEXT: s_cmp_lt_u32 s6, s5 -; GFX10-NEXT: s_cselect_b32 s5, s6, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 -; GFX10-NEXT: s_lshr_b32 s5, s2, 16 -; GFX10-NEXT: s_lshr_b32 s6, s3, 16 -; GFX10-NEXT: s_add_i32 s2, s2, s3 -; GFX10-NEXT: s_add_i32 s5, s5, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s5 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x i32> @@ -2662,77 +1976,44 @@ ; GFX8-LABEL: v_uaddsat_v8i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: s_mov_b32 s4, 0xffff -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0 -; GFX8-NEXT: v_xor_b32_e32 v12, s4, v0 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1 -; GFX8-NEXT: v_xor_b32_e32 v13, s4, v8 -; GFX8-NEXT: v_min_u16_e32 v12, v12, v4 -; GFX8-NEXT: v_min_u16_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v13, s4, v1 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX8-NEXT: v_xor_b32_e32 v14, s4, v9 -; GFX8-NEXT: v_min_u16_e32 v13, v13, v5 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX8-NEXT: v_min_u16_sdwa v5, v14, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v14, s4, v2 -; GFX8-NEXT: v_xor_b32_e32 v15, s4, v10 -; GFX8-NEXT: v_add_u16_e32 v0, v0, v12 -; GFX8-NEXT: v_add_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v14, v14, v6 -; GFX8-NEXT: v_min_u16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_xor_b32_e32 v15, s4, v3 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_xor_b32_e32 v16, s4, v11 -; GFX8-NEXT: v_add_u16_e32 v1, v1, v13 -; GFX8-NEXT: v_add_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v15, v15, v7 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 -; GFX8-NEXT: v_min_u16_sdwa v7, v16, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_add_u16_e32 v2, v2, v14 -; GFX8-NEXT: v_add_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX8-NEXT: v_add_u16_e32 v3, v3, v15 -; GFX8-NEXT: v_add_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v3, v3, v4 +; GFX8-NEXT: v_add_u16_e64 v8, v0, v4 clamp +; GFX8-NEXT: v_add_u16_sdwa v0, v0, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v4, v1, v5 clamp +; GFX8-NEXT: v_add_u16_sdwa v1, v1, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v5, v2, v6 clamp +; GFX8-NEXT: v_add_u16_sdwa v2, v2, v6 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_add_u16_e64 v6, v3, v7 clamp +; GFX8-NEXT: v_add_u16_sdwa v3, v3, v7 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v7, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_mov_b32_e32 v7, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_uaddsat_v8i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_pack_ll_b32_b16 s4, -1, -1 -; GFX9-NEXT: v_xor_b32_e32 v8, s4, v0 -; GFX9-NEXT: v_pk_min_u16 v4, v8, v4 -; GFX9-NEXT: v_pk_add_u16 v0, v0, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, s4, v1 -; GFX9-NEXT: v_pk_min_u16 v4, v4, v5 -; GFX9-NEXT: v_pk_add_u16 v1, v1, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, s4, v2 -; GFX9-NEXT: v_pk_min_u16 v4, v4, v6 -; GFX9-NEXT: v_pk_add_u16 v2, v2, v4 -; GFX9-NEXT: v_xor_b32_e32 v4, s4, v3 -; GFX9-NEXT: v_pk_min_u16 v4, v4, v7 -; GFX9-NEXT: v_pk_add_u16 v3, v3, v4 +; GFX9-NEXT: v_pk_add_u16 v0, v0, v4 clamp +; GFX9-NEXT: v_pk_add_u16 v1, v1, v5 clamp +; GFX9-NEXT: v_pk_add_u16 v2, v2, v6 clamp +; GFX9-NEXT: v_pk_add_u16 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_uaddsat_v8i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, -1, -1 +; GFX10-NEXT: v_pk_add_u16 v0, v0, v4 clamp +; GFX10-NEXT: v_pk_add_u16 v1, v1, v5 clamp +; GFX10-NEXT: v_pk_add_u16 v2, v2, v6 clamp +; GFX10-NEXT: v_pk_add_u16 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_xor_b32_e32 v15, s4, v0 -; GFX10-NEXT: v_xor_b32_e32 v19, s4, v1 -; GFX10-NEXT: v_xor_b32_e32 v23, s4, v2 -; GFX10-NEXT: v_xor_b32_e32 v10, s4, v3 -; GFX10-NEXT: v_pk_min_u16 v11, v15, v4 -; GFX10-NEXT: v_pk_min_u16 v15, v19, v5 -; GFX10-NEXT: v_pk_min_u16 v19, v23, v6 -; GFX10-NEXT: v_pk_min_u16 v6, v10, v7 -; GFX10-NEXT: v_pk_add_u16 v0, v0, v11 -; GFX10-NEXT: v_pk_add_u16 v1, v1, v15 -; GFX10-NEXT: v_pk_add_u16 v2, v2, v19 -; GFX10-NEXT: v_pk_add_u16 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x float> @@ -2819,212 +2100,72 @@ ; ; GFX8-LABEL: s_uaddsat_v8i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_mov_b32 s16, 0xffff -; GFX8-NEXT: s_xor_b32 s17, s0, s16 ; GFX8-NEXT: s_lshr_b32 s12, s4, 16 +; GFX8-NEXT: s_lshr_b32 s13, s5, 16 ; GFX8-NEXT: s_lshr_b32 s8, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s12 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: s_lshr_b32 s14, s6, 16 +; GFX8-NEXT: s_lshr_b32 s15, s7, 16 ; GFX8-NEXT: s_lshr_b32 s9, s1, 16 +; GFX8-NEXT: v_mov_b32_e32 v3, s13 +; GFX8-NEXT: v_add_u16_e64 v1, s8, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v8, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: s_lshr_b32 s10, s2, 16 +; GFX8-NEXT: v_mov_b32_e32 v5, s14 ; GFX8-NEXT: s_lshr_b32 s11, s3, 16 -; GFX8-NEXT: s_lshr_b32 s13, s5, 16 -; GFX8-NEXT: s_lshr_b32 s14, s6, 16 -; GFX8-NEXT: s_lshr_b32 s15, s7, 16 -; GFX8-NEXT: s_bfe_u32 s17, s17, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s17, s4 -; GFX8-NEXT: s_cselect_b32 s4, s17, s4 -; GFX8-NEXT: s_add_i32 s0, s0, s4 -; GFX8-NEXT: s_xor_b32 s4, s8, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s12, s12, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s12 -; GFX8-NEXT: s_cselect_b32 s4, s4, s12 -; GFX8-NEXT: s_add_i32 s8, s8, s4 -; GFX8-NEXT: s_xor_b32 s4, s1, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s1, s1, s4 -; GFX8-NEXT: s_xor_b32 s4, s9, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s13, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s9, s9, s4 -; GFX8-NEXT: s_xor_b32 s4, s2, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s6, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s2, s2, s4 -; GFX8-NEXT: s_xor_b32 s4, s10, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s14, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s10, s10, s4 -; GFX8-NEXT: s_xor_b32 s4, s3, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s7, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s3, s3, s4 -; GFX8-NEXT: s_xor_b32 s4, s11, s16 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s15, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s5 -; GFX8-NEXT: s_cselect_b32 s4, s4, s5 -; GFX8-NEXT: s_add_i32 s11, s11, s4 -; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s4 -; GFX8-NEXT: s_bfe_u32 s4, s9, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s4 -; GFX8-NEXT: s_bfe_u32 s4, s10, 0x100000 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s2, s2, s4 -; GFX8-NEXT: s_bfe_u32 s4, s11, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v7, s15 +; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v3, s9, v3 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, s6 +; GFX8-NEXT: v_mov_b32_e32 v6, s7 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v7, s11, v7 clamp +; GFX8-NEXT: v_add_u16_e64 v5, s10, v5 clamp +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_add_u16_e64 v4, s2, v4 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_add_u16_e64 v6, s3, v6 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_uaddsat_v8i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_pack_ll_b32_b16 s8, -1, -1 -; GFX9-NEXT: s_xor_b32 s9, s0, s8 -; GFX9-NEXT: s_mov_b32 s11, 0xffff -; GFX9-NEXT: s_lshr_b32 s10, s9, 16 -; GFX9-NEXT: s_lshr_b32 s12, s4, 16 -; GFX9-NEXT: s_and_b32 s9, s9, s11 -; GFX9-NEXT: s_and_b32 s4, s4, s11 -; GFX9-NEXT: s_cmp_lt_u32 s9, s4 -; GFX9-NEXT: s_cselect_b32 s4, s9, s4 -; GFX9-NEXT: s_cmp_lt_u32 s10, s12 -; GFX9-NEXT: s_cselect_b32 s9, s10, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s9 -; GFX9-NEXT: s_lshr_b32 s9, s0, 16 -; GFX9-NEXT: s_lshr_b32 s10, s4, 16 -; GFX9-NEXT: s_add_i32 s0, s0, s4 -; GFX9-NEXT: s_add_i32 s9, s9, s10 -; GFX9-NEXT: s_xor_b32 s4, s1, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s9 -; GFX9-NEXT: s_lshr_b32 s9, s4, 16 -; GFX9-NEXT: s_lshr_b32 s10, s5, 16 -; GFX9-NEXT: s_and_b32 s4, s4, s11 -; GFX9-NEXT: s_and_b32 s5, s5, s11 -; GFX9-NEXT: s_cmp_lt_u32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_u32 s9, s10 -; GFX9-NEXT: s_cselect_b32 s5, s9, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s1, 16 -; GFX9-NEXT: s_lshr_b32 s9, s4, 16 -; GFX9-NEXT: s_add_i32 s1, s1, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s9 -; GFX9-NEXT: s_xor_b32 s4, s2, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_lshr_b32 s9, s6, 16 -; GFX9-NEXT: s_and_b32 s4, s4, s11 -; GFX9-NEXT: s_and_b32 s6, s6, s11 -; GFX9-NEXT: s_cmp_lt_u32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s4, s4, s6 -; GFX9-NEXT: s_cmp_lt_u32 s5, s9 -; GFX9-NEXT: s_cselect_b32 s5, s5, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s2, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_add_i32 s2, s2, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s6 -; GFX9-NEXT: s_xor_b32 s4, s3, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_lshr_b32 s6, s7, 16 -; GFX9-NEXT: s_and_b32 s4, s4, s11 -; GFX9-NEXT: s_and_b32 s7, s7, s11 -; GFX9-NEXT: s_cmp_lt_u32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s4, s4, s7 -; GFX9-NEXT: s_cmp_lt_u32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_add_i32 s3, s3, s4 -; GFX9-NEXT: s_add_i32 s5, s5, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_add_u16 v2, s2, v2 clamp +; GFX9-NEXT: v_pk_add_u16 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_uaddsat_v8i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_pack_ll_b32_b16 s8, -1, -1 -; GFX10-NEXT: s_mov_b32 s10, 0xffff -; GFX10-NEXT: s_xor_b32 s9, s0, s8 -; GFX10-NEXT: s_and_b32 s12, s4, s10 -; GFX10-NEXT: s_lshr_b32 s11, s9, 16 -; GFX10-NEXT: s_and_b32 s9, s9, s10 -; GFX10-NEXT: s_lshr_b32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_u32 s9, s12 +; GFX10-NEXT: v_pk_add_u16 v0, s0, s4 clamp +; GFX10-NEXT: v_pk_add_u16 v1, s1, s5 clamp +; GFX10-NEXT: v_pk_add_u16 v2, s2, s6 clamp +; GFX10-NEXT: v_pk_add_u16 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s9, s9, s12 -; GFX10-NEXT: s_cmp_lt_u32 s11, s4 -; GFX10-NEXT: s_cselect_b32 s4, s11, s4 -; GFX10-NEXT: s_and_b32 s12, s5, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s9, s4 -; GFX10-NEXT: s_lshr_b32 s9, s0, 16 -; GFX10-NEXT: s_lshr_b32 s11, s4, 16 -; GFX10-NEXT: s_add_i32 s0, s0, s4 -; GFX10-NEXT: s_xor_b32 s4, s1, s8 -; GFX10-NEXT: s_add_i32 s9, s9, s11 -; GFX10-NEXT: s_lshr_b32 s11, s4, 16 -; GFX10-NEXT: s_and_b32 s4, s4, s10 -; GFX10-NEXT: s_lshr_b32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_u32 s4, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s9 -; GFX10-NEXT: s_cselect_b32 s4, s4, s12 -; GFX10-NEXT: s_cmp_lt_u32 s11, s5 -; GFX10-NEXT: s_cselect_b32 s5, s11, s5 -; GFX10-NEXT: s_and_b32 s12, s6, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX10-NEXT: s_lshr_b32 s5, s1, 16 -; GFX10-NEXT: s_lshr_b32 s11, s4, 16 -; GFX10-NEXT: s_add_i32 s1, s1, s4 -; GFX10-NEXT: s_xor_b32 s4, s2, s8 -; GFX10-NEXT: s_add_i32 s5, s5, s11 -; GFX10-NEXT: s_lshr_b32 s11, s4, 16 -; GFX10-NEXT: s_and_b32 s4, s4, s10 -; GFX10-NEXT: s_lshr_b32 s6, s6, 16 -; GFX10-NEXT: s_cmp_lt_u32 s4, s12 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX10-NEXT: s_cselect_b32 s4, s4, s12 -; GFX10-NEXT: s_cmp_lt_u32 s11, s6 -; GFX10-NEXT: s_cselect_b32 s6, s11, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6 -; GFX10-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-NEXT: s_lshr_b32 s11, s4, 16 -; GFX10-NEXT: s_add_i32 s2, s2, s4 -; GFX10-NEXT: s_xor_b32 s4, s3, s8 -; GFX10-NEXT: s_add_i32 s6, s6, s11 -; GFX10-NEXT: s_lshr_b32 s8, s4, 16 -; GFX10-NEXT: s_and_b32 s4, s4, s10 -; GFX10-NEXT: s_and_b32 s10, s7, s10 -; GFX10-NEXT: s_lshr_b32 s7, s7, 16 -; GFX10-NEXT: s_cmp_lt_u32 s4, s10 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX10-NEXT: s_cselect_b32 s4, s4, s10 -; GFX10-NEXT: s_cmp_lt_u32 s8, s7 -; GFX10-NEXT: s_cselect_b32 s7, s8, s7 -; GFX10-NEXT: s_lshr_b32 s5, s3, 16 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s7 -; GFX10-NEXT: s_lshr_b32 s7, s4, 16 -; GFX10-NEXT: s_add_i32 s3, s3, s4 -; GFX10-NEXT: s_add_i32 s5, s5, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x i32> Index: llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll @@ -20,8 +20,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX8-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -30,8 +29,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1 -; GFX9-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -42,8 +40,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u16_e64 v1, v0, v1 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs) @@ -66,13 +63,10 @@ ; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2 -; GFX8-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s1 -; GFX8-NEXT: s_cselect_b32 s1, s3, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshr_b32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_i7: @@ -80,28 +74,21 @@ ; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 ; GFX9-NEXT: s_lshl_b32 s0, s0, s2 -; GFX9-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX9-NEXT: s_lshr_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_i7: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_lshl_b32 s1, s1, s2 ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX10-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX10-NEXT: s_cmp_lt_u32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX10-NEXT: s_lshr_b32 s0, s0, s2 +; GFX10-NEXT: s_lshl_b32 s1, s1, s2 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs) ret i7 %result @@ -123,8 +110,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX8-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -133,8 +119,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1 -; GFX9-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -145,8 +130,7 @@ ; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u16_e64 v1, v0, v1 -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs) @@ -169,13 +153,10 @@ ; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX8-NEXT: s_lshl_b32 s1, s1, s2 ; GFX8-NEXT: s_lshl_b32 s0, s0, s2 -; GFX8-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s1 -; GFX8-NEXT: s_cselect_b32 s1, s3, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshr_b32 s0, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_i8: @@ -183,28 +164,21 @@ ; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX9-NEXT: s_lshl_b32 s1, s1, s2 ; GFX9-NEXT: s_lshl_b32 s0, s0, s2 -; GFX9-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s3, s1 -; GFX9-NEXT: s_cselect_b32 s1, s3, s1 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX9-NEXT: s_lshr_b32 s0, s0, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_i8: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_lshl_b32 s1, s1, s2 ; GFX10-NEXT: s_lshl_b32 s0, s0, s2 -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX10-NEXT: s_bfe_u32 s3, s0, 0x100000 -; GFX10-NEXT: s_cmp_lt_u32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX10-NEXT: s_lshr_b32 s0, s0, s2 +; GFX10-NEXT: s_lshl_b32 s1, s1, s2 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs) ret i8 %result @@ -226,8 +200,7 @@ ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX8-NEXT: v_min_u32_e32 v1, v0, v1 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] ; @@ -236,8 +209,7 @@ ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_min_u32_e32 v1, v0, v1 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; @@ -248,8 +220,7 @@ ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_min_u32_e32 v1, v0, v1 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp ; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs) @@ -269,22 +240,22 @@ ; ; GFX8-LABEL: s_usubsat_i24: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_lshl_b32 s0, s0, 8 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8 -; GFX8-NEXT: s_cmp_lt_u32 s0, s1 -; GFX8-NEXT: s_cselect_b32 s1, s0, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 -; GFX8-NEXT: s_lshr_b32 s0, s0, 8 +; GFX8-NEXT: s_lshl_b32 s0, s0, 8 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_i24: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_lshl_b32 s0, s0, 8 ; GFX9-NEXT: s_lshl_b32 s1, s1, 8 -; GFX9-NEXT: s_cmp_lt_u32 s0, s1 -; GFX9-NEXT: s_cselect_b32 s1, s0, s1 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_lshr_b32 s0, s0, 8 +; GFX9-NEXT: s_lshl_b32 s0, s0, 8 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_i24: @@ -292,10 +263,9 @@ ; GFX10-NEXT: s_lshl_b32 s0, s0, 8 ; GFX10-NEXT: s_lshl_b32 s1, s1, 8 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s0, s1 -; GFX10-NEXT: s_cselect_b32 s1, s0, s1 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_lshr_b32 s0, s0, 8 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp +; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs) ret i24 %result @@ -312,24 +282,21 @@ ; GFX8-LABEL: v_usubsat_i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v1, v0, v1 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v1, v0, v1 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v1, v0, v1 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -345,24 +312,23 @@ ; ; GFX8-LABEL: s_usubsat_i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s1 -; GFX8-NEXT: s_cselect_b32 s1, s0, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s1 -; GFX9-NEXT: s_cselect_b32 s1, s0, s1 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s1 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s1, s0, s1 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) ret i32 %result @@ -377,21 +343,18 @@ ; ; GFX8-LABEL: usubsat_i32_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_min_u32_e32 v0, s0, v0 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_i32_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_u32_e32 v0, s0, v0 -; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_i32_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_u32_e32 v0, s0, v0 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -407,21 +370,18 @@ ; ; GFX8-LABEL: usubsat_i32_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_min_u32_e32 v1, s0, v0 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1 +; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], v0, s0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_i32_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_u32_e32 v1, s0, v0 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_i32_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_u32_e32 v1, s0, v0 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs) %cast = bitcast i32 %result to float @@ -441,30 +401,24 @@ ; GFX8-LABEL: v_usubsat_v2i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v2, v0, v2 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2 -; GFX8-NEXT: v_min_u32_e32 v2, v1, v3 -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v2 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v2i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v2, v0, v2 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2 -; GFX9-NEXT: v_min_u32_e32 v2, v1, v3 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v2 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v2i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v2, v0, v2 -; GFX10-NEXT: v_min_u32_e32 v3, v1, v3 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v2 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -483,33 +437,31 @@ ; ; GFX8-LABEL: s_usubsat_v2i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s2 -; GFX8-NEXT: s_cselect_b32 s2, s0, s2 -; GFX8-NEXT: s_sub_i32 s0, s0, s2 -; GFX8-NEXT: s_cmp_lt_u32 s1, s3 -; GFX8-NEXT: s_cselect_b32 s2, s1, s3 -; GFX8-NEXT: s_sub_i32 s1, s1, s2 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v2i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s2 -; GFX9-NEXT: s_cselect_b32 s2, s0, s2 -; GFX9-NEXT: s_sub_i32 s0, s0, s2 -; GFX9-NEXT: s_cmp_lt_u32 s1, s3 -; GFX9-NEXT: s_cselect_b32 s2, s1, s3 -; GFX9-NEXT: s_sub_i32 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v2i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s2 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s2 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s0, s2 -; GFX10-NEXT: s_sub_i32 s0, s0, s2 -; GFX10-NEXT: s_cmp_lt_u32 s1, s3 -; GFX10-NEXT: s_cselect_b32 s2, s1, s3 -; GFX10-NEXT: s_sub_i32 s1, s1, s2 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs) ret <2 x i32> %result @@ -530,36 +482,27 @@ ; GFX8-LABEL: v_usubsat_v3i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v3, v0, v3 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3 -; GFX8-NEXT: v_min_u32_e32 v3, v1, v4 -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3 -; GFX8-NEXT: v_min_u32_e32 v3, v2, v5 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v3i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v3, v0, v3 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 -; GFX9-NEXT: v_min_u32_e32 v3, v1, v4 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3 -; GFX9-NEXT: v_min_u32_e32 v3, v2, v5 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v3 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v4 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v3i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v3, v0, v3 -; GFX10-NEXT: v_min_u32_e32 v4, v1, v4 -; GFX10-NEXT: v_min_u32_e32 v5, v2, v5 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v3 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v4 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v3 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v4 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -581,42 +524,39 @@ ; ; GFX8-LABEL: s_usubsat_v3i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s3 -; GFX8-NEXT: s_cselect_b32 s3, s0, s3 -; GFX8-NEXT: s_sub_i32 s0, s0, s3 -; GFX8-NEXT: s_cmp_lt_u32 s1, s4 -; GFX8-NEXT: s_cselect_b32 s3, s1, s4 -; GFX8-NEXT: s_sub_i32 s1, s1, s3 -; GFX8-NEXT: s_cmp_lt_u32 s2, s5 -; GFX8-NEXT: s_cselect_b32 s3, s2, s5 -; GFX8-NEXT: s_sub_i32 s2, s2, s3 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_sub_u32_e64 v0, s[6:7], s0, v0 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v3i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s3 -; GFX9-NEXT: s_cselect_b32 s3, s0, s3 -; GFX9-NEXT: s_sub_i32 s0, s0, s3 -; GFX9-NEXT: s_cmp_lt_u32 s1, s4 -; GFX9-NEXT: s_cselect_b32 s3, s1, s4 -; GFX9-NEXT: s_sub_i32 s1, s1, s3 -; GFX9-NEXT: s_cmp_lt_u32 s2, s5 -; GFX9-NEXT: s_cselect_b32 s3, s2, s5 -; GFX9-NEXT: s_sub_i32 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v3i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s3 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s3 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s4 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s3, s0, s3 -; GFX10-NEXT: s_sub_i32 s0, s0, s3 -; GFX10-NEXT: s_cmp_lt_u32 s1, s4 -; GFX10-NEXT: s_cselect_b32 s3, s1, s4 -; GFX10-NEXT: s_sub_i32 s1, s1, s3 -; GFX10-NEXT: s_cmp_lt_u32 s2, s5 -; GFX10-NEXT: s_cselect_b32 s3, s2, s5 -; GFX10-NEXT: s_sub_i32 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs) ret <3 x i32> %result @@ -639,42 +579,30 @@ ; GFX8-LABEL: v_usubsat_v4i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v4, v0, v4 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4 -; GFX8-NEXT: v_min_u32_e32 v4, v1, v5 -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4 -; GFX8-NEXT: v_min_u32_e32 v4, v2, v6 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v4 -; GFX8-NEXT: v_min_u32_e32 v4, v3, v7 -; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v4 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v7 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v4i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v4, v0, v4 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4 -; GFX9-NEXT: v_min_u32_e32 v4, v1, v5 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v4 -; GFX9-NEXT: v_min_u32_e32 v4, v2, v6 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_min_u32_e32 v4, v3, v7 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v4 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v4 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v5 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v6 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v4i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v19, v2, v6 -; GFX10-NEXT: v_min_u32_e32 v11, v0, v4 -; GFX10-NEXT: v_min_u32_e32 v15, v1, v5 -; GFX10-NEXT: v_min_u32_e32 v6, v3, v7 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v4 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v5 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v6 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v19 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v11 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v15 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -699,51 +627,47 @@ ; ; GFX8-LABEL: s_usubsat_v4i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s4 -; GFX8-NEXT: s_cselect_b32 s4, s0, s4 -; GFX8-NEXT: s_sub_i32 s0, s0, s4 -; GFX8-NEXT: s_cmp_lt_u32 s1, s5 -; GFX8-NEXT: s_cselect_b32 s4, s1, s5 -; GFX8-NEXT: s_sub_i32 s1, s1, s4 -; GFX8-NEXT: s_cmp_lt_u32 s2, s6 -; GFX8-NEXT: s_cselect_b32 s4, s2, s6 -; GFX8-NEXT: s_sub_i32 s2, s2, s4 -; GFX8-NEXT: s_cmp_lt_u32 s3, s7 -; GFX8-NEXT: s_cselect_b32 s4, s3, s7 -; GFX8-NEXT: s_sub_i32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_mov_b32_e32 v2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_sub_u32_e64 v0, s[8:9], s0, v0 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v4i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s4 -; GFX9-NEXT: s_cselect_b32 s4, s0, s4 -; GFX9-NEXT: s_sub_i32 s0, s0, s4 -; GFX9-NEXT: s_cmp_lt_u32 s1, s5 -; GFX9-NEXT: s_cselect_b32 s4, s1, s5 -; GFX9-NEXT: s_sub_i32 s1, s1, s4 -; GFX9-NEXT: s_cmp_lt_u32 s2, s6 -; GFX9-NEXT: s_cselect_b32 s4, s2, s6 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_cmp_lt_u32 s3, s7 -; GFX9-NEXT: s_cselect_b32 s4, s3, s7 -; GFX9-NEXT: s_sub_i32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v4i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s4 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s4 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s5 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s6 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s4, s0, s4 -; GFX10-NEXT: s_sub_i32 s0, s0, s4 -; GFX10-NEXT: s_cmp_lt_u32 s1, s5 -; GFX10-NEXT: s_cselect_b32 s4, s1, s5 -; GFX10-NEXT: s_sub_i32 s1, s1, s4 -; GFX10-NEXT: s_cmp_lt_u32 s2, s6 -; GFX10-NEXT: s_cselect_b32 s4, s2, s6 -; GFX10-NEXT: s_sub_i32 s2, s2, s4 -; GFX10-NEXT: s_cmp_lt_u32 s3, s7 -; GFX10-NEXT: s_cselect_b32 s4, s3, s7 -; GFX10-NEXT: s_sub_i32 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs) ret <4 x i32> %result @@ -768,47 +692,32 @@ ; GFX8-LABEL: v_usubsat_v5i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v5, v0, v5 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5 -; GFX8-NEXT: v_min_u32_e32 v5, v1, v6 -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5 -; GFX8-NEXT: v_min_u32_e32 v5, v2, v7 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5 -; GFX8-NEXT: v_min_u32_e32 v5, v3, v8 -; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v5 -; GFX8-NEXT: v_min_u32_e32 v5, v4, v9 -; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v5 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v5 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v6 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v7 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v8 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v9 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v5i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v5, v0, v5 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v5 -; GFX9-NEXT: v_min_u32_e32 v5, v1, v6 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5 -; GFX9-NEXT: v_min_u32_e32 v5, v2, v7 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v5 -; GFX9-NEXT: v_min_u32_e32 v5, v3, v8 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_min_u32_e32 v5, v4, v9 -; GFX9-NEXT: v_sub_u32_e32 v4, v4, v5 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v5 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v6 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v7 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v8 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, v4, v9 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v5i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v5, v0, v5 -; GFX10-NEXT: v_min_u32_e32 v6, v1, v6 -; GFX10-NEXT: v_min_u32_e32 v7, v2, v7 -; GFX10-NEXT: v_min_u32_e32 v8, v3, v8 -; GFX10-NEXT: v_min_u32_e32 v9, v4, v9 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v5 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v6 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v7 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v8 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v9 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v5 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v6 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v7 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v8 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v9 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) @@ -837,60 +746,55 @@ ; ; GFX8-LABEL: s_usubsat_v5i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s5 -; GFX8-NEXT: s_cselect_b32 s5, s0, s5 -; GFX8-NEXT: s_sub_i32 s0, s0, s5 -; GFX8-NEXT: s_cmp_lt_u32 s1, s6 -; GFX8-NEXT: s_cselect_b32 s5, s1, s6 -; GFX8-NEXT: s_sub_i32 s1, s1, s5 -; GFX8-NEXT: s_cmp_lt_u32 s2, s7 -; GFX8-NEXT: s_cselect_b32 s5, s2, s7 -; GFX8-NEXT: s_sub_i32 s2, s2, s5 -; GFX8-NEXT: s_cmp_lt_u32 s3, s8 -; GFX8-NEXT: s_cselect_b32 s5, s3, s8 -; GFX8-NEXT: s_sub_i32 s3, s3, s5 -; GFX8-NEXT: s_cmp_lt_u32 s4, s9 -; GFX8-NEXT: s_cselect_b32 s5, s4, s9 -; GFX8-NEXT: s_sub_i32 s4, s4, s5 +; GFX8-NEXT: v_mov_b32_e32 v0, s5 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: v_mov_b32_e32 v2, s7 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: v_mov_b32_e32 v4, s9 +; GFX8-NEXT: v_sub_u32_e64 v0, s[10:11], s0, v0 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[0:1], s4, v4 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v4 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v5i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s5 -; GFX9-NEXT: s_cselect_b32 s5, s0, s5 -; GFX9-NEXT: s_sub_i32 s0, s0, s5 -; GFX9-NEXT: s_cmp_lt_u32 s1, s6 -; GFX9-NEXT: s_cselect_b32 s5, s1, s6 -; GFX9-NEXT: s_sub_i32 s1, s1, s5 -; GFX9-NEXT: s_cmp_lt_u32 s2, s7 -; GFX9-NEXT: s_cselect_b32 s5, s2, s7 -; GFX9-NEXT: s_sub_i32 s2, s2, s5 -; GFX9-NEXT: s_cmp_lt_u32 s3, s8 -; GFX9-NEXT: s_cselect_b32 s5, s3, s8 -; GFX9-NEXT: s_sub_i32 s3, s3, s5 -; GFX9-NEXT: s_cmp_lt_u32 s4, s9 -; GFX9-NEXT: s_cselect_b32 s5, s4, s9 -; GFX9-NEXT: s_sub_i32 s4, s4, s5 +; GFX9-NEXT: v_mov_b32_e32 v0, s5 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_mov_b32_e32 v2, s7 +; GFX9-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v5i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s5 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s5, s0, s5 -; GFX10-NEXT: s_sub_i32 s0, s0, s5 -; GFX10-NEXT: s_cmp_lt_u32 s1, s6 -; GFX10-NEXT: s_cselect_b32 s5, s1, s6 -; GFX10-NEXT: s_sub_i32 s1, s1, s5 -; GFX10-NEXT: s_cmp_lt_u32 s2, s7 -; GFX10-NEXT: s_cselect_b32 s5, s2, s7 -; GFX10-NEXT: s_sub_i32 s2, s2, s5 -; GFX10-NEXT: s_cmp_lt_u32 s3, s8 -; GFX10-NEXT: s_cselect_b32 s5, s3, s8 -; GFX10-NEXT: s_sub_i32 s3, s3, s5 -; GFX10-NEXT: s_cmp_lt_u32 s4, s9 -; GFX10-NEXT: s_cselect_b32 s5, s4, s9 -; GFX10-NEXT: s_sub_i32 s4, s4, s5 ; GFX10-NEXT: ; return to shader part epilog %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs) ret <5 x i32> %result @@ -937,113 +841,65 @@ ; GFX8-LABEL: v_usubsat_v16i32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u32_e32 v16, v0, v16 -; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v1, v17 -; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v2, v18 -; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v3, v19 -; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v4, v20 -; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v5, v21 -; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v6, v22 -; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v7, v23 -; GFX8-NEXT: v_sub_u32_e32 v7, vcc, v7, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v8, v24 -; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v8, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v9, v25 -; GFX8-NEXT: v_sub_u32_e32 v9, vcc, v9, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v10, v26 -; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v10, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v11, v27 -; GFX8-NEXT: v_sub_u32_e32 v11, vcc, v11, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v12, v28 -; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v12, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v13, v29 -; GFX8-NEXT: v_sub_u32_e32 v13, vcc, v13, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v14, v30 -; GFX8-NEXT: v_sub_u32_e32 v14, vcc, v14, v16 -; GFX8-NEXT: v_min_u32_e32 v16, v15, v31 -; GFX8-NEXT: v_sub_u32_e32 v15, vcc, v15, v16 +; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v19 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v20 clamp +; GFX8-NEXT: v_sub_u32_e64 v5, s[4:5], v5, v21 clamp +; GFX8-NEXT: v_sub_u32_e64 v6, s[4:5], v6, v22 clamp +; GFX8-NEXT: v_sub_u32_e64 v7, s[4:5], v7, v23 clamp +; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v8, v24 clamp +; GFX8-NEXT: v_sub_u32_e64 v9, s[4:5], v9, v25 clamp +; GFX8-NEXT: v_sub_u32_e64 v10, s[4:5], v10, v26 clamp +; GFX8-NEXT: v_sub_u32_e64 v11, s[4:5], v11, v27 clamp +; GFX8-NEXT: v_sub_u32_e64 v12, s[4:5], v12, v28 clamp +; GFX8-NEXT: v_sub_u32_e64 v13, s[4:5], v13, v29 clamp +; GFX8-NEXT: v_sub_u32_e64 v14, s[4:5], v14, v30 clamp +; GFX8-NEXT: v_sub_u32_e64 v15, s[4:5], v15, v31 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v16i32: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u32_e32 v16, v0, v16 -; GFX9-NEXT: v_sub_u32_e32 v0, v0, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v1, v17 -; GFX9-NEXT: v_sub_u32_e32 v1, v1, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v2, v18 -; GFX9-NEXT: v_sub_u32_e32 v2, v2, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v3, v19 -; GFX9-NEXT: v_sub_u32_e32 v3, v3, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v4, v20 -; GFX9-NEXT: v_sub_u32_e32 v4, v4, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v5, v21 -; GFX9-NEXT: v_sub_u32_e32 v5, v5, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v6, v22 -; GFX9-NEXT: v_sub_u32_e32 v6, v6, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v7, v23 -; GFX9-NEXT: v_sub_u32_e32 v7, v7, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v8, v24 -; GFX9-NEXT: v_sub_u32_e32 v8, v8, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v9, v25 -; GFX9-NEXT: v_sub_u32_e32 v9, v9, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v10, v26 -; GFX9-NEXT: v_sub_u32_e32 v10, v10, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v11, v27 -; GFX9-NEXT: v_sub_u32_e32 v11, v11, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v12, v28 -; GFX9-NEXT: v_sub_u32_e32 v12, v12, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v13, v29 -; GFX9-NEXT: v_sub_u32_e32 v13, v13, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v14, v30 -; GFX9-NEXT: v_sub_u32_e32 v14, v14, v16 -; GFX9-NEXT: v_min_u32_e32 v16, v15, v31 -; GFX9-NEXT: v_sub_u32_e32 v15, v15, v16 +; GFX9-NEXT: v_sub_u32_e64 v0, v0, v16 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, v1, v17 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, v2, v18 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, v3, v19 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, v4, v20 clamp +; GFX9-NEXT: v_sub_u32_e64 v5, v5, v21 clamp +; GFX9-NEXT: v_sub_u32_e64 v6, v6, v22 clamp +; GFX9-NEXT: v_sub_u32_e64 v7, v7, v23 clamp +; GFX9-NEXT: v_sub_u32_e64 v8, v8, v24 clamp +; GFX9-NEXT: v_sub_u32_e64 v9, v9, v25 clamp +; GFX9-NEXT: v_sub_u32_e64 v10, v10, v26 clamp +; GFX9-NEXT: v_sub_u32_e64 v11, v11, v27 clamp +; GFX9-NEXT: v_sub_u32_e64 v12, v12, v28 clamp +; GFX9-NEXT: v_sub_u32_e64 v13, v13, v29 clamp +; GFX9-NEXT: v_sub_u32_e64 v14, v14, v30 clamp +; GFX9-NEXT: v_sub_u32_e64 v15, v15, v31 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v16i32: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u32_e32 v35, v0, v16 -; GFX10-NEXT: v_min_u32_e32 v16, v1, v17 -; GFX10-NEXT: v_min_u32_e32 v17, v2, v18 -; GFX10-NEXT: v_min_u32_e32 v18, v3, v19 -; GFX10-NEXT: v_min_u32_e32 v19, v4, v20 -; GFX10-NEXT: v_min_u32_e32 v20, v5, v21 -; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v16 -; GFX10-NEXT: v_min_u32_e32 v16, v6, v22 -; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v17 -; GFX10-NEXT: v_min_u32_e32 v17, v7, v23 -; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v18 -; GFX10-NEXT: v_min_u32_e32 v18, v8, v24 -; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v19 -; GFX10-NEXT: v_min_u32_e32 v19, v9, v25 -; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v20 -; GFX10-NEXT: v_min_u32_e32 v20, v10, v26 -; GFX10-NEXT: v_sub_nc_u32_e32 v6, v6, v16 -; GFX10-NEXT: v_min_u32_e32 v16, v11, v27 -; GFX10-NEXT: v_sub_nc_u32_e32 v7, v7, v17 -; GFX10-NEXT: v_min_u32_e32 v17, v12, v28 -; GFX10-NEXT: v_sub_nc_u32_e32 v8, v8, v18 -; GFX10-NEXT: v_min_u32_e32 v18, v13, v29 -; GFX10-NEXT: v_sub_nc_u32_e32 v9, v9, v19 -; GFX10-NEXT: v_min_u32_e32 v19, v14, v30 -; GFX10-NEXT: v_sub_nc_u32_e32 v10, v10, v20 -; GFX10-NEXT: v_min_u32_e32 v20, v15, v31 -; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v35 -; GFX10-NEXT: v_sub_nc_u32_e32 v11, v11, v16 -; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v17 -; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v18 -; GFX10-NEXT: v_sub_nc_u32_e32 v14, v14, v19 -; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v20 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) @@ -1105,159 +961,143 @@ ; ; GFX8-LABEL: s_usubsat_v16i32: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_cmp_lt_u32 s0, s16 -; GFX8-NEXT: s_cselect_b32 s16, s0, s16 -; GFX8-NEXT: s_sub_i32 s0, s0, s16 -; GFX8-NEXT: s_cmp_lt_u32 s1, s17 -; GFX8-NEXT: s_cselect_b32 s16, s1, s17 -; GFX8-NEXT: s_sub_i32 s1, s1, s16 -; GFX8-NEXT: s_cmp_lt_u32 s2, s18 -; GFX8-NEXT: s_cselect_b32 s16, s2, s18 -; GFX8-NEXT: s_sub_i32 s2, s2, s16 -; GFX8-NEXT: s_cmp_lt_u32 s3, s19 -; GFX8-NEXT: s_cselect_b32 s16, s3, s19 -; GFX8-NEXT: s_sub_i32 s3, s3, s16 -; GFX8-NEXT: s_cmp_lt_u32 s4, s20 -; GFX8-NEXT: s_cselect_b32 s16, s4, s20 -; GFX8-NEXT: s_sub_i32 s4, s4, s16 -; GFX8-NEXT: s_cmp_lt_u32 s5, s21 -; GFX8-NEXT: s_cselect_b32 s16, s5, s21 -; GFX8-NEXT: s_sub_i32 s5, s5, s16 -; GFX8-NEXT: s_cmp_lt_u32 s6, s22 -; GFX8-NEXT: s_cselect_b32 s16, s6, s22 -; GFX8-NEXT: s_sub_i32 s6, s6, s16 -; GFX8-NEXT: s_cmp_lt_u32 s7, s23 -; GFX8-NEXT: s_cselect_b32 s16, s7, s23 -; GFX8-NEXT: s_sub_i32 s7, s7, s16 -; GFX8-NEXT: s_cmp_lt_u32 s8, s24 -; GFX8-NEXT: s_cselect_b32 s16, s8, s24 -; GFX8-NEXT: s_sub_i32 s8, s8, s16 -; GFX8-NEXT: s_cmp_lt_u32 s9, s25 -; GFX8-NEXT: s_cselect_b32 s16, s9, s25 -; GFX8-NEXT: s_sub_i32 s9, s9, s16 -; GFX8-NEXT: s_cmp_lt_u32 s10, s26 -; GFX8-NEXT: s_cselect_b32 s16, s10, s26 -; GFX8-NEXT: s_sub_i32 s10, s10, s16 -; GFX8-NEXT: s_cmp_lt_u32 s11, s27 -; GFX8-NEXT: s_cselect_b32 s16, s11, s27 -; GFX8-NEXT: s_sub_i32 s11, s11, s16 -; GFX8-NEXT: s_cmp_lt_u32 s12, s28 -; GFX8-NEXT: s_cselect_b32 s16, s12, s28 -; GFX8-NEXT: s_sub_i32 s12, s12, s16 -; GFX8-NEXT: s_cmp_lt_u32 s13, s29 -; GFX8-NEXT: s_cselect_b32 s16, s13, s29 -; GFX8-NEXT: s_sub_i32 s13, s13, s16 -; GFX8-NEXT: s_cmp_lt_u32 s14, s30 -; GFX8-NEXT: s_cselect_b32 s16, s14, s30 -; GFX8-NEXT: s_sub_i32 s14, s14, s16 -; GFX8-NEXT: s_cmp_lt_u32 s15, s31 -; GFX8-NEXT: s_cselect_b32 s16, s15, s31 -; GFX8-NEXT: s_sub_i32 s15, s15, s16 +; GFX8-NEXT: v_mov_b32_e32 v0, s16 +; GFX8-NEXT: v_mov_b32_e32 v1, s17 +; GFX8-NEXT: v_mov_b32_e32 v2, s18 +; GFX8-NEXT: v_mov_b32_e32 v3, s19 +; GFX8-NEXT: v_mov_b32_e32 v4, s20 +; GFX8-NEXT: v_mov_b32_e32 v5, s21 +; GFX8-NEXT: v_mov_b32_e32 v6, s22 +; GFX8-NEXT: v_mov_b32_e32 v7, s23 +; GFX8-NEXT: v_mov_b32_e32 v8, s24 +; GFX8-NEXT: v_mov_b32_e32 v9, s25 +; GFX8-NEXT: v_mov_b32_e32 v10, s26 +; GFX8-NEXT: v_mov_b32_e32 v11, s27 +; GFX8-NEXT: v_mov_b32_e32 v12, s28 +; GFX8-NEXT: v_mov_b32_e32 v13, s29 +; GFX8-NEXT: v_mov_b32_e32 v14, s30 +; GFX8-NEXT: v_mov_b32_e32 v15, s31 +; GFX8-NEXT: v_sub_u32_e64 v0, s[32:33], s0, v0 clamp +; GFX8-NEXT: v_sub_u32_e64 v1, s[16:17], s1, v1 clamp +; GFX8-NEXT: v_sub_u32_e64 v2, s[16:17], s2, v2 clamp +; GFX8-NEXT: v_sub_u32_e64 v3, s[2:3], s3, v3 clamp +; GFX8-NEXT: v_sub_u32_e64 v4, s[2:3], s4, v4 clamp +; GFX8-NEXT: v_sub_u32_e64 v5, s[2:3], s5, v5 clamp +; GFX8-NEXT: v_sub_u32_e64 v6, s[2:3], s6, v6 clamp +; GFX8-NEXT: v_sub_u32_e64 v7, s[2:3], s7, v7 clamp +; GFX8-NEXT: v_sub_u32_e64 v8, s[2:3], s8, v8 clamp +; GFX8-NEXT: v_sub_u32_e64 v9, s[2:3], s9, v9 clamp +; GFX8-NEXT: v_sub_u32_e64 v10, s[2:3], s10, v10 clamp +; GFX8-NEXT: v_sub_u32_e64 v11, s[2:3], s11, v11 clamp +; GFX8-NEXT: v_sub_u32_e64 v12, s[2:3], s12, v12 clamp +; GFX8-NEXT: v_sub_u32_e64 v13, s[2:3], s13, v13 clamp +; GFX8-NEXT: v_sub_u32_e64 v14, s[2:3], s14, v14 clamp +; GFX8-NEXT: v_sub_u32_e64 v15, s[2:3], s15, v15 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 +; GFX8-NEXT: v_readfirstlane_b32 s4, v4 +; GFX8-NEXT: v_readfirstlane_b32 s5, v5 +; GFX8-NEXT: v_readfirstlane_b32 s6, v6 +; GFX8-NEXT: v_readfirstlane_b32 s7, v7 +; GFX8-NEXT: v_readfirstlane_b32 s8, v8 +; GFX8-NEXT: v_readfirstlane_b32 s9, v9 +; GFX8-NEXT: v_readfirstlane_b32 s10, v10 +; GFX8-NEXT: v_readfirstlane_b32 s11, v11 +; GFX8-NEXT: v_readfirstlane_b32 s12, v12 +; GFX8-NEXT: v_readfirstlane_b32 s13, v13 +; GFX8-NEXT: v_readfirstlane_b32 s14, v14 +; GFX8-NEXT: v_readfirstlane_b32 s15, v15 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v16i32: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_cmp_lt_u32 s0, s16 -; GFX9-NEXT: s_cselect_b32 s16, s0, s16 -; GFX9-NEXT: s_sub_i32 s0, s0, s16 -; GFX9-NEXT: s_cmp_lt_u32 s1, s17 -; GFX9-NEXT: s_cselect_b32 s16, s1, s17 -; GFX9-NEXT: s_sub_i32 s1, s1, s16 -; GFX9-NEXT: s_cmp_lt_u32 s2, s18 -; GFX9-NEXT: s_cselect_b32 s16, s2, s18 -; GFX9-NEXT: s_sub_i32 s2, s2, s16 -; GFX9-NEXT: s_cmp_lt_u32 s3, s19 -; GFX9-NEXT: s_cselect_b32 s16, s3, s19 -; GFX9-NEXT: s_sub_i32 s3, s3, s16 -; GFX9-NEXT: s_cmp_lt_u32 s4, s20 -; GFX9-NEXT: s_cselect_b32 s16, s4, s20 -; GFX9-NEXT: s_sub_i32 s4, s4, s16 -; GFX9-NEXT: s_cmp_lt_u32 s5, s21 -; GFX9-NEXT: s_cselect_b32 s16, s5, s21 -; GFX9-NEXT: s_sub_i32 s5, s5, s16 -; GFX9-NEXT: s_cmp_lt_u32 s6, s22 -; GFX9-NEXT: s_cselect_b32 s16, s6, s22 -; GFX9-NEXT: s_sub_i32 s6, s6, s16 -; GFX9-NEXT: s_cmp_lt_u32 s7, s23 -; GFX9-NEXT: s_cselect_b32 s16, s7, s23 -; GFX9-NEXT: s_sub_i32 s7, s7, s16 -; GFX9-NEXT: s_cmp_lt_u32 s8, s24 -; GFX9-NEXT: s_cselect_b32 s16, s8, s24 -; GFX9-NEXT: s_sub_i32 s8, s8, s16 -; GFX9-NEXT: s_cmp_lt_u32 s9, s25 -; GFX9-NEXT: s_cselect_b32 s16, s9, s25 -; GFX9-NEXT: s_sub_i32 s9, s9, s16 -; GFX9-NEXT: s_cmp_lt_u32 s10, s26 -; GFX9-NEXT: s_cselect_b32 s16, s10, s26 -; GFX9-NEXT: s_sub_i32 s10, s10, s16 -; GFX9-NEXT: s_cmp_lt_u32 s11, s27 -; GFX9-NEXT: s_cselect_b32 s16, s11, s27 -; GFX9-NEXT: s_sub_i32 s11, s11, s16 -; GFX9-NEXT: s_cmp_lt_u32 s12, s28 -; GFX9-NEXT: s_cselect_b32 s16, s12, s28 -; GFX9-NEXT: s_sub_i32 s12, s12, s16 -; GFX9-NEXT: s_cmp_lt_u32 s13, s29 -; GFX9-NEXT: s_cselect_b32 s16, s13, s29 -; GFX9-NEXT: s_sub_i32 s13, s13, s16 -; GFX9-NEXT: s_cmp_lt_u32 s14, s30 -; GFX9-NEXT: s_cselect_b32 s16, s14, s30 -; GFX9-NEXT: s_sub_i32 s14, s14, s16 -; GFX9-NEXT: s_cmp_lt_u32 s15, s31 -; GFX9-NEXT: s_cselect_b32 s16, s15, s31 -; GFX9-NEXT: s_sub_i32 s15, s15, s16 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: v_mov_b32_e32 v14, s30 +; GFX9-NEXT: v_mov_b32_e32 v15, s31 +; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp +; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp +; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp +; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp +; GFX9-NEXT: v_sub_u32_e64 v5, s5, v5 clamp +; GFX9-NEXT: v_sub_u32_e64 v6, s6, v6 clamp +; GFX9-NEXT: v_sub_u32_e64 v7, s7, v7 clamp +; GFX9-NEXT: v_sub_u32_e64 v8, s8, v8 clamp +; GFX9-NEXT: v_sub_u32_e64 v9, s9, v9 clamp +; GFX9-NEXT: v_sub_u32_e64 v10, s10, v10 clamp +; GFX9-NEXT: v_sub_u32_e64 v11, s11, v11 clamp +; GFX9-NEXT: v_sub_u32_e64 v12, s12, v12 clamp +; GFX9-NEXT: v_sub_u32_e64 v13, s13, v13 clamp +; GFX9-NEXT: v_sub_u32_e64 v14, s14, v14 clamp +; GFX9-NEXT: v_sub_u32_e64 v15, s15, v15 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 +; GFX9-NEXT: v_readfirstlane_b32 s4, v4 +; GFX9-NEXT: v_readfirstlane_b32 s5, v5 +; GFX9-NEXT: v_readfirstlane_b32 s6, v6 +; GFX9-NEXT: v_readfirstlane_b32 s7, v7 +; GFX9-NEXT: v_readfirstlane_b32 s8, v8 +; GFX9-NEXT: v_readfirstlane_b32 s9, v9 +; GFX9-NEXT: v_readfirstlane_b32 s10, v10 +; GFX9-NEXT: v_readfirstlane_b32 s11, v11 +; GFX9-NEXT: v_readfirstlane_b32 s12, v12 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v16i32: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_cmp_lt_u32 s0, s16 +; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp +; GFX10-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 +; GFX10-NEXT: v_readfirstlane_b32 s4, v4 +; GFX10-NEXT: v_readfirstlane_b32 s5, v5 +; GFX10-NEXT: v_readfirstlane_b32 s6, v6 +; GFX10-NEXT: v_readfirstlane_b32 s7, v7 +; GFX10-NEXT: v_readfirstlane_b32 s8, v8 +; GFX10-NEXT: v_readfirstlane_b32 s9, v9 +; GFX10-NEXT: v_readfirstlane_b32 s10, v10 +; GFX10-NEXT: v_readfirstlane_b32 s11, v11 +; GFX10-NEXT: v_readfirstlane_b32 s12, v12 +; GFX10-NEXT: v_readfirstlane_b32 s13, v13 +; GFX10-NEXT: v_readfirstlane_b32 s14, v14 +; GFX10-NEXT: v_readfirstlane_b32 s15, v15 ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s46, s0, s16 -; GFX10-NEXT: s_sub_i32 s0, s0, s46 -; GFX10-NEXT: s_cmp_lt_u32 s1, s17 -; GFX10-NEXT: s_cselect_b32 s46, s1, s17 -; GFX10-NEXT: s_sub_i32 s1, s1, s46 -; GFX10-NEXT: s_cmp_lt_u32 s2, s18 -; GFX10-NEXT: s_cselect_b32 s16, s2, s18 -; GFX10-NEXT: s_sub_i32 s2, s2, s16 -; GFX10-NEXT: s_cmp_lt_u32 s3, s19 -; GFX10-NEXT: s_cselect_b32 s16, s3, s19 -; GFX10-NEXT: s_sub_i32 s3, s3, s16 -; GFX10-NEXT: s_cmp_lt_u32 s4, s20 -; GFX10-NEXT: s_cselect_b32 s16, s4, s20 -; GFX10-NEXT: s_sub_i32 s4, s4, s16 -; GFX10-NEXT: s_cmp_lt_u32 s5, s21 -; GFX10-NEXT: s_cselect_b32 s16, s5, s21 -; GFX10-NEXT: s_sub_i32 s5, s5, s16 -; GFX10-NEXT: s_cmp_lt_u32 s6, s22 -; GFX10-NEXT: s_cselect_b32 s16, s6, s22 -; GFX10-NEXT: s_sub_i32 s6, s6, s16 -; GFX10-NEXT: s_cmp_lt_u32 s7, s23 -; GFX10-NEXT: s_cselect_b32 s16, s7, s23 -; GFX10-NEXT: s_sub_i32 s7, s7, s16 -; GFX10-NEXT: s_cmp_lt_u32 s8, s24 -; GFX10-NEXT: s_cselect_b32 s16, s8, s24 -; GFX10-NEXT: s_sub_i32 s8, s8, s16 -; GFX10-NEXT: s_cmp_lt_u32 s9, s25 -; GFX10-NEXT: s_cselect_b32 s16, s9, s25 -; GFX10-NEXT: s_sub_i32 s9, s9, s16 -; GFX10-NEXT: s_cmp_lt_u32 s10, s26 -; GFX10-NEXT: s_cselect_b32 s16, s10, s26 -; GFX10-NEXT: s_sub_i32 s10, s10, s16 -; GFX10-NEXT: s_cmp_lt_u32 s11, s27 -; GFX10-NEXT: s_cselect_b32 s16, s11, s27 -; GFX10-NEXT: s_sub_i32 s11, s11, s16 -; GFX10-NEXT: s_cmp_lt_u32 s12, s28 -; GFX10-NEXT: s_cselect_b32 s16, s12, s28 -; GFX10-NEXT: s_sub_i32 s12, s12, s16 -; GFX10-NEXT: s_cmp_lt_u32 s13, s29 -; GFX10-NEXT: s_cselect_b32 s16, s13, s29 -; GFX10-NEXT: s_sub_i32 s13, s13, s16 -; GFX10-NEXT: s_cmp_lt_u32 s14, s30 -; GFX10-NEXT: s_cselect_b32 s16, s14, s30 -; GFX10-NEXT: s_sub_i32 s14, s14, s16 -; GFX10-NEXT: s_cmp_lt_u32 s15, s31 -; GFX10-NEXT: s_cselect_b32 s16, s15, s31 -; GFX10-NEXT: s_sub_i32 s15, s15, s16 ; GFX10-NEXT: ; return to shader part epilog %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs) ret <16 x i32> %result @@ -1277,24 +1117,21 @@ ; GFX8-LABEL: v_usubsat_i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_min_u16_e32 v1, v0, v1 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_min_u16_e64 v1, v0, v1 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -1313,30 +1150,23 @@ ; ; GFX8-LABEL: s_usubsat_i16: ; GFX8: ; %bb.0: -; GFX8-NEXT: s_bfe_u32 s2, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s1 -; GFX8-NEXT: s_cselect_b32 s1, s2, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_bfe_u32 s2, s0, 0x100000 -; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX9-NEXT: s_cmp_lt_u32 s2, s1 -; GFX9-NEXT: s_cselect_b32 s1, s2, s1 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_bfe_u32 s2, s0, 0x100000 -; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cmp_lt_u32 s2, s1 -; GFX10-NEXT: s_cselect_b32 s1, s2, s1 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) ret i16 %result @@ -1354,21 +1184,18 @@ ; ; GFX8-LABEL: usubsat_i16_sv: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_min_u16_e32 v0, s0, v0 -; GFX8-NEXT: v_sub_u16_e32 v0, s0, v0 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_u16_e32 v0, s0, v0 -; GFX9-NEXT: v_sub_u16_e32 v0, s0, v0 +; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_u16_e64 v0, s0, v0 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -1387,21 +1214,18 @@ ; ; GFX8-LABEL: usubsat_i16_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_min_u16_e32 v1, s0, v0 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX8-NEXT: v_sub_u16_e64 v0, v0, s0 clamp ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_min_u16_e32 v1, s0, v0 -; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1 +; GFX9-NEXT: v_sub_u16_e64 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_min_u16_e64 v1, v0, s0 +; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs) %cast = bitcast i16 %result to half @@ -1427,28 +1251,25 @@ ; GFX8-LABEL: v_usubsat_v2i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX8-NEXT: v_min_u16_e32 v3, v0, v1 -; GFX8-NEXT: v_min_u16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v3 -; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v1, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v2i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_min_u16 v1, v0, v1 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v2i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_pk_min_u16 v1, v0, v1 +; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) ret <2 x i16> %result @@ -1480,57 +1301,28 @@ ; GFX8: ; %bb.0: ; GFX8-NEXT: s_lshr_b32 s3, s1, 16 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16 -; GFX8-NEXT: s_bfe_u32 s4, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s1 -; GFX8-NEXT: s_cselect_b32 s1, s4, s1 -; GFX8-NEXT: s_sub_i32 s0, s0, s1 -; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s1, s3 -; GFX8-NEXT: s_cselect_b32 s1, s1, s3 -; GFX8-NEXT: s_sub_i32 s1, s2, s1 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s1, s1, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mov_b32_e32 v0, s1 +; GFX8-NEXT: v_sub_u16_e64 v1, s2, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v2i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s3, 0xffff -; GFX9-NEXT: s_lshr_b32 s5, s1, 16 -; GFX9-NEXT: s_lshr_b32 s2, s0, 16 -; GFX9-NEXT: s_and_b32 s4, s0, s3 -; GFX9-NEXT: s_and_b32 s1, s1, s3 -; GFX9-NEXT: s_cmp_lt_u32 s4, s1 -; GFX9-NEXT: s_cselect_b32 s1, s4, s1 -; GFX9-NEXT: s_cmp_lt_u32 s2, s5 -; GFX9-NEXT: s_cselect_b32 s3, s2, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s1 -; GFX9-NEXT: s_sub_i32 s1, s2, s3 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v2i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_mov_b32 s2, 0xffff -; GFX10-NEXT: s_lshr_b32 s3, s0, 16 -; GFX10-NEXT: s_and_b32 s4, s0, s2 -; GFX10-NEXT: s_and_b32 s2, s1, s2 -; GFX10-NEXT: s_lshr_b32 s1, s1, 16 -; GFX10-NEXT: s_cmp_lt_u32 s4, s2 +; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s2, s4, s2 -; GFX10-NEXT: s_cmp_lt_u32 s3, s1 -; GFX10-NEXT: s_cselect_b32 s1, s3, s1 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1 -; GFX10-NEXT: s_lshr_b32 s2, s1, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s1 -; GFX10-NEXT: s_sub_i32 s1, s3, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to i32 @@ -1561,24 +1353,22 @@ ; GFX8: ; %bb.0: ; GFX8-NEXT: s_lshr_b32 s1, s0, 16 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: v_min_u16_e32 v1, s0, v0 -; GFX8-NEXT: v_min_u16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v1, s0, v1 -; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX8-NEXT: v_sub_u16_e64 v1, s0, v0 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_v2i16_sv: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_pk_min_u16 v0, s0, v0 -; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 +; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_v2i16_sv: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_pk_min_u16 v0, s0, v0 +; GFX10-NEXT: v_pk_sub_u16 v0, s0, v0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -1607,26 +1397,24 @@ ; ; GFX8-LABEL: usubsat_v2i16_vs: ; GFX8: ; %bb.0: -; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16 -; GFX8-NEXT: v_min_u16_e32 v2, s0, v0 -; GFX8-NEXT: v_min_u16_e32 v3, s1, v1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v2 -; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_sub_u16_e64 v1, v0, s0 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v2, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: usubsat_v2i16_vs: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_pk_min_u16 v1, v0, s0 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, s0 clamp ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: usubsat_v2i16_vs: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_pk_min_u16 v1, v0, s0 +; GFX10-NEXT: v_pk_sub_u16 v0, v0, s0 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs) %cast = bitcast <2 x i16> %result to float @@ -1682,38 +1470,31 @@ ; GFX8-LABEL: v_usubsat_v4i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0 -; GFX8-NEXT: v_min_u16_e32 v6, v0, v2 -; GFX8-NEXT: v_min_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1 -; GFX8-NEXT: v_min_u16_e32 v7, v1, v3 -; GFX8-NEXT: v_min_u16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v6 -; GFX8-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX8-NEXT: v_sub_u16_e32 v1, v1, v7 -; GFX8-NEXT: v_sub_u16_sdwa v2, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX8-NEXT: v_sub_u16_e64 v4, v0, v2 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v2, v1, v3 clamp +; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v3, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v4i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_min_u16 v2, v0, v2 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 -; GFX9-NEXT: v_pk_min_u16 v2, v1, v3 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v4i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_pk_min_u16 v2, v0, v2 -; GFX10-NEXT: v_pk_min_u16 v3, v1, v3 +; GFX10-NEXT: v_pk_sub_u16 v0, v0, v2 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, v1, v3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x float> @@ -1761,100 +1542,43 @@ ; GFX8-LABEL: s_usubsat_v4i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_lshr_b32 s6, s2, 16 +; GFX8-NEXT: s_lshr_b32 s7, s3, 16 ; GFX8-NEXT: s_lshr_b32 s4, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: s_lshr_b32 s5, s1, 16 -; GFX8-NEXT: s_lshr_b32 s7, s3, 16 -; GFX8-NEXT: s_bfe_u32 s8, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s8, s2 -; GFX8-NEXT: s_cselect_b32 s2, s8, s2 -; GFX8-NEXT: s_sub_i32 s0, s0, s2 -; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s2, s6 -; GFX8-NEXT: s_cselect_b32 s2, s2, s6 -; GFX8-NEXT: s_sub_i32 s2, s4, s2 -; GFX8-NEXT: s_bfe_u32 s4, s1, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s3 -; GFX8-NEXT: s_cselect_b32 s3, s4, s3 -; GFX8-NEXT: s_sub_i32 s1, s1, s3 -; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s4 -; GFX8-NEXT: s_cselect_b32 s3, s3, s4 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_sub_i32 s3, s5, s3 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s2, s2, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s2 -; GFX8-NEXT: s_bfe_u32 s2, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s2, s2, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_sub_u16_e64 v1, s4, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v3, s5, v3 clamp +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v4i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s5, 0xffff -; GFX9-NEXT: s_lshr_b32 s7, s2, 16 -; GFX9-NEXT: s_lshr_b32 s4, s0, 16 -; GFX9-NEXT: s_and_b32 s6, s0, s5 -; GFX9-NEXT: s_and_b32 s2, s2, s5 -; GFX9-NEXT: s_cmp_lt_u32 s6, s2 -; GFX9-NEXT: s_cselect_b32 s2, s6, s2 -; GFX9-NEXT: s_cmp_lt_u32 s4, s7 -; GFX9-NEXT: s_cselect_b32 s6, s4, s7 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX9-NEXT: s_lshr_b32 s6, s2, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s2 -; GFX9-NEXT: s_sub_i32 s2, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX9-NEXT: s_lshr_b32 s6, s3, 16 -; GFX9-NEXT: s_lshr_b32 s2, s1, 16 -; GFX9-NEXT: s_and_b32 s4, s1, s5 -; GFX9-NEXT: s_and_b32 s3, s3, s5 -; GFX9-NEXT: s_cmp_lt_u32 s4, s3 -; GFX9-NEXT: s_cselect_b32 s3, s4, s3 -; GFX9-NEXT: s_cmp_lt_u32 s2, s6 -; GFX9-NEXT: s_cselect_b32 s4, s2, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s3 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v4i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_mov_b32 s4, 0xffff -; GFX10-NEXT: s_lshr_b32 s5, s0, 16 -; GFX10-NEXT: s_and_b32 s7, s2, s4 -; GFX10-NEXT: s_and_b32 s6, s0, s4 -; GFX10-NEXT: s_lshr_b32 s2, s2, 16 -; GFX10-NEXT: s_cmp_lt_u32 s6, s7 +; GFX10-NEXT: v_pk_sub_u16 v0, s0, s2 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, s1, s3 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s6, s6, s7 -; GFX10-NEXT: s_cmp_lt_u32 s5, s2 -; GFX10-NEXT: s_cselect_b32 s2, s5, s2 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2 -; GFX10-NEXT: s_lshr_b32 s6, s2, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s2 -; GFX10-NEXT: s_sub_i32 s2, s5, s6 -; GFX10-NEXT: s_and_b32 s6, s1, s4 -; GFX10-NEXT: s_and_b32 s4, s3, s4 -; GFX10-NEXT: s_lshr_b32 s5, s1, 16 -; GFX10-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_u32 s6, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX10-NEXT: s_cselect_b32 s4, s6, s4 -; GFX10-NEXT: s_cmp_lt_u32 s5, s3 -; GFX10-NEXT: s_cselect_b32 s3, s5, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s3 -; GFX10-NEXT: s_lshr_b32 s4, s3, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s3 -; GFX10-NEXT: s_sub_i32 s3, s5, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 ; GFX10-NEXT: ; return to shader part epilog %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs) %cast = bitcast <4 x i16> %result to <2 x i32> @@ -1924,48 +1648,38 @@ ; GFX8-LABEL: v_usubsat_v6i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0 -; GFX8-NEXT: v_min_u16_e32 v9, v0, v3 -; GFX8-NEXT: v_min_u16_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1 -; GFX8-NEXT: v_min_u16_e32 v10, v1, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2 -; GFX8-NEXT: v_min_u16_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v9 -; GFX8-NEXT: v_sub_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v11, v2, v5 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v3 -; GFX8-NEXT: v_min_u16_sdwa v5, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v1, v1, v10 -; GFX8-NEXT: v_sub_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX8-NEXT: v_sub_u16_e32 v2, v2, v11 -; GFX8-NEXT: v_sub_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 +; GFX8-NEXT: v_sub_u16_e64 v6, v0, v3 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v3, v1, v4 clamp +; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v4, v2, v5 clamp +; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v5, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_mov_b32_e32 v3, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v6i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_min_u16 v3, v0, v3 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 -; GFX9-NEXT: v_pk_min_u16 v3, v1, v4 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 -; GFX9-NEXT: v_pk_min_u16 v3, v2, v5 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v3 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, v1, v4 clamp +; GFX9-NEXT: v_pk_sub_u16 v2, v2, v5 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v6i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_pk_min_u16 v3, v0, v3 -; GFX10-NEXT: v_pk_min_u16 v4, v1, v4 -; GFX10-NEXT: v_pk_min_u16 v5, v2, v5 +; GFX10-NEXT: v_pk_sub_u16 v0, v0, v3 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, v1, v4 clamp +; GFX10-NEXT: v_pk_sub_u16 v2, v2, v5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 -; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x float> @@ -2029,142 +1743,57 @@ ; GFX8-LABEL: s_usubsat_v6i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_lshr_b32 s9, s3, 16 +; GFX8-NEXT: s_lshr_b32 s10, s4, 16 ; GFX8-NEXT: s_lshr_b32 s6, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s9 +; GFX8-NEXT: v_mov_b32_e32 v0, s3 +; GFX8-NEXT: s_lshr_b32 s11, s5, 16 ; GFX8-NEXT: s_lshr_b32 s7, s1, 16 +; GFX8-NEXT: v_mov_b32_e32 v3, s10 +; GFX8-NEXT: v_sub_u16_e64 v1, s6, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v6, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: s_lshr_b32 s8, s2, 16 -; GFX8-NEXT: s_lshr_b32 s10, s4, 16 -; GFX8-NEXT: s_lshr_b32 s11, s5, 16 -; GFX8-NEXT: s_bfe_u32 s12, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s12, s3 -; GFX8-NEXT: s_cselect_b32 s3, s12, s3 -; GFX8-NEXT: s_sub_i32 s0, s0, s3 -; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000 -; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s3, s9 -; GFX8-NEXT: s_cselect_b32 s3, s3, s9 -; GFX8-NEXT: s_sub_i32 s3, s6, s3 -; GFX8-NEXT: s_bfe_u32 s6, s1, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s6, s4 -; GFX8-NEXT: s_cselect_b32 s4, s6, s4 -; GFX8-NEXT: s_sub_i32 s1, s1, s4 -; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000 -; GFX8-NEXT: s_bfe_u32 s6, s10, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s6 -; GFX8-NEXT: s_cselect_b32 s4, s4, s6 -; GFX8-NEXT: s_sub_i32 s4, s7, s4 -; GFX8-NEXT: s_bfe_u32 s6, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s6, s5 -; GFX8-NEXT: s_cselect_b32 s5, s6, s5 -; GFX8-NEXT: s_sub_i32 s2, s2, s5 -; GFX8-NEXT: s_bfe_u32 s5, s8, 0x100000 -; GFX8-NEXT: s_bfe_u32 s6, s11, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s5, s6 -; GFX8-NEXT: s_cselect_b32 s5, s5, s6 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s3 -; GFX8-NEXT: s_bfe_u32 s3, s4, 0x100000 -; GFX8-NEXT: s_sub_i32 s5, s8, s5 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s3 -; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_lshl_b32 s3, s3, 16 -; GFX8-NEXT: s_or_b32 s2, s2, s3 +; GFX8-NEXT: v_mov_b32_e32 v5, s11 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v3, s7, v3 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v5, s8, v5 clamp +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v6i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s7, 0xffff -; GFX9-NEXT: s_lshr_b32 s9, s3, 16 -; GFX9-NEXT: s_lshr_b32 s6, s0, 16 -; GFX9-NEXT: s_and_b32 s8, s0, s7 -; GFX9-NEXT: s_and_b32 s3, s3, s7 -; GFX9-NEXT: s_cmp_lt_u32 s8, s3 -; GFX9-NEXT: s_cselect_b32 s3, s8, s3 -; GFX9-NEXT: s_cmp_lt_u32 s6, s9 -; GFX9-NEXT: s_cselect_b32 s8, s6, s9 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8 -; GFX9-NEXT: s_lshr_b32 s8, s3, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s3 -; GFX9-NEXT: s_sub_i32 s3, s6, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3 -; GFX9-NEXT: s_lshr_b32 s8, s4, 16 -; GFX9-NEXT: s_lshr_b32 s3, s1, 16 -; GFX9-NEXT: s_and_b32 s6, s1, s7 -; GFX9-NEXT: s_and_b32 s4, s4, s7 -; GFX9-NEXT: s_cmp_lt_u32 s6, s4 -; GFX9-NEXT: s_cselect_b32 s4, s6, s4 -; GFX9-NEXT: s_cmp_lt_u32 s3, s8 -; GFX9-NEXT: s_cselect_b32 s6, s3, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s6 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s4 -; GFX9-NEXT: s_sub_i32 s3, s3, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3 -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: s_lshr_b32 s3, s2, 16 -; GFX9-NEXT: s_and_b32 s4, s2, s7 -; GFX9-NEXT: s_and_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_u32 s4, s5 -; GFX9-NEXT: s_cselect_b32 s4, s4, s5 -; GFX9-NEXT: s_cmp_lt_u32 s3, s6 -; GFX9-NEXT: s_cselect_b32 s5, s3, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5 -; GFX9-NEXT: s_lshr_b32 s5, s4, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s4 -; GFX9-NEXT: s_sub_i32 s3, s3, s5 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v6i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_mov_b32 s6, 0xffff -; GFX10-NEXT: s_lshr_b32 s7, s0, 16 -; GFX10-NEXT: s_and_b32 s9, s3, s6 -; GFX10-NEXT: s_and_b32 s8, s0, s6 -; GFX10-NEXT: s_lshr_b32 s3, s3, 16 -; GFX10-NEXT: s_cmp_lt_u32 s8, s9 +; GFX10-NEXT: v_pk_sub_u16 v0, s0, s3 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, s1, s4 clamp +; GFX10-NEXT: v_pk_sub_u16 v2, s2, s5 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s8, s8, s9 -; GFX10-NEXT: s_cmp_lt_u32 s7, s3 -; GFX10-NEXT: s_cselect_b32 s3, s7, s3 -; GFX10-NEXT: s_and_b32 s9, s4, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s8, s3 -; GFX10-NEXT: s_lshr_b32 s4, s4, 16 -; GFX10-NEXT: s_lshr_b32 s8, s3, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s3 -; GFX10-NEXT: s_sub_i32 s3, s7, s8 -; GFX10-NEXT: s_and_b32 s8, s1, s6 -; GFX10-NEXT: s_lshr_b32 s7, s1, 16 -; GFX10-NEXT: s_cmp_lt_u32 s8, s9 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3 -; GFX10-NEXT: s_cselect_b32 s8, s8, s9 -; GFX10-NEXT: s_cmp_lt_u32 s7, s4 -; GFX10-NEXT: s_cselect_b32 s4, s7, s4 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s4 -; GFX10-NEXT: s_lshr_b32 s8, s4, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s4 -; GFX10-NEXT: s_sub_i32 s4, s7, s8 -; GFX10-NEXT: s_and_b32 s8, s2, s6 -; GFX10-NEXT: s_and_b32 s6, s5, s6 -; GFX10-NEXT: s_lshr_b32 s7, s2, 16 -; GFX10-NEXT: s_lshr_b32 s5, s5, 16 -; GFX10-NEXT: s_cmp_lt_u32 s8, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX10-NEXT: s_cselect_b32 s6, s8, s6 -; GFX10-NEXT: s_cmp_lt_u32 s7, s5 -; GFX10-NEXT: s_cselect_b32 s5, s7, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s6, s5 -; GFX10-NEXT: s_lshr_b32 s3, s5, 16 -; GFX10-NEXT: s_sub_i32 s2, s2, s5 -; GFX10-NEXT: s_sub_i32 s3, s7, s3 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 ; GFX10-NEXT: ; return to shader part epilog %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs) %cast = bitcast <6 x i16> %result to <3 x i32> @@ -2237,58 +1866,44 @@ ; GFX8-LABEL: v_usubsat_v8i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0 -; GFX8-NEXT: v_min_u16_e32 v12, v0, v4 -; GFX8-NEXT: v_min_u16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1 -; GFX8-NEXT: v_min_u16_e32 v13, v1, v5 -; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2 -; GFX8-NEXT: v_min_u16_sdwa v5, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12 -; GFX8-NEXT: v_sub_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v14, v2, v6 -; GFX8-NEXT: v_or_b32_e32 v0, v0, v4 -; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3 -; GFX8-NEXT: v_min_u16_sdwa v6, v10, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v1, v1, v13 -; GFX8-NEXT: v_sub_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_min_u16_e32 v15, v3, v7 -; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 -; GFX8-NEXT: v_min_u16_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX8-NEXT: v_sub_u16_e32 v2, v2, v14 -; GFX8-NEXT: v_sub_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v2, v2, v4 -; GFX8-NEXT: v_sub_u16_e32 v3, v3, v15 -; GFX8-NEXT: v_sub_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GFX8-NEXT: v_or_b32_e32 v3, v3, v4 +; GFX8-NEXT: v_sub_u16_e64 v8, v0, v4 clamp +; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v4, v1, v5 clamp +; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v5, v2, v6 clamp +; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v6 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_sub_u16_e64 v6, v3, v7 clamp +; GFX8-NEXT: v_sub_u16_sdwa v3, v3, v7 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX8-NEXT: v_mov_b32_e32 v7, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_mov_b32_e32 v7, 16 +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: v_usubsat_v8i16: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_pk_min_u16 v4, v0, v4 -; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 -; GFX9-NEXT: v_pk_min_u16 v4, v1, v5 -; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 -; GFX9-NEXT: v_pk_min_u16 v4, v2, v6 -; GFX9-NEXT: v_pk_sub_i16 v2, v2, v4 -; GFX9-NEXT: v_pk_min_u16 v4, v3, v7 -; GFX9-NEXT: v_pk_sub_i16 v3, v3, v4 +; GFX9-NEXT: v_pk_sub_u16 v0, v0, v4 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, v1, v5 clamp +; GFX9-NEXT: v_pk_sub_u16 v2, v2, v6 clamp +; GFX9-NEXT: v_pk_sub_u16 v3, v3, v7 clamp ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: v_usubsat_v8i16: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_pk_min_u16 v19, v2, v6 -; GFX10-NEXT: v_pk_min_u16 v11, v0, v4 -; GFX10-NEXT: v_pk_min_u16 v15, v1, v5 -; GFX10-NEXT: v_pk_min_u16 v6, v3, v7 +; GFX10-NEXT: v_pk_sub_u16 v0, v0, v4 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, v1, v5 clamp +; GFX10-NEXT: v_pk_sub_u16 v2, v2, v6 clamp +; GFX10-NEXT: v_pk_sub_u16 v3, v3, v7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: v_pk_sub_i16 v2, v2, v19 -; GFX10-NEXT: v_pk_sub_i16 v0, v0, v11 -; GFX10-NEXT: v_pk_sub_i16 v1, v1, v15 -; GFX10-NEXT: v_pk_sub_i16 v3, v3, v6 ; GFX10-NEXT: s_setpc_b64 s[30:31] %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x float> @@ -2368,184 +1983,71 @@ ; GFX8-LABEL: s_usubsat_v8i16: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_lshr_b32 s12, s4, 16 +; GFX8-NEXT: s_lshr_b32 s13, s5, 16 ; GFX8-NEXT: s_lshr_b32 s8, s0, 16 +; GFX8-NEXT: v_mov_b32_e32 v1, s12 +; GFX8-NEXT: v_mov_b32_e32 v0, s4 +; GFX8-NEXT: s_lshr_b32 s14, s6, 16 +; GFX8-NEXT: s_lshr_b32 s15, s7, 16 ; GFX8-NEXT: s_lshr_b32 s9, s1, 16 +; GFX8-NEXT: v_mov_b32_e32 v3, s13 +; GFX8-NEXT: v_sub_u16_e64 v1, s8, v1 clamp +; GFX8-NEXT: v_mov_b32_e32 v8, 16 +; GFX8-NEXT: v_mov_b32_e32 v2, s5 ; GFX8-NEXT: s_lshr_b32 s10, s2, 16 +; GFX8-NEXT: v_mov_b32_e32 v5, s14 ; GFX8-NEXT: s_lshr_b32 s11, s3, 16 -; GFX8-NEXT: s_lshr_b32 s13, s5, 16 -; GFX8-NEXT: s_lshr_b32 s14, s6, 16 -; GFX8-NEXT: s_lshr_b32 s15, s7, 16 -; GFX8-NEXT: s_bfe_u32 s16, s0, 0x100000 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s16, s4 -; GFX8-NEXT: s_cselect_b32 s4, s16, s4 -; GFX8-NEXT: s_sub_i32 s0, s0, s4 -; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000 -; GFX8-NEXT: s_bfe_u32 s12, s12, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s4, s12 -; GFX8-NEXT: s_cselect_b32 s4, s4, s12 -; GFX8-NEXT: s_sub_i32 s4, s8, s4 -; GFX8-NEXT: s_bfe_u32 s8, s1, 0x100000 -; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s8, s5 -; GFX8-NEXT: s_cselect_b32 s5, s8, s5 -; GFX8-NEXT: s_sub_i32 s1, s1, s5 -; GFX8-NEXT: s_bfe_u32 s5, s9, 0x100000 -; GFX8-NEXT: s_bfe_u32 s8, s13, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s5, s8 -; GFX8-NEXT: s_cselect_b32 s5, s5, s8 -; GFX8-NEXT: s_sub_i32 s5, s9, s5 -; GFX8-NEXT: s_bfe_u32 s8, s2, 0x100000 -; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s8, s6 -; GFX8-NEXT: s_cselect_b32 s6, s8, s6 -; GFX8-NEXT: s_sub_i32 s2, s2, s6 -; GFX8-NEXT: s_bfe_u32 s6, s10, 0x100000 -; GFX8-NEXT: s_bfe_u32 s8, s14, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s6, s8 -; GFX8-NEXT: s_cselect_b32 s6, s6, s8 -; GFX8-NEXT: s_sub_i32 s6, s10, s6 -; GFX8-NEXT: s_bfe_u32 s8, s3, 0x100000 -; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s8, s7 -; GFX8-NEXT: s_cselect_b32 s7, s8, s7 -; GFX8-NEXT: s_sub_i32 s3, s3, s7 -; GFX8-NEXT: s_bfe_u32 s7, s11, 0x100000 -; GFX8-NEXT: s_bfe_u32 s8, s15, 0x100000 -; GFX8-NEXT: s_cmp_lt_u32 s7, s8 -; GFX8-NEXT: s_cselect_b32 s7, s7, s8 -; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000 -; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s0, s0, s4 -; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000 -; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s1, s1, s4 -; GFX8-NEXT: s_bfe_u32 s4, s6, 0x100000 -; GFX8-NEXT: s_sub_i32 s7, s11, s7 -; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s2, s2, s4 -; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000 -; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000 -; GFX8-NEXT: s_lshl_b32 s4, s4, 16 -; GFX8-NEXT: s_or_b32 s3, s3, s4 +; GFX8-NEXT: v_mov_b32_e32 v7, s15 +; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v3, s9, v3 clamp +; GFX8-NEXT: v_mov_b32_e32 v4, s6 +; GFX8-NEXT: v_mov_b32_e32 v6, s7 +; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v7, s11, v7 clamp +; GFX8-NEXT: v_sub_u16_e64 v5, s10, v5 clamp +; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_sub_u16_e64 v6, s3, v6 clamp +; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_readfirstlane_b32 s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s1, v1 +; GFX8-NEXT: v_readfirstlane_b32 s2, v2 +; GFX8-NEXT: v_readfirstlane_b32 s3, v3 ; GFX8-NEXT: ; return to shader part epilog ; ; GFX9-LABEL: s_usubsat_v8i16: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_mov_b32 s9, 0xffff -; GFX9-NEXT: s_lshr_b32 s11, s4, 16 -; GFX9-NEXT: s_lshr_b32 s8, s0, 16 -; GFX9-NEXT: s_and_b32 s10, s0, s9 -; GFX9-NEXT: s_and_b32 s4, s4, s9 -; GFX9-NEXT: s_cmp_lt_u32 s10, s4 -; GFX9-NEXT: s_cselect_b32 s4, s10, s4 -; GFX9-NEXT: s_cmp_lt_u32 s8, s11 -; GFX9-NEXT: s_cselect_b32 s10, s8, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10 -; GFX9-NEXT: s_lshr_b32 s10, s4, 16 -; GFX9-NEXT: s_sub_i32 s0, s0, s4 -; GFX9-NEXT: s_sub_i32 s4, s8, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX9-NEXT: s_lshr_b32 s10, s5, 16 -; GFX9-NEXT: s_lshr_b32 s4, s1, 16 -; GFX9-NEXT: s_and_b32 s8, s1, s9 -; GFX9-NEXT: s_and_b32 s5, s5, s9 -; GFX9-NEXT: s_cmp_lt_u32 s8, s5 -; GFX9-NEXT: s_cselect_b32 s5, s8, s5 -; GFX9-NEXT: s_cmp_lt_u32 s4, s10 -; GFX9-NEXT: s_cselect_b32 s8, s4, s10 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s8 -; GFX9-NEXT: s_lshr_b32 s8, s5, 16 -; GFX9-NEXT: s_sub_i32 s1, s1, s5 -; GFX9-NEXT: s_sub_i32 s4, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshr_b32 s4, s2, 16 -; GFX9-NEXT: s_and_b32 s5, s2, s9 -; GFX9-NEXT: s_and_b32 s6, s6, s9 -; GFX9-NEXT: s_cmp_lt_u32 s5, s6 -; GFX9-NEXT: s_cselect_b32 s5, s5, s6 -; GFX9-NEXT: s_cmp_lt_u32 s4, s8 -; GFX9-NEXT: s_cselect_b32 s6, s4, s8 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: s_sub_i32 s2, s2, s5 -; GFX9-NEXT: s_sub_i32 s4, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4 -; GFX9-NEXT: s_lshr_b32 s6, s7, 16 -; GFX9-NEXT: s_lshr_b32 s4, s3, 16 -; GFX9-NEXT: s_and_b32 s5, s3, s9 -; GFX9-NEXT: s_and_b32 s7, s7, s9 -; GFX9-NEXT: s_cmp_lt_u32 s5, s7 -; GFX9-NEXT: s_cselect_b32 s5, s5, s7 -; GFX9-NEXT: s_cmp_lt_u32 s4, s6 -; GFX9-NEXT: s_cselect_b32 s6, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: s_sub_i32 s3, s3, s5 -; GFX9-NEXT: s_sub_i32 s4, s4, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp +; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp +; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp +; GFX9-NEXT: v_pk_sub_u16 v3, s3, v3 clamp +; GFX9-NEXT: v_readfirstlane_b32 s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s1, v1 +; GFX9-NEXT: v_readfirstlane_b32 s2, v2 +; GFX9-NEXT: v_readfirstlane_b32 s3, v3 ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: s_usubsat_v8i16: ; GFX10: ; %bb.0: -; GFX10-NEXT: s_mov_b32 s8, 0xffff -; GFX10-NEXT: s_lshr_b32 s9, s0, 16 -; GFX10-NEXT: s_and_b32 s11, s4, s8 -; GFX10-NEXT: s_and_b32 s10, s0, s8 -; GFX10-NEXT: s_lshr_b32 s4, s4, 16 -; GFX10-NEXT: s_cmp_lt_u32 s10, s11 +; GFX10-NEXT: v_pk_sub_u16 v0, s0, s4 clamp +; GFX10-NEXT: v_pk_sub_u16 v1, s1, s5 clamp +; GFX10-NEXT: v_pk_sub_u16 v2, s2, s6 clamp +; GFX10-NEXT: v_pk_sub_u16 v3, s3, s7 clamp ; GFX10-NEXT: ; implicit-def: $vcc_hi -; GFX10-NEXT: s_cselect_b32 s10, s10, s11 -; GFX10-NEXT: s_cmp_lt_u32 s9, s4 -; GFX10-NEXT: s_cselect_b32 s4, s9, s4 -; GFX10-NEXT: s_and_b32 s11, s5, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s10, s4 -; GFX10-NEXT: s_lshr_b32 s5, s5, 16 -; GFX10-NEXT: s_lshr_b32 s10, s4, 16 -; GFX10-NEXT: s_sub_i32 s0, s0, s4 -; GFX10-NEXT: s_sub_i32 s4, s9, s10 -; GFX10-NEXT: s_and_b32 s10, s1, s8 -; GFX10-NEXT: s_lshr_b32 s9, s1, 16 -; GFX10-NEXT: s_cmp_lt_u32 s10, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4 -; GFX10-NEXT: s_cselect_b32 s10, s10, s11 -; GFX10-NEXT: s_cmp_lt_u32 s9, s5 -; GFX10-NEXT: s_cselect_b32 s5, s9, s5 -; GFX10-NEXT: s_and_b32 s11, s6, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s5, s10, s5 -; GFX10-NEXT: s_lshr_b32 s6, s6, 16 -; GFX10-NEXT: s_lshr_b32 s10, s5, 16 -; GFX10-NEXT: s_sub_i32 s1, s1, s5 -; GFX10-NEXT: s_sub_i32 s5, s9, s10 -; GFX10-NEXT: s_and_b32 s10, s2, s8 -; GFX10-NEXT: s_lshr_b32 s9, s2, 16 -; GFX10-NEXT: s_cmp_lt_u32 s10, s11 -; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GFX10-NEXT: s_cselect_b32 s10, s10, s11 -; GFX10-NEXT: s_cmp_lt_u32 s9, s6 -; GFX10-NEXT: s_cselect_b32 s6, s9, s6 -; GFX10-NEXT: s_pack_ll_b32_b16 s6, s10, s6 -; GFX10-NEXT: s_lshr_b32 s10, s6, 16 -; GFX10-NEXT: s_sub_i32 s2, s2, s6 -; GFX10-NEXT: s_sub_i32 s6, s9, s10 -; GFX10-NEXT: s_and_b32 s10, s3, s8 -; GFX10-NEXT: s_and_b32 s8, s7, s8 -; GFX10-NEXT: s_lshr_b32 s9, s3, 16 -; GFX10-NEXT: s_lshr_b32 s7, s7, 16 -; GFX10-NEXT: s_cmp_lt_u32 s10, s8 -; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6 -; GFX10-NEXT: s_cselect_b32 s8, s10, s8 -; GFX10-NEXT: s_cmp_lt_u32 s9, s7 -; GFX10-NEXT: s_cselect_b32 s7, s9, s7 -; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s7 -; GFX10-NEXT: s_lshr_b32 s5, s4, 16 -; GFX10-NEXT: s_sub_i32 s3, s3, s4 -; GFX10-NEXT: s_sub_i32 s4, s9, s5 -; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4 +; GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GFX10-NEXT: v_readfirstlane_b32 s3, v3 ; GFX10-NEXT: ; return to shader part epilog %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs) %cast = bitcast <8 x i16> %result to <4 x i32>