diff --git a/lld/ELF/Arch/PPC64.cpp b/lld/ELF/Arch/PPC64.cpp --- a/lld/ELF/Arch/PPC64.cpp +++ b/lld/ELF/Arch/PPC64.cpp @@ -1035,11 +1035,6 @@ type != R_PPC64_REL24_NOTOC) return false; - // FIXME: Remove the fatal error once the call protocol is implemented. - if (type == R_PPC64_REL24_NOTOC && s.isInPlt()) - fatal("unimplemented feature: external function call with the reltype" - " R_PPC64_REL24_NOTOC"); - // If a function is in the Plt it needs to be called with a call-stub. if (s.isInPlt()) return true; diff --git a/lld/ELF/Thunks.cpp b/lld/ELF/Thunks.cpp --- a/lld/ELF/Thunks.cpp +++ b/lld/ELF/Thunks.cpp @@ -305,6 +305,21 @@ void addSymbols(ThunkSection &isec) override; }; +// PPC64 PC-relative PLT Stub +// When a caller that does not maintain a toc-pointer performs an extern call +// then this stub is needed for: +// 1) Loading the target functions address from the procedure linkage table into +// r12 for use by the target functions global entry point, and into the count +// register with pc-relative instructions. +// 2) Transferring control to the target function through an indirect branch. +class PPC64PCRelPLTStub final : public Thunk { +public: + PPC64PCRelPLTStub(Symbol &dest) : Thunk(dest, 0) {} + uint32_t size() override { return 16; } + void writeTo(uint8_t *buf) override; + void addSymbols(ThunkSection &isec) override; +}; + // A bl instruction uses a signed 24 bit offset, with an implicit 4 byte // alignment. This gives a possible 26 bits of 'reach'. If the call offset is // larger then that we need to emit a long-branch thunk. The target address @@ -880,6 +895,23 @@ isec); } +void PPC64PCRelPLTStub::writeTo(uint8_t *buf) { + int64_t offset = destination.getGotPltVA() - getThunkTargetSym()->getVA(); + if (!isInt<34>(offset)) + fatal("offset must fit in 34 bits to encode in the instruction"); + uint64_t pld = + PLD_R12_NO_DISP | (((offset >> 16) & 0x3ffff) << 32) | (offset & 0xffff); + + writePrefixedInstruction(buf + 0, pld); // pld r12, func@plt@pcrel + write32(buf + 8, MTCTR_R12); // mtctr r12 + write32(buf + 12, BCTR); // bctr +} + +void PPC64PCRelPLTStub::addSymbols(ThunkSection &isec) { + addSymbol(saver.save("__plt_pcrel_" + destination.getName()), STT_FUNC, 0, + isec); +} + void PPC64LongBranchThunk::writeTo(uint8_t *buf) { int64_t offset = in.ppc64LongBranchTarget->getEntryVA(&destination, addend) - getPPC64TocBase(); @@ -1007,7 +1039,8 @@ type == R_PPC64_REL24_NOTOC) && "unexpected relocation type for thunk"); if (s.isInPlt()) - return make(s); + return type == R_PPC64_REL24_NOTOC ? (Thunk *)make(s) + : (Thunk *)make(s); // This check looks at the st_other bits of the callee. If the value is 1 // then the callee clobbers the TOC and we need an R2 save stub. diff --git a/lld/test/ELF/ppc64-pcrel-call-to-extern.s b/lld/test/ELF/ppc64-pcrel-call-to-extern.s new file mode 100644 --- /dev/null +++ b/lld/test/ELF/ppc64-pcrel-call-to-extern.s @@ -0,0 +1,137 @@ +# REQUIRES: ppc +# RUN: extract asmcaller %s -o %t1.s && extract asmcallee %s -o %t2.s && extract lds %s -o %t.lds +# RUN: llvm-mc -filetype=obj -triple=powerpc64le %t1.s -o %t1.o +# RUN: llvm-mc -filetype=obj -triple=powerpc64le %t2.s -o %t2.o +# RUN: ld.lld --shared %t2.o -o %t2.so +# RUN: ld.lld -o %t --script %t.lds %t1.o %t2.so +# RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=SYMBOL +# RUN: llvm-readelf -S -d %t | FileCheck %s --check-prefix=SEC +# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=REL +# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t | FileCheck %s + +# RUN: llvm-mc -filetype=obj -triple=powerpc64 %t1.s -o %t1.o +# RUN: llvm-mc -filetype=obj -triple=powerpc64 %t2.s -o %t2.o +# RUN: ld.lld --shared %t2.o -o %t2.so +# RUN: ld.lld -o %t --script %t.lds %t1.o %t2.so +# RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=SYMBOL +# RUN: llvm-readelf -S -d %t | FileCheck %s --check-prefix=SEC +# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=REL +# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t | FileCheck %s + +## The test is created to check that when a function without TOC access an +## external function, a r12 setup stub is inserted. + +# SYMBOL: Symbol table '.dynsym' contains 4 entries: +# SYMBOL: 1: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [] UND callee_global_TOC +# SYMBOL-NEXT: 2: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND callee_global_stother0 +# SYMBOL-NEXT: 3: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [] UND callee_global_stother1 + +# SYMBOL: Symbol table '.symtab' contains 11 entries: +# SYMBOL: 1: 0000000010010000 0 NOTYPE LOCAL DEFAULT [] 6 caller1 +# SYMBOL-NEXT: 2: 0000000010020000 0 NOTYPE LOCAL DEFAULT [] 7 caller2 +# SYMBOL-NEXT: 3: 0000000010030000 0 NOTYPE LOCAL DEFAULT [] 8 caller3 +# SYMBOL: 5: 0000000010010008 16 FUNC LOCAL DEFAULT 6 __plt_pcrel_callee_global_stother0 +# SYMBOL-NEXT: 6: 0000000010020008 16 FUNC LOCAL DEFAULT 7 __plt_pcrel_callee_global_stother1 +# SYMBOL-NEXT: 7: 0000000010030008 16 FUNC LOCAL DEFAULT 8 __plt_pcrel_callee_global_TOC +# SYMBOL-NEXT: 8: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [] UND callee_global_TOC +# SYMBOL-NEXT: 9: 0000000000000000 0 NOTYPE GLOBAL DEFAULT UND callee_global_stother0 +# SYMBOL-NEXT: 10: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [] UND callee_global_stother1 + +## DT_PLTGOT points to .plt +# SEC: .plt NOBITS 0000000010030140 040140 000028 00 WA 0 0 8 +# SEC: 0x0000000000000003 (PLTGOT) 0x10030140 + +## .plt[0] holds the address of _dl_runtime_resolve, .plt[0]:0x0000000010030140 +## .plt[1] holds the link map, .plt[1]:0x0000000010030148 +## The JMP_SLOT relocations are stored at .plt[2], .plt[3], .plt[4] +## Check that we emit 3 R_PPC64_JMP_SLOT in .rela.plt. +# REL: .rela.plt { +# REL-NEXT: 0x10030150 R_PPC64_JMP_SLOT callee_global_stother0 0x0 +# REL-NEXT: 0x10030158 R_PPC64_JMP_SLOT callee_global_stother1 0x0 +# REL-NEXT: 0x10030160 R_PPC64_JMP_SLOT callee_global_TOC 0x0 +# REL-NEXT: } + +# CHECK-LABEL: : +# CHECK: 10010000: bl 0x10010008 +# CHECK-NEXT: 10010004: blr + +## .plt[2] - 0x10010008 = 0x10030150 - 0x10010008 = 0x20148 = 131400 +# CHECK-LABEL: <__plt_pcrel_callee_global_stother0>: +# CHECK: 10010008: pld 12, 131400(0), 1 +# CHECK-NEXT: 10010010: mtctr 12 +# CHECK-NEXT: 10010014: bctr + +# CHECK-LABEL: : +# CHECK: 10020000: bl 0x10020008 +# CHECK-NEXT: 10020004: blr + +## .plt[3] - 0x10020008 = 0x10030158 - 0x10020008 = 0x10150 = 65872 +# CHECK-LABEL: <__plt_pcrel_callee_global_stother1>: +# CHECK: 10020008: pld 12, 65872(0), 1 +# CHECK-NEXT: 10020010: mtctr 12 +# CHECK-NEXT: 10020014: bctr + +# CHECK-LABEL: : +# CHECK: 10030000: bl 0x10030008 +# CHECK-NEXT: 10030004: blr + +## .plt[4] - 0x10030008 = 0x10030160 - 0x10030008 = 0x158 = 344 +# CHECK-LABEL: <__plt_pcrel_callee_global_TOC>: +# CHECK: 10030008: pld 12, 344(0), 1 +# CHECK-NEXT: 10030010: mtctr 12 +# CHECK-NEXT: 10030014: bctr + +#--- asmcaller +.section .text_caller1, "ax", %progbits +caller1: + .localentry caller1, 1 + bl callee_global_stother0@notoc + blr + +.section .text_caller2, "ax", %progbits +caller2: + .localentry caller2, 1 + bl callee_global_stother1@notoc + blr + +.section .text_caller3, "ax", %progbits +caller3: + .localentry caller3, 1 + bl callee_global_TOC@notoc + blr + +#--- asmcallee +func_extern: + blr + +.globl callee_global_stother0 +callee_global_stother0: + blr + +.globl callee_global_stother1 +callee_global_stother1: + .localentry callee_global_stother1, 1 + ## nop is not needed after bl for R_PPC64_REL24_NOTOC + bl func_extern@notoc + blr + +.globl callee_global_TOC +callee_global_TOC: +.Lfunc_gep1: + addis 2, 12, .TOC.-.Lfunc_gep1@ha + addi 2, 2, .TOC.-.Lfunc_gep1@l +.Lfunc_lep1: + .localentry callee_global_TOC, .Lfunc_lep1-.Lfunc_gep1 + addis 4, 2, global@toc@ha + lwz 3, global@toc@l(4) + blr +global: + .long 0 + .size global, 4 + +#--- lds +SECTIONS { + .text_caller1 0x10010000 : { *(.text_caller1) } + .text_caller2 0x10020000 : { *(.text_caller2) } + .text_caller3 0x10030000 : { *(.text_caller3) } +} diff --git a/llvm/include/llvm/Object/ELF.h b/llvm/include/llvm/Object/ELF.h --- a/llvm/include/llvm/Object/ELF.h +++ b/llvm/include/llvm/Object/ELF.h @@ -50,6 +50,7 @@ enum PPCInstrMasks : uint64_t { PADDI_R12_NO_DISP = 0x0610000039800000, + PLD_R12_NO_DISP = 0x04100000E5800000, MTCTR_R12 = 0x7D8903A6, BCTR = 0x4E800420, };